CN118102572A

CN118102572A - Circuit board structure and manufacturing method thereof

Info

Publication number: CN118102572A
Application number: CN202211491183.2A
Authority: CN
Inventors: 郭俊宏
Original assignee: Unimicron Technology Corp
Current assignee: Unimicron Technology Corp
Priority date: 2022-11-25
Filing date: 2022-11-25
Publication date: 2024-05-28

Abstract

A circuit board structure and a manufacturing method thereof are provided, wherein the manufacturing method comprises the following steps. A temporary carrier plate is provided. And forming a graphene layer on the temporary carrier. And forming a layering structure on the graphene layer. The temporary carrier plate is removed from the graphene layer. And arranging a conductive column on the graphene layer. And performing an oxidation procedure on the graphene layer to enable the graphene layer to comprise an oxidized area which is not shielded by the conductive column and an unoxidized area which is shielded by the conductive column.

Description

Circuit board structure and manufacturing method thereof

Technical Field

The present invention relates to a circuit board, and more particularly to a circuit board structure and a method for manufacturing the same.

Background

The embedded circuit carrier board (Embedded Trace Substrate, ETS) is a technology capable of realizing a circuit board with circuit patterns embedded in an insulating substrate, and is widely used in the related fields because of its advantages in terms of thin lines.

However, the existing embedded circuit carrier board has room for improvement in terms of transmission and integrity of circuit signals. Specifically, the conventional embedded circuit carrier board is a circuit build-up process performed on a core layer (core), in which a metal layer (e.g., copper foil) is interposed between the core layer and the circuit build-up layer, and a process of removing the metal layer is required to expose the outermost circuit pattern of the circuit build-up layer covered by the metal layer. However, the metal layer and the circuit pattern are the same, so that the liquid medicine involved in the removal process can erode the circuit of the circuit pattern indiscriminately, thereby adversely affecting the aspects of signal transmission, integrity and the like of the circuit.

For this reason, non-copper metal is used as the etching stop layer, but the problem that the circuit is corroded during the copper foil removal process cannot be effectively solved, and the etching stop layer of the non-copper metal needs to be removed finally without other added value.

Disclosure of Invention

Accordingly, one of the objectives of the present invention is to provide a circuit board structure and a method for manufacturing the same, which solve the above-mentioned problems associated with the conventional method for etching copper foil.

At least one embodiment of the present invention provides a method for manufacturing a circuit board structure, including the following steps: providing a temporary carrier plate; forming a graphene layer on the temporary carrier plate; forming a build-up structure on the graphene layer; removing the temporary carrier from the graphene layer; arranging a conductive column on the graphene layer; and performing an oxidation procedure on the graphene layer to enable the graphene layer to comprise an oxidized area which is not shielded by the conductive column and an unoxidized area which is shielded by the conductive column.

In at least one embodiment of the present invention, the step of disposing the conductive pillars on the graphene layer includes: setting a patterned mask layer on the graphene layer; and forming a conductive pillar on the graphene layer in a region not covered by the patterned mask layer.

In at least one embodiment of the present invention, the area of the graphene layer not covered by the patterned mask layer corresponds to a portion of one of the patterned circuit layers of the build-up structure closest to the graphene layer.

In at least one embodiment of the present invention, the conductive pillars are electrically connected to one of the patterned circuit layers closest to the graphene layer through the unoxidized regions.

In at least one embodiment of the present invention, the step of forming a build-up structure on the graphene layer includes: and forming a plurality of staggered stacked patterned circuit layers, a plurality of dielectric layers and a plurality of conductive blind holes electrically connected between the patterned circuit layers on the graphene layer.

In at least one embodiment of the present invention, the step of forming the graphene layer on the temporary carrier includes: and forming a graphene layer on the metal film layer of the temporary carrier plate.

In at least one embodiment of the present invention, the step of self-aligning the temporary carrier from the graphene layer includes: removing the substrate of the temporary carrier plate from the metal film layer; and removing the metal film layer from the graphene layer.

In at least one embodiment of the present invention, the above-mentioned manufacturing method further includes the following steps: setting heat source on the conductive column; and making the bonding structure cover the conductive column and be bonded between the heat source and the oxidation region.

In at least one embodiment of the present invention, the above-mentioned manufacturing method further includes the following steps: a heat sink is disposed on the graphene layer such that the heat source is in thermal contact with the heat sink via the graphene layer.

The invention provides a circuit board structure, which comprises a build-up structure, a graphene layer and a conductive column, wherein the graphene layer is arranged on the build-up structure, the conductive column is arranged on the graphene layer, the graphene layer comprises an oxidized region which is not shielded by the conductive column and an unoxidized region which is shielded by the conductive column, and the conductive column is electrically connected with the build-up structure through the unoxidized region.

In at least one embodiment of the present invention, the circuit board structure further includes a heat source, and the heat source is disposed on the conductive column.

In at least one embodiment of the present invention, the circuit board structure further includes a heat spreader, where the heat spreader is disposed on the graphene layer and thermally contacts the heat source through the graphene layer.

In at least one embodiment of the present invention, the conductive pillars include a plurality of conductive pillars, wherein the conductive pillars are interposed between the heat spreader and the unoxidized region.

In at least one embodiment of the present invention, the build-up structure includes a plurality of patterned circuit layers and a plurality of dielectric layers stacked alternately and a plurality of conductive blind vias electrically connected between the patterned circuit layers, and the conductive pillars are electrically connected to one of the patterned circuit layers closest to the graphene layer through the unoxidized regions.

Based on the above, since the temporary carrier plate is provided with the graphene layer as the seed layer for forming the build-up structure, the graphene layer can be used as an etching stop layer in the subsequent process of removing the metal film layer of the temporary carrier plate based on chemical resistance of graphene, so that the liquid medicine involved in removing the metal film layer is effectively prevented from corroding the embedded circuit of the build-up structure, and the embedded circuit of the build-up structure can be ensured to have a complete line shape.

And based on the characteristics of graphene and graphene oxide, the unoxidized region of the graphene layer, which is shielded by the conductive column, can maintain the electrical conduction characteristic so as to realize the required electrical connection between the conductive column and the embedded circuit of the build-up structure, and meanwhile, the part of the graphene layer, which is not shielded by the conductive column, can be oxidized into an oxidized region to generate the electrical insulation characteristic so as to protect other parts of the build-up structure, which are not corresponding to the conductive column. Furthermore, since the graphene layer has good thermal conductivity, in some embodiments, the graphene layer may also serve as a thermal conductive layer between the heat sink and the heat source to effectively conduct heat generated by operation of the heat source to the heat sink. Compared with the traditional method that non-copper metal is used as the etching stop layer and finally needs to be removed without other added values, the graphene layer serving as the etching stop layer can also exert the added values of heat conduction, protection of the build-up structure, local electric conduction and the like after the circuit board structure is completed.

The foregoing description of the disclosure and the following description of the embodiments are provided to illustrate and explain the spirit and principles of the invention and to provide a further explanation of the invention as claimed.

Drawings

Fig. 1 to 10 are schematic flow diagrams illustrating a method for manufacturing a circuit board structure according to an exemplary embodiment of the invention.

Fig. 11 to 14 are schematic flow diagrams illustrating partial steps of a method for manufacturing a circuit board structure according to another exemplary embodiment of the present invention.

Detailed Description

The embodiments set forth below are described in conjunction with the accompanying drawings to provide a thorough understanding of the present invention and to enable a person skilled in the art to practice the same. It is to be understood that the illustrated embodiments are merely exemplary of the scope of the claims and are not intended to limit the scope of the claims. Moreover, for the purposes of illustration and understanding, the features of the drawings may not be to scale. Furthermore, like elements in the accompanying drawings will be denoted by like reference numerals.

In addition, terms such as "substantially," "about," and "substantially" may be used hereinafter to describe a reasonable amount of deviation that may exist for a modified event or circumstance, but still achieve the desired result. It is also possible to use "at least one" in the following to describe the quantity of the object to be described, but it should not be limited to the case of the quantity "only one" unless otherwise explicitly stated. The term "and/or" may also be used hereinafter and should be understood to include all combinations of any and many of the listed items. The terms "forming," "joining," "abutting," "disposing," "configuring," and the like may also be used below to describe the relative positional relationship between various layers, structures, elements, unless otherwise indicated, they may encompass the layers, structures, elements being in direct contact with one another, or there may be one or more intervening layers, structures, elements, etc. between the layers, structures, elements. The terms "first," "second," and the like may also be used below, but this is primarily for distinguishing between elements or operations described in the same language, and not for limiting the order or sequence of elements or operations.

Fig. 1 to 10 are schematic step flow diagrams of a method for manufacturing a circuit board structure according to an exemplary embodiment of the present invention, and fig. 1 to 10 are schematic side sectional views for ease of understanding.

Referring to fig. 1, first, a temporary carrier 10 is provided. The type and material of the temporary carrier 10 can be selected according to practical requirements, and the invention is not limited thereto. For example, in the present embodiment, the temporary carrier 10 may include a substrate 11. The substrate 11 may be, for example, but not limited to, a glass substrate (glass substrate), a silicon substrate (silicon substrate), a ceramic substrate (ceramic substrate), or a combination thereof, having a desired thickness. Optionally, the temporary carrier plate 10 may further include a metal thin film layer 12 disposed on at least one side (or surface) of the substrate 11. The metal film layer 12 may be, but not limited to, a metal layer having a desired thickness, such as a copper foil, but the arrangement, material and thickness of the metal film layer 12 may be adjusted according to practical requirements, and the invention is not limited thereto. In some other embodiments, the other side of the substrate 11 of the temporary carrier 10 may also be provided with a metal film layer 12, but the invention is not limited thereto.

Optionally, in this embodiment, a release layer (RELEASE FILM) R may be disposed between the substrate 11 of the temporary carrier 10 and the metal film layer 12. The release layer R may be, for example, but not limited to, a photo-curable film RELEASE FILM, a thermo-curable film RELEASE FILM, or a laser release film laser debond RELEASE FILM with a suitable thickness, but the setting mode, material and thickness of the release layer R may be adjusted according to practical requirements, and the invention is not limited thereto.

Next, referring to fig. 2, a graphene layer 20 is formed on the temporary carrier 10. Specifically, the graphene layer 20 may be disposed on the metal thin film layer 12 of the temporary carrier plate 10. The Graphene layer 20 may be, but is not limited to, a structure containing a Graphene (Graphene) component, and particularly a structure containing unoxidized Graphene, which has desired characteristics such as thermal conductivity and chemical stability.

In detail, it is known that graphene has excellent electrical conductivity, for example, the resistivity of graphene may be lower than copper or silver (for example, only about 10 ^-6 Ω·cm), and graphene may also have thermal conductivity higher than that of carbon nanotubes and diamond (for example, the thermal conductivity may be as high as 5300W/m·k), and the electron mobility of graphene at normal temperature may be higher than that of carbon nanotubes or silicon crystals (for example, more than 15000cm ²/v·s), and in addition, graphene also has good characteristics such as acid and alkali resistance, chemical resistance of solvent (CHEMICAL RESISTANCE). Therefore, the graphene can be widely applied to heat dissipation and corrosion prevention coatings. It is understood that the presence of graphene may render the graphene layer 20 suitable for separating the metal to be protected from the material corrosive to the metal, so as to provide protection against corrosion. However, it is stated that the arrangement, process, thickness, etc. of the graphene layer 20 can be adjusted and selected according to the actual requirements, and the invention is not limited thereto.

In addition, it is also described that Graphene Oxide (GO) is an oxide of graphene, and it is known that graphene oxide can be converted from electrically conductive to electrically insulating while maintaining similar heat conduction characteristics to graphene, and thus, graphene oxide can be widely used in electrically insulating heat dissipation paint. It is thus seen that when the graphene layer 20 is oxidized, an electrical insulation effect can be achieved between the applied components.

Next, referring to fig. 3, at least one (or one or more) build-up structures 30 may be formed on the graphene layer 20. Specifically, the build-up structure 30 may be formed on the side (or surface) of the graphene layer 20 remote from the metal thin-film layer 12 using any suitable build-up process. In detail, a plurality of patterned circuit layers (patterned circuit layers 31a, 31b, 31c as shown) and a plurality of dielectric layers (dielectric layers 32a, 32b as shown) and conductive blind holes 33a, 33b electrically connected between the patterned circuit layers 31a, 31b, 31c are formed on the side (or surface) of the graphene layer 20 away from the metal film layer 12, so as to form the build-up structure 30. It will be appreciated that the graphene layer 20 may serve as a seed layer (SEED LAYER) for forming the build-up structure 30, providing the surface required for forming the first patterned wiring layer (e.g., patterned wiring layer 31 a) of the build-up structure 30.

It is stated that the build-up structure 30 is for illustration only, and the number, the formation, the material, the thickness, etc. of the patterned circuit layer, the dielectric layer, and the conductive via holes can be adjusted according to the actual requirements, and the invention is not limited thereto.

Furthermore, optionally, a side (or surface) of the build-up structure 30 furthest from the graphene layer 20 or the temporary carrier plate 10 may be provided with a protective layer 40. The material of the protection layer 40 may include, for example, a photosensitive dielectric material, an ABF film, or a polymer resin material, but the invention is not limited thereto, and the protection layer 40 may cover the patterned circuit layer and the dielectric layer (e.g., the patterned circuit layer 31c and the dielectric layer 32 b) of the build-up structure 30 furthest from the graphene layer 20 or the temporary carrier 10, thereby protecting.

Next, referring to fig. 4 to 6, the temporary carrier 10 may be removed from the graphene layer 20. In detail, first, as shown in fig. 4, a disassembling procedure is performed on the temporary carrier 10 to remove the substrate 11 of the temporary carrier 10 from the metal film layer 12. Specifically, the metal film layer 12 of the temporary carrier 10 may be separated from the release layer R, so that the metal film layer 12 is detached from the substrate 11, so as to obtain a structure formed by stacking the build-up structure 30, the graphene layer 20 and the metal film layer 12 in sequence. It is added that the method of separating the metal film layer 12 from the release layer R includes, for example, irradiation of light, heating, applying mechanical force (e.g., peeling) or laser dissociation to reduce the viscosity of the release layer R, but the invention is not limited thereto. It should be further noted that, in other embodiments in which the metal film layer 12 is directly detachable from the substrate 11, the release layer R may not be disposed between the substrate 11 and the metal film layer 12.

Next, optionally, as shown in fig. 5, the structure formed by stacking the build-up structure 30, the graphene layer 20 and the metal thin film layer 12 in sequence in fig. 4 may be reversed to a state in which the metal thin film layer 12 faces a specific direction (e.g., upwards) according to requirements, so as to facilitate the subsequent process.

Next, as shown in fig. 6, the metal thin film layer 12 may be removed from the graphene layer 20. For example, the metal film layer 12 covering the graphene layer 20 may be removed using any common etchant or medicinal liquid. The etchant or the liquid medicine may include, for example, sulfuric acid/hydrogen peroxide (H ₂SO₄/H₂O₂), copper chloride (CuCl ₂), ferric sulfate (Fe ₂(SO₄)₃), and the like, which can be used for etching copper, but the invention is not limited thereto. It will be appreciated that in order to be able to remove the metal film layer 12, the liquid medicine involved is corrosive to metal, but since the graphene layer 20 is resistant to the liquid medicine involved in removing the metal film layer 12, it may provide anti-corrosion protection to the patterned wiring layer of the build-up structure 30 (e.g. the patterned wiring layer 31a closest to the graphene layer 20).

Compared to the conventional method of directly etching the metal film covered on the build-up structure to generate the problem that the chemical solution can erode the embedded circuit without difference, the method of using the graphene layer 20 in the present invention can make the graphene layer 20 act as an etching stop layer (etching stop layer) on the side (or surface) of the build-up structure 30 close to the metal film layer 12, so as to effectively avoid the influence of removing the metal film layer 12 from the build-up structure 30, thereby maintaining the integrity of the patterned circuit layer (e.g. the patterned circuit layer 31 a) of the build-up structure 30, and further ensuring the expected signal transmission and signal integrity of the circuit board structure completed later.

Next, referring to fig. 7 to 8, at least one (or one or more) conductive pillars (conductive pillar) 60 may be disposed on the graphene layer 20, and the number and the positions thereof may be adjusted according to the actual requirements, which is not limited to the present invention. In detail, first, as shown in fig. 7, a patterned mask layer 50 may be disposed on the graphene layer 20. Specifically, after the metal thin film layer 12 is removed from the graphene layer 20, a patterned masking layer 50 may be disposed on a side (or surface) of the graphene layer 20 away from the build-up structure 30. With respect to the formation of the patterned mask layer 50, a photosensitive material may be pressed or coated on the graphene layer 20, and then a portion of the photosensitive material may be removed by means of exposure and development to pattern the photosensitive material, thereby obtaining the patterned mask layer 50.

Here, the patterned mask layer 50 may expose a portion of the graphene layer 20 in a predetermined pattern, for example, the patterned mask layer 50 may expose a portion of the graphene layer 20 corresponding to a portion of the build-up structure 30 in which the patterned circuit layer is patterned. Specifically, as shown, the area of the graphene layer 20 not masked by the patterned masking layer 50 may correspond to a portion of the patterned line layer 31a on the build-up structure 30 closest to the graphene layer 20. However, it should be noted that the patterned mask layer 50 is used to expose the pattern of the graphene layer 20, and the invention is not limited thereto, as the design can be performed according to practical requirements.

Next, a suitable metal material (e.g., copper) may be deposited on the exposed portions of the graphene layer 20 not covered by the patterned masking layer 50, for example, by electroplating electroplating or electroless plating CHEMICAL PLATING, to form the conductive pillars 60. It should be noted that the number and arrangement of the conductive posts 60 can be designed according to practical requirements, and the invention is not limited thereto. In addition, it is added that, since the region of the patterned mask layer 50 where the graphene layer 20 is exposed may correspond to a portion of the patterned circuit layer 31a, the conductive pillars 60 formed herein may also correspond to a portion of the patterned circuit layer 31 a. After the conductive pillars 60 are formed, the patterned masking layer 50 may be removed, as shown in fig. 8, to expose portions of the graphene layer 20 that are originally covered by the patterned masking layer 50, and to leave the conductive pillars 60 corresponding to the portions of the patterned circuit layer 31a on the graphene layer 20.

Next, referring to fig. 9, an oxidation process may be performed on the graphene layer 20. Specifically, since the conductive pillars 60 are locally disposed on the side (or surface) of the graphene layer 20 away from the build-up structure 30, or the side (or surface) of the graphene layer 20 away from the build-up structure 30 may be locally shielded by the conductive pillars 60, during the oxidation process of the graphene layer 20, the portion of the graphene layer 20 not shielded by the conductive pillars 60 may be oxidized, and the portion of the graphene layer 20 shielded by the conductive pillars 60 may not be oxidized due to the shielding by the conductive pillars 60, so that the original state may be maintained, whereby the graphene layer 20 may be converted into the graphene layer 20'. As shown, the graphene layer 20 'has a portion that is oxidized into oxidized regions 22 of oxidized graphene, while the other portion of the graphene layer 20' has unoxidized regions 21 that are unoxidized and remain as graphene. As can be seen from this, the graphene layer 20' is a structure containing both graphene and graphene oxide components; alternatively, the graphene layer 20' refers to a structure including an unoxidized region 21 that is masked by the conductive pillars 60 and an oxidized region 22 that is not masked by the conductive pillars 60. The unoxidized region 21 may extend between the conductive pillars 60 and the patterned circuit layer 31a of the build-up structure 30.

Based on the characteristics of graphene and graphene oxide, after the graphene layer 20 is subjected to an oxidation process to form a graphene layer 20', the region (i.e., the unoxidized region 21) whose composition is still graphene maintains good electrical conductivity and thermal conductivity, and the region (i.e., the oxidized region 22) whose composition changes from graphene to graphene oxide has good thermal conductivity and also changes from electrically conductive to electrically insulating. That is, the unoxidized region 21 of the graphene layer 20 'corresponding to the conductive pillar 60 is thermally conductive and electrically conductive, so that the conductive pillar 60 and the patterned circuit layer 31a of the build-up structure 30 can maintain an electrically conductive state through the unoxidized region 21, but the oxidized region 22 of the graphene layer 20' not corresponding to the conductive pillar 60 is thermally conductive and electrically insulating, so that the oxidized region 22 can form an electrical barrier in the region of the build-up structure 30 not corresponding to the conductive pillar 60.

It is further noted that the oxidation process performed on the graphene layer 20 may be, for example, but not limited to, a plasma oxidation (plasma) process involving oxygen (O ₂) or ozone (O ₃), which may be performed with a suitable oxygen or ozone gas flow, plasma power, and plasma time, depending on the oxidation requirements. In this case, the fabricator may provide plasma in a specific direction to facilitate the conductive unoxidized region 21 extending from the conductive pillar 60 to the portion of the patterned circuit layer 31a of the build-up structure 30 where the corresponding connection is required.

Through the above steps, the circuit board structure 1 formed by stacking the build-up structure 30, the graphene layer 20' and the conductive pillars 60 is completed.

Next, referring to fig. 10, a heat source 81 can be selectively disposed on the circuit board structure 1 according to the requirement. Specifically, the heat source 81 can be selectively disposed on the conductive posts 60 of the circuit board structure 1. The heat source 81 may be, but is not limited to, any suitable chip (chip) or other electronic component that may have one or more pins 811 that may be electrically connected to the conductive pillars 60. Thereby, the heat source 81 can be electrically connected to the patterned circuit layer 31a of the build-up structure 30 via the conductive pillars 60 and the unoxidized regions 21 of the graphene layer 20'. Therefore, the graphene layer 20' can be used as a conductive layer on the build-up structure 30 where the thermal source 81 needs to be electrically connected to effectively realize the electrical connection between the build-up structure 30 and the thermal source 81.

It is to be noted that, the pins 811 of the heat source 81 and the conductive posts 60 may be bonded by, for example, providing solder balls (solder balls) 61, but the present invention is not limited thereto; for example, in other embodiments, the solder balls between the pins 811 of the heat source 81 and the conductive posts 60 can be omitted and changed to direct contact.

In addition, after the heat source 81 is configured to be abutted against the conductive pillars 60, a bonding structure 70 may be provided to cover the conductive pillars 60 and bond between the heat source 81 and the oxidation zone 22. The material of the bonding structure 70 may be, for example, but not limited to, epoxy or other suitable insulating material, but the present invention is not limited thereto. In the oxidation region 22 of the graphene layer 20', the graphene oxide and the cured epoxy resin have good bonding strength, so that the stability of the heat source 81 on the circuit board structure 1 is improved, and the electrical connection between the heat source 81 and the conductive column 60 is ensured.

Optionally, a heat sink (cooler) 82 may also be provided on the circuit board structure 1. Specifically, the heat spreader 82 may be selectively disposed at the oxidized region 22 of the graphene layer 20'. The heat sink 82 may be, for example but not limited to, any passive or active component that facilitates heat dissipation, for example, the heat sink 82 may be a heat sink fin, but the invention is not limited thereto. In addition, one side of the heat sink 82 may be provided with a thermally conductive structure 90, which thermally conductive structure 90 may include, for example, but not limited to, copper or other materials that facilitate thermal conduction. In addition, after the heat spreader 82 thermally contacts the oxidized region 22 of the graphene layer 20' with the thermally conductive structure 90, the bonding structure 70 may be provided to cover the heat spreader 82 on the circuit board structure 1. In addition, good bonding strength can be formed between the cured material of the bonding structure 70 and the graphene oxide of the oxidized region 22 of the graphene layer 20', so as to help to improve the stability of the heat spreader 82 on the circuit board structure 1.

With this configuration, the heat energy generated by the operation of the heat source 81 can be transferred to the heat sink 82 via the conductive pillars 60, the graphene layer 20 'and the heat conductive structure 90, so that the graphene layer 20' can serve as a heat conductive layer between the conductive pillars 60 and the heat sink 82 to effectively conduct the heat of the heat source 81 to the heat sink 82, thereby effectively dissipating the heat of the heat source 81.

The above is only one exemplary embodiment of the circuit board structure of the present invention, and those skilled in the art can make the required adjustments or modifications to the circuit board structure according to the actual requirements. For example, please refer to fig. 11-14, which illustrate a schematic flow chart of a part of steps of a method for manufacturing a circuit board structure 1' according to another exemplary embodiment of the present invention, but it should be noted that the following embodiments only differ from the foregoing embodiments in that the distribution of the patterned circuit layer of the build-up structure and the patterned mask layer expose the local graphene layer in different patterns, and therefore, for the sake of brevity, only the differences between the described embodiments and the foregoing embodiments will be described, and the steps related to the two embodiments may be omitted.

First, as in fig. 11, a patterned masking layer 50' may be disposed on the graphene layer 20. The patterned masking layer 50 'additionally exposes regions of the graphene layer 20 for subsequent steps to dispose the heat spreader 82, as compared to the patterned masking layer 50 of the previous embodiment, for example, the patterned masking layer 50' may selectively expose localized regions of the patterned line layer 31a 'of the graphene layer 20 that are not in direct contact with the build-up structure 30' (e.g., may selectively expose localized regions of the dielectric layer 32a 'of the graphene layer 20 that are in direct contact with the build-up structure 30').

Next, one or more conductive pillars (conductive pillar) 60 and conductive pillars 60 'may be formed on the portion of the graphene layer 20 not covered by the patterned masking layer 50', and then, after the patterned masking layer 50 'is removed, as shown in fig. 12, the portion of the graphene layer 20 originally covered by the patterned masking layer 50' is exposed, and the conductive pillars 60 and 60 'corresponding to the portion of the patterned circuit layer 31a are left on the graphene layer 20, as shown in the drawings, the conductive pillars 60 may be located at positions corresponding to the patterned circuit layer 31a' of the build-up structure 30', and the conductive pillars 60' may be located at positions corresponding to the patterned circuit layer 31a 'of the non-build-up structure 30'.

Next, referring to fig. 13, an oxidation process may be performed on the graphene layer 20, so that a portion of the graphene layer 20 not covered by the conductive pillars 60 and 60' may be oxidized, thereby converting the graphene layer 20 into a graphene layer 20 partially having unoxidized regions 21 and 21' and partially having oxidized regions 22 '. As shown in the figure, the unoxidized region 21 refers to the portion of the patterned circuit layer 31a of the graphene layer 20″ that is not oxidized and extends between the conductive pillars 60 and the build-up structure 30', the unoxidized region 21' refers to the portion of the graphene layer 20″ that is not oxidized and extends between the conductive pillars 60' and the dielectric layer 32a ' of the build-up structure 30', and the oxidized region 22' refers to the portion of the graphene layer 20″ that is not shielded by the conductive pillars 60 and 60' and undergoes oxidation. In this way, the circuit board structure 1' formed by stacking the build-up structure 30', the graphene layer 20 "and the conductive pillars 60 and 60' is completed.

Next, referring to fig. 14, the heat source 81 may be disposed on the conductive pillar 60 and secured in position by the bonding structure 70, and the heat spreader 82 may be directly in thermal contact with the conductive pillar 60' without the aforementioned heat conductive structure 90 and secured in position by the bonding structure 70, that is, the conductive pillar 60' may be interposed between the heat spreader 82 and the unoxidized region 21 '. With this configuration, the heat energy generated by the operation of the heat source 81 can be transferred to the heat sink 82 via the conductive pillars 60, the unoxidized regions 21, the oxidized regions 22' and 21', and the conductive pillars 60', so that the graphene layer 20 "can also serve as a heat conducting layer between the heat source 81 and the heat sink 82 to effectively conduct the heat of the heat source 81 to the heat sink 82, thereby effectively dissipating the heat of the heat source 81.

According to the step flow of the manufacturing method of the circuit board structure in the foregoing embodiment, since the temporary carrier is provided with the graphene layer as the seed layer for forming the build-up structure, the graphene layer can be used as an etching stop layer in the subsequent process of removing the metal film layer of the temporary carrier based on the chemical resistance of the graphene, so as to effectively prevent the liquid medicine involved in removing the metal film layer from corroding the embedded circuit of the build-up structure, thereby ensuring that the embedded circuit of the build-up structure has a complete line shape.

[ Symbolic description ]

1,1' Circuit board structure

10 Temporary carrier plate

11 Substrate

12 Metal film layer

20,20' Graphene layers

21,21': Unoxidized region

22,22': Oxidation zone

30,30' Layered structure

31A,31a',31b,31c patterning the wiring layer

32A,32a',32b dielectric layer

33A,33b conductive blind via

40 Protective layer

50,50' Patterning mask layer

60,60' Conductive column

61 Solder ball

70 Joint structure

81 Heat source

811 Pin

82 Radiator

90, A thermally conductive structure.

Claims

1. A circuit board structure, comprising:

a build-up structure;

The graphene layer is arranged on the layer-adding structure; and

At least one conductive column arranged on the graphene layer;

the graphene layer comprises an oxidized region which is not shielded by the at least one conductive column and an unoxidized region which is shielded by the at least one conductive column, and the at least one conductive column is electrically connected with the build-up structure through the unoxidized region.

2. The circuit board structure of claim 1, further comprising a heat source disposed on the at least one conductive post.

3. The circuit board structure of claim 2, further comprising a heat spreader disposed on the graphene layer and in thermal contact with the heat source via the graphene layer.

4. The circuit board structure of claim 3, wherein the at least one conductive pillar comprises a plurality of conductive pillars, wherein the conductive pillars are interposed between the heat spreader and the unoxidized region.

5. The circuit board structure of claim 1, wherein the build-up structure comprises a plurality of patterned circuit layers and a plurality of dielectric layers stacked alternately and a plurality of conductive blind vias electrically connected between the patterned circuit layers, and the at least one conductive pillar is electrically connected to one of the patterned circuit layers closest to the graphene layer via the unoxidized region.

6. The manufacturing method of the circuit board structure is characterized by comprising the following steps:

Providing a temporary carrier plate;

forming a graphene layer on the temporary carrier plate;

Forming a build-up structure on the graphene layer;

removing the temporary carrier from the graphene layer;

At least one conductive column is arranged on the graphene layer; and

And performing an oxidation procedure on the graphene layer to enable the graphene layer to comprise an oxidized area which is not shielded by the at least one conductive column and an unoxidized area which is shielded by the at least one conductive column.

7. The method of claim 6, wherein disposing at least one conductive pillar on the graphene layer comprises:

setting a patterned mask layer on the graphene layer; and

And forming the at least one conductive column on the graphene layer in a region not covered by the patterned masking layer.

8. The method of claim 7, wherein the area of the graphene layer not covered by the patterned masking layer corresponds to a portion of one of the patterned circuit layers of the build-up structure closest to the graphene layer.

9. The method of claim 7, wherein the at least one conductive pillar is electrically connected to one of the patterned circuit layers of the build-up structure closest to the graphene layer via the unoxidized region.

10. The method of claim 6, wherein forming the build-up structure on the graphene layer comprises:

and forming a plurality of staggered stacked patterned circuit layers, a plurality of dielectric layers and a plurality of conductive blind holes electrically connected between the patterned circuit layers on the graphene layer.

11. The method of claim 6, wherein the step of forming the graphene layer on the temporary carrier comprises:

and forming the graphene layer on the metal film layer of the temporary carrier plate.

12. The method of claim 11, wherein the step of removing the temporary carrier from the graphene layer comprises:

Removing the substrate of the temporary carrier plate from the metal film layer; and

The metal film layer is removed from the graphene layer.

13. The method of manufacturing of claim 6, further comprising:

Providing a heat source on the at least one conductive post; and

The bonding structure is made to cover the at least one conductive column and is bonded between the heat source and the oxidation region.

14. The method of manufacturing of claim 13, further comprising:

A heat sink is disposed on the graphene layer such that the heat source is in thermal contact with the heat sink via the graphene layer.