CN118101395A - Receiver and SerDes system based on frequency domain processing - Google Patents

Abstract

The invention discloses a receiver based on frequency domain processing and a SerDes system. In order to solve the problem of complexity and clock jitter tolerance of CDR loop, the invention is based on the receiver of the frequency domain processing and includes main route and clock data recovery loop; the main path performs frequency domain filtering based on discrete Fourier transform; and the clock data recovery loop is used for recovering the clock and the data based on the signals after the frequency domain filtering is completed, and the main path is used for carrying out analog-to-digital conversion based on the clock signals recovered by the clock data recovery loop and the recovered data signals. The invention can reduce the complexity of the system and effectively control the delay and jitter tolerance of the CDR loop. The invention is suitable for the field of high-speed wired communication.

Description

Receiver and SerDes system based on frequency domain processing

Technical Field

The invention relates to the field of high-speed wired communication, in particular to a receiver and a SerDes system based on frequency domain processing.

Background

At present, common communication modes in the industry include wired communication and wireless communication, and the two communication modes have significant differences in architecture design of a transmitter and a receiver due to different physical media propagated by the two communication modes.

Serializers and deserializers (Serializer and Deserializer, serDes) are common high-speed wired communication technologies. The SerDes technique typically requires link equalization, while the de-emphasis technique, the pre-emphasis technique, is a link equalization method commonly used to implement a feedback decision equalizer (Decision Feedback Equalizer, DFE) and a forward feedback equalizer (Feed Forward Equalizer, FFE). Further, the weighting technique can be divided into: the forward de-emphasis, the forward pre-emphasis, the backward de-emphasis and the backward pre-emphasis are respectively used for solving the problems of forward crosstalk and backward crosstalk in a communication link. The present invention is directed to a SerDes system including a DFE.

The SerDes system is a typical digital-analog hybrid system that does not transmit a clock signal, integrates a clock data recovery (Clock and Data Recovery, CDR) circuit at the receiving end, uses the CDR circuit to extract the clock from the edge information of the data, and finds the optimal sampling location. The SerDes system reduces the required transmission channels and improves the anti-interference capability of signals at the same time by embedding clocks in the data lines, thereby greatly reducing the communication cost, and further improving the signal quality by a weighting or equalizing technology so as to realize high-speed long-distance transmission, thus having wide application in the fields of computer networks, communication systems, data storage, graphic display and the like.

FIG. 1 is a diagram of a conventional SerDes system architecture, including a transmitter and a receiver. The transmitter converts parallel data into serial data by using a serializer, the serial data is driven by a driver to be output, a data link transmits signals output by the transmitter to the receiver, and the receiver processes the received serial data through an analog front end and then converts the serial data into parallel data to be output by using a deserializer.

Fig. 2 is a schematic diagram of a SerDes system receiver according to the prior art. In the receiver, the clock data recovery circuit is responsible for clock recovery, analog-to-digital converter (Analogy Digital Converter, ADC) performs analog-to-digital conversion and phase adjustment based on the clock and data recovered by the CDR circuit. After the signals sampled by the ADC are processed by the blocking and overlapping adding module, the signals are balanced by a forward feedback equalizer (Feed Forward Equalizer, FFE) and a Floating Tap forward equalizer (Floating Tap Feed Forward Equalizer, floating Tap FFE), the signal quality is further improved by a feedback decision equalizer (Decision Feedback Equalizer, DFE) to obtain better performance, meanwhile, the FFE and the Floating Tap forward equalizer are updated by a first updating module, and the DFE is updated by a second updating module.

However, as the baud rate of the transmitted signal increases, the channel attenuation increases, and the number of taps required for FFE, floating tap forward equalizer, and DFE used in order to suppress the intersymbol interference of the signal increases, so that the transmission delay and the complexity of the chip increase. Meanwhile, in order to improve the quality of the input signal of the CDR circuit, a feedforward equalizer with a smaller tap number is usually added in front of the CDR circuit, such as the preprocessing equalizer shown in fig. 2 and the corresponding preprocessing update module thereof, and a second block and overlap adding module to be added for preprocessing, thereby increasing the delay and complexity on the clock recovery loop. As the baud rate of the system increases and the channel attenuation increases, the tolerance of the system to clock jitter becomes smaller and smaller, and on the basis of improving the signal quality, the tolerance requirement to delay is also smaller and smaller, and in the scenario of high baud rate and high attenuation, the current SerDes architecture must reduce delay and chip complexity/power consumption if better performance is to be obtained.

In summary, how to reduce the complexity of CDR loop and the problem of poor tolerance of clock jitter in the high baud rate and high attenuation scenario, so as to reduce the delay and the chip complexity/power consumption of SerDes system, is a technical problem that needs to be solved urgently in the field.

Disclosure of Invention

In order to alleviate or partially alleviate the above technical problem, the solution of the present invention is as follows:

a receiver based on frequency domain processing, comprising a main path and a clock data recovery loop;

The main path is used for transforming the input signal of the receiver after analog-to-digital conversion from a time domain to a frequency domain, then performing frequency domain filtering, transforming the signal after the frequency domain filtering from the frequency domain to the time domain, and then performing feedback equalization and decision processing;

And the main path carries out analog-to-digital conversion based on the clock signal recovered by the clock data recovery loop and the recovered data signal.

The main path transforms the input signal of the receiver after analog-to-digital conversion from a time domain to a frequency domain by using discrete Fourier transform;

The main path transforms the frequency domain filtered signal from the frequency domain to the time domain using an inverse discrete fourier transform.

Further, the main path performs discrete fourier transform after the receiver input signal subjected to analog-to-digital conversion is segmented by the segmentation module.

Further, the main path includes:

The analog-to-digital converter is used for performing analog-to-digital conversion on the input signal of the receiver;

the input end of the blocking module is coupled with the output end of the analog-to-digital converter and is used for blocking the digital signal after analog-to-digital conversion;

the input end of the discrete Fourier transform module is coupled with the output end of the blocking module so as to transform the signals after blocking from the time domain to the frequency domain;

The input end of the frequency domain filtering module is coupled with the output end of the Fourier transform module so as to carry out frequency domain filtering;

the input end of the inverse discrete Fourier transform module is coupled with the output end of the frequency domain filtering module and is used for transforming the signals after frequency domain filtering back to the time domain;

and the input end of the feedback decision equalizer is coupled with the output end of the inverse discrete Fourier transform module to perform feedback equalization and decision processing.

Further, the main path further comprises a frequency domain filtering updating module, and the frequency domain filtering updating module is used for updating frequency domain coefficients or/and frequency domain errors of the frequency domain filtering module.

Further, the main path further includes:

and the feedback decision equalization updating module is used for updating the equalization coefficient or/and the equalization error of the feedback decision equalizer.

Further, the clock data recovery loop comprises a clock data recovery module, an input end of the clock data recovery module is coupled with an output end of the inverse discrete fourier transform module, and a clock signal recovered by the clock data recovery module and a recovered data signal are fed back to the analog-to-digital converter.

Further, the bandwidth of the discrete Fourier transformed signal is less than or equal toAnd the center frequency satisfies the following relationship:

，

Wherein m=0, 1,2, …, (M-1), M is the number of points after discrete fourier transform, For sampling frequency,/>Is the center frequency.

The invention also relates to a SerDes system based on frequency domain processing, comprising a transmitter, and a receiver as described before; the receiver receives the signal output by the transmitter.

Further, the transmitter includes:

a data generator for generating a digital signal;

the input end of the mapper is coupled with the output end of the data generator and is used for mapping the digital signal;

a transmitter forward feedback equalizer, the input end of the transmitter forward feedback equalizer is coupled with the output end of the mapper, and is used for performing time domain filtering;

And the input end of the digital-to-analog converter is coupled with the output end of the transmitter forward feedback equalizer and is used for carrying out digital-to-analog conversion.

The technical scheme of the invention has one or more of the following beneficial technical effects:

(1) The invention uses a frequency domain filtering module to replace a plurality of modules (such as a preprocessing equalizer, a forward feedback equalizer and a floating tap forward equalizer in a CDR loop in a receiver in the prior art) in time domain equalization, thereby greatly reducing the complexity of the system.

(2) And the result of the transformation back to the time domain after the frequency domain filtering on the CDR loop multiplexing main path is recovered based on the signal after the frequency domain filtering, so that a preprocessing equalizer and a coefficient updating module thereof on the CDR loop are omitted, and the delay and jitter tolerance of the loop are effectively controlled while the quality of the input signal of the CDR loop is improved.

Furthermore, other advantageous effects that the present invention has will be mentioned in the specific embodiments.

Drawings

FIG. 1 is a diagram of a conventional SerDes system architecture;

FIG. 2 is a schematic diagram of a prior art ADC-based SerDes system receiver;

fig. 3 is a schematic overview of the receiver of the present invention;

FIG. 4 is a schematic diagram of a receiver based on frequency domain processing in a SerDes system of the present invention;

Fig. 5 is a schematic diagram of a transmitter in a SerDes system based on frequency domain processing in accordance with the invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Numerous specific details are set forth in the following description in order to provide a better understanding of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.

The invention carries out frequency domain equalization based on discrete Fourier transform (Discrete Fourier Transform, DFT), and compensates the amplitude-frequency characteristic and the group delay characteristic of the actual channel by utilizing the frequency characteristic of the adjustable filter, so that the total frequency characteristic of the whole system meets the condition of no intersymbol interference transmission.

Fig. 3 is a schematic overview of the receiver of the present invention, including a main path and a clock data recovery loop.

The main path comprises a frequency domain equalization processing module for performing frequency domain equalization processing. Specifically, the input signal of the receiver after analog-to-digital conversion is transformed from the time domain to the frequency domain, then frequency domain filtering is performed, and after the signal after the frequency domain filtering is transformed from the frequency domain to the time domain, feedback equalization and decision processing are performed.

And simultaneously, a clock data recovery loop is used for recovering the clock and the data based on the signal converted from the frequency domain to the time domain, and the main path is used for carrying out analog-to-digital conversion based on the clock signal recovered by the clock data recovery loop and the recovered data signal.

The frequency domain filtering module on the main path has larger tap number, so the quality of the input signal of the CDR circuit is improved more. In addition, because the delay of the frequency domain filtering is irrelevant to the tap number, the main path selects a proper DFT point number, so that the delay and jitter tolerance of the CDR loop can be effectively controlled on the basis of improving the signal quality, and the time domain signal output after IDFT is beneficial to continuing other processes of clock recovery of the CDR loop.

Fig. 4 is a schematic diagram of a receiver based on frequency domain processing in a preferred embodiment of the invention. After analog-to-digital conversion is carried out on a receiver input signal by an ADC, the receiver input signal is segmented on a main path, and then is converted from a time domain to a frequency domain through DFT processing; frequency domain filtering is carried out on the signals after DFT conversion, and coefficient updating or/and error updating of the frequency domain is carried out; after the filtering is completed, the signal is converted back to the time domain by inverse discrete fourier transform (INVERSE DISCRETE Fourier Transform, IDFT), and DFE and decision processing is performed by using a feedback decision equalizer. Meanwhile, on the clock data recovery loop, the signals converted into the time domain after the completion of the filtering are obtained from the main path to replace a preprocessing equalizer and a coefficient updating module thereof before the CDR circuit in the prior art.

Specifically, the main path comprises an ADC, a blocking module, a discrete Fourier transform module, a frequency domain filtering module, an inverse discrete Fourier transform and a feedback decision equalizer which are sequentially coupled.

And the ADC is used for carrying out analog-to-digital conversion on the input signal of the receiver.

And the input end of the blocking module is coupled with the output end of the analog-to-digital converter and is used for blocking the digital signal after analog-to-digital conversion.

And the discrete Fourier transform module is used for carrying out DFT processing on the segmented signals so as to transform the segmented signals from the time domain to the frequency domain.

And the input end of the frequency domain filtering module is coupled with the output end of the Fourier transform module so as to carry out frequency domain filtering.

An inverse discrete fourier transform (INVERSE DISCRETE Fourier Transform, IDFT) module converts the frequency domain filtered signal back to the time domain.

And the input end of the feedback decision equalizer is coupled with the output end of the inverse discrete Fourier transform module and is used for carrying out feedback equalization and decision processing on the IDFT signals.

Further, the receiver based on frequency domain processing of the invention further comprises a frequency domain filtering updating module, which is used for updating the frequency domain coefficients or/and the frequency domain errors of the frequency domain filtering module.

Further, the receiver based on frequency domain processing of the invention further comprises a feedback decision equalization updating module for updating the equalization coefficient or/and the equalization error of the DFE.

Meanwhile, in the clock data recovery loop, the input of the CDR circuit is coupled with the output of the inverse discrete Fourier transform module, clock and data recovery is performed based on signals converted into a time domain after frequency domain filtering is completed, and the recovered clock signals and the recovered data signals are fed back to the ADC. Wherein the ADC converts an analog signal received by the receiver into a digital signal based on the recovered clock signal and the recovered data signal of the CDR circuit.

Preferably, the CDR circuit is implemented based on a Mueller-Mueller phase detector (Mueller-Muller phase detector, MMPD).

Fig. 5 is a schematic diagram of a transmitter in a SerDes system based on frequency domain processing in accordance with the invention. The transmitter includes a data generator, a mapper, a transmitter forward feedback equalizer (TRANSCEIVER FEED Forward Equalizer, TX FFE), a digital-to-analog converter (Digital to Analog Converter, DAC) coupled in sequence. The digital signal generated by the data generator is mapped by the mapper and filtered by the transmitter forward feedback equalizer and then sent to the DAC for conversion, and the output of the DAC is transmitted to the receiver through the link.

Specifically, a data generator for generating a digital signal; the input end of the mapper is coupled with the output end of the data generator and is used for carrying out data mapping; a transmitter forward feedback equalizer, the input end of the transmitter forward feedback equalizer is coupled with the output end of the mapper, and is used for performing time domain filtering; and the input end of the digital-to-analog converter is coupled with the output end of the transmitter forward feedback equalizer and is used for carrying out digital-to-analog conversion.

Optionally, the invention properly designs the transmitter feedforward equalizer, adopts the transmitter feedforward equalizer coefficient corresponding to the DFT and IDFT conversion point number M, can avoid spectrum leakage, and does not increase extra delay and complexity while maintaining enough filtering precision. Specifically, the DFT equivalent is a set of narrow band filters, each with a center frequency ofWith a bandwidth of/>. Each filter is shaped as a sinc function, also known as a sinc function. When the receiver input signal falls on one of the set of narrow band filters, i.e. the bandwidth of the discrete fourier transformed signal is less than or equal to/>And the center frequency satisfies the following relationship:

，

Wherein m=0, 1,2, …, (M-1), M is the number of points after discrete fourier transform, For sampling frequency,/>Is the center frequency. Therefore, the frequency spectrum of the input signal of the narrow-band filter and the frequency spectrum of the input signal of the receiver are basically overlapped, and the frequency spectrum leakage is solved. For example, by bandwidth filtering the signal to near fs/M with a center frequency set to 0 while meeting the bandwidth conditions of each equalizer on the main path, spectrum leakage can be avoided without adding additional delay and complexity while maintaining sufficient filtering accuracy.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (9)

1. A receiver based on frequency domain processing is applied to the field of high-speed wired communication, and is characterized in that:

The clock data recovery circuit comprises a main path and a clock data recovery loop;

The main path is used for transforming the input signal of the receiver after analog-to-digital conversion from a time domain to a frequency domain, then performing frequency domain filtering, transforming the signal after the frequency domain filtering from the frequency domain to the time domain, and then performing feedback equalization and decision processing;

the clock data recovery loop recovers the clock and the data based on the signal converted from the frequency domain to the time domain, and the main path performs analog-to-digital conversion based on the clock signal recovered by the clock data recovery loop and the recovered data signal;

the main path transforms the input signal of the receiver after analog-to-digital conversion from a time domain to a frequency domain by using discrete Fourier transform; the main path transforms the frequency domain filtered signal from the frequency domain to the time domain using an inverse discrete fourier transform.

2. The receiver based on frequency domain processing of claim 1, wherein:

The main path uses a blocking module to block the input signal of the receiver after analog-to-digital conversion and then performs discrete Fourier transform.

3. The frequency domain processing based receiver of claim 2, wherein the main path comprises:

The analog-to-digital converter is used for performing analog-to-digital conversion on the input signal of the receiver;

the input end of the blocking module is coupled with the output end of the analog-to-digital converter and is used for blocking the digital signal after analog-to-digital conversion;

the input end of the discrete Fourier transform module is coupled with the output end of the blocking module so as to transform the signals after blocking from the time domain to the frequency domain;

The input end of the frequency domain filtering module is coupled with the output end of the Fourier transform module so as to carry out frequency domain filtering;

the input end of the inverse discrete Fourier transform module is coupled with the output end of the frequency domain filtering module and is used for transforming the signals after frequency domain filtering back to the time domain;

and the input end of the feedback decision equalizer is coupled with the output end of the inverse discrete Fourier transform module to perform feedback equalization and decision processing.

4. A receiver based on frequency domain processing as claimed in claim 3, characterized in that:

the main path further comprises a frequency domain filtering updating module, and the frequency domain filtering updating module is used for updating frequency domain coefficients or/and frequency domain errors of the frequency domain filtering module.

5. The frequency domain processing based receiver of claim 4, wherein the main path further comprises:

and the feedback decision equalization updating module is used for updating the equalization coefficient or/and the equalization error of the feedback decision equalizer.

6. The frequency domain processing based receiver according to any of claims 3 to 5, characterized in that:

the clock data recovery loop comprises a clock data recovery module, wherein the input end of the clock data recovery module is coupled with the output end of the inverse discrete Fourier transform module, and a clock signal recovered by the clock data recovery module and a recovered data signal are fed back to the analog-to-digital converter.

7. The frequency domain processing based receiver of claim 6, wherein:

The bandwidth of the signal after the discrete Fourier transform is less than or equal to And the center frequency satisfies the following relationship:

；

Wherein m=0, 1,2, …, (M-1), M is the number of points after discrete fourier transform, For sampling frequency,/>Is the center frequency.

8. A SerDes system based on frequency domain processing, characterized by:

The SerDes system comprising a transmitter and a receiver based on frequency domain processing as claimed in any one of claims 1 to 7;

the receiver based on frequency domain processing receives the signal output by the transmitter.

9. The frequency domain processing based SerDes system of claim 8, wherein the transmitter comprises:

a data generator for generating a digital signal;

the input end of the mapper is coupled with the output end of the data generator and is used for mapping the digital signal;

a transmitter forward feedback equalizer, the input end of the transmitter forward feedback equalizer is coupled with the output end of the mapper, and is used for performing time domain filtering;

And the input end of the digital-to-analog converter is coupled with the output end of the transmitter forward feedback equalizer and is used for carrying out digital-to-analog conversion.