CN118101396A - Information receiving method and SerDes system based on ADC - Google Patents

Abstract

The invention discloses an information receiving method and a SerDes system based on an ADC. In order to reduce the technical problems of high complexity of a forward feedback equalizer of a high-baud rate and large delay of a transmission signal, the receiver of the SerDes system based on the ADC performs equalization in a frequency domain, performs filtering in the frequency domain after transforming a signal from the time domain to the frequency domain by using discrete Fourier transform, and then converts the filtered signal into the time domain by using an inverse discrete Fourier transform module to perform feedback equalization decision processing. The invention converts the time domain convolution into the frequency domain multiplication, equalizes in the frequency domain, reduces the computational complexity and reduces the delay of signals. The invention is suitable for the field of high-speed wired communication.

Description

Information receiving method and SerDes system based on ADC

Technical Field

The invention relates to the field of high-speed wired communication, in particular to an information receiving method and a SerDes system based on an ADC (analog to digital converter).

Background

At present, common communication modes in the industry include wired communication and wireless communication, and the two communication modes have significant differences in architecture design of a transmitter and a receiver due to different physical media propagated by the two communication modes.

Serializers and deserializers (Serializer and Deserializer, serDes) are common high-speed communication techniques. The SerDes technique typically requires link equalization, while the de-emphasis technique, the pre-emphasis technique, is a link equalization method commonly used to implement a feedback decision equalizer (Decision Feedback Equalizer, DFE) and a forward feedback equalizer (Feed Forward Equalizer, FFE). Further, the weighting technique can be divided into: the forward de-emphasis, the forward pre-emphasis, the backward de-emphasis and the backward pre-emphasis are respectively used for solving the problems of forward crosstalk and backward crosstalk in a communication link. The present invention is directed to a SerDes system including a DFE.

The SerDes system fully utilizes the channel capacity of the transmission medium, can reduce the number of required transmission channels and device pins, and improves the transmission speed and the anti-interference capability of signals, thereby greatly reducing the communication cost and being more and more widely applied in the future with high bandwidth and low cost. The main features of the SerDes system include: the clock is embedded in the data line, clock signals do not need to be transmitted, high-speed long-distance transmission can be realized through a weighting or equalization technology, and fewer chip pins and the like are used.

Fig. 1 is a diagram of a conventional SerDes system based on an analog-to-digital converter (Analog Digital Converter, ADC) that includes a transmitter and a receiver, with the transmitter signal being transmitted over a link to the receiver. In the receiver, a clock data recovery (Clock and Data Recovery, CDR) circuit is responsible for clock recovery, ADC analog-to-digital conversion and phase adjustment based on the clock and data recovered by the CDR circuit. After the signals sampled by the ADC are processed by the block and overlap adding module, the signals are balanced by the FFE, a Floating Tap forward equalizer (Floating Tap Feed Forward Equalizer, a Floating Tap FFE) and the DFE, and meanwhile, the FFE and the Floating Tap FFE update the balance coefficient by the time domain coefficient updating module, and the DFE updates the balance coefficient by the DFE updating module. In the case of high-speed SerDes systems where the channel attenuation is relatively large, it is often necessary to use a time domain FFE with a large number of taps and a streaming Tap FFE to equalize the intersymbol interference (Inter-Symbol Interference, ISI) of the signal, and even further improve the signal quality with DFE for better performance.

As the baud rate of signals increases, the number of taps required for each equalizer used increases, resulting in increased delay of the signals and increased complexity of the chip. Meanwhile, since the signal must be blocked in the actual signal processing to reduce the delay of the single module processing and the storage pressure, this may cause a large influence on the FFE filtering performance due to a truncation effect caused by the data discontinuity when the FFE filtering processes the single block signal. The method typically employed is to buffer the data down for overlap addition to reduce the loss of performance, but this causes further delays in the signal. In addition, since the number of taps is positively correlated with the channel performance, as the baud rate increases, the intersymbol interference increases, the number of taps required for FFE increases, the complexity and power consumption of FFE increases, and the number of taps for FFE is generally limited as the data added in overlapping also increases.

For the problem of FFE complexity of the current high baud rate and large attenuation channel, the main solution in the industry is to reduce or limit the number of taps of the FFE, and add other equalizers, for example, utilize the later stage DFE to share part of equalizing pressure, but when the number of taps of the DFE is greater than 1, the timing pressure of the feedback loop is too large to be unfavorable for high-speed implementation, so that the DFE cannot select too high number of taps, so that the compensating effect of the DFE is limited, and the performance of the whole system is limited.

Therefore, how to reduce the high complexity and the large delay of the transmission signal of the feed-forward equalizer of the high baud rate and large attenuation channel is a technical problem that needs to be solved in the field.

Disclosure of Invention

In order to alleviate or partially alleviate the above technical problem, the solution of the present invention is as follows:

An information receiving method applied to an ADC-based SerDes system, the method comprising the steps of: step S1: converting an analog signal received by a receiver into a digital signal; step S2: performing discrete Fourier transform on the digital signal so as to transform a time domain signal into a frequency domain signal, and then performing frequency domain filtering; step S3: performing inverse discrete Fourier transform on the signals after the frequency domain filtering; step S4: and carrying out feedback equalization and decision processing on the signal after the inverse discrete Fourier transform.

Further, the converted digital signal is blocked before the discrete fourier transform is performed in step S2.

Further, in the step S2, frequency domain filtering is performed based on the following formula:

，

E(k)=D(k)-Y(k)，

，

Wherein X (k), Y (k), W (k), E (k) and D (k) are discrete fourier transform values of X (N), Y (N), W (N), E (N) and D (N), respectively, X (N) represents N time domain signals input by the current time frequency domain filtering module, Y (N) represents N time domain signals output by the current time table frequency domain filtering module, E (N) represents N error signals at the current time, D (N) represents N ideal values of the current time signal, W (N) represents a coefficient value at the current time, W (n+1) represents a coefficient value at the next time, and u represents a step size of FFE convergence.

Further, in the step S2, the bandwidth of the digital signal after the discrete fourier transform is less than or equal toAnd the center frequency satisfies the following relationship:

，

Wherein m=0, 1,2, …, (M-1), M is the number of points after discrete fourier transform, For sampling frequency,/>Is the center frequency.

An ADC-based SerDes system comprising a transmitter and a receiver, an output of the transmitter being communicated to the receiver via a link; the receiver includes:

An analog-to-digital converter for converting the analog signal received by the receiver into a digital signal;

The input end of the blocking module is coupled with the output end of the analog-to-digital converter, and the digital signal after conversion is blocked;

the input end of the discrete Fourier transform module is coupled with the output end of the blocking module, and the signals after blocking are subjected to discrete Fourier transform;

The input end of the frequency domain filtering module is coupled with the output end of the Fourier transform module so as to carry out frequency domain filtering;

The input end of the inverse discrete Fourier transform module is coupled with the output end of the frequency domain filtering module, and the signal after frequency domain filtering is subjected to inverse discrete Fourier transform;

And the input end of the feedback decision equalization module is coupled with the output end of the inverse discrete Fourier transform module so as to perform feedback equalization and decision processing.

Further, the discrete fourier transform module transforms the segmented signal from the time domain to the frequency domain, and the inverse discrete fourier transform module transforms the frequency domain filtered signal from the frequency domain back to the time domain.

Further, the SerDes system further comprises a frequency domain filtering updating module, wherein the frequency domain filtering updating module is used for updating frequency domain coefficients or/and frequency domain errors of the frequency domain filtering module.

Further, the discrete fourier transform module performs the following transforms:

，

Where N is the current time, X (N) is N time domain signals input by frequency domain filtering at the current time, X (k) is a discrete fourier transform value of X (N), k is the frequency of the frequency domain, exp is an exponential function, and N is a positive integer.

Further, the frequency domain filtering module performs frequency domain filtering based on the following formula:

，

E(k)=D(k)-Y(k)，

，

Wherein X (k), Y (k), W (k), E (k) and D (k) are discrete fourier transform values of X (N), Y (N), W (N), E (N) and D (N), respectively, X (N) represents N time domain signals input by the current time frequency domain filtering module, Y (N) represents N time domain signals output by the current time table frequency domain filtering module, E (N) represents N error signals at the current time, D (N) represents N ideal values of the current time signal, W (N) represents a coefficient value at the current time, W (n+1) represents a coefficient value at the next time, and u represents a step size of FFE convergence.

Further, the SerDes system also includes a clock data recovery circuit having an input coupled to the output of the analog-to-digital converter, the clock data recovery circuit feeding back a recovered clock signal and a recovered data signal to the analog-to-digital converter. Preferably, the clock data recovery circuit is implemented based on a Mueller-Mueller phase detector (Mueller-Muller phase detector, MMPD).

Further, the analog-to-digital converter converts an analog signal received by the receiver into a digital signal based on the clock signal and the data signal recovered by the clock data recovery circuit.

Further, the transmitter comprises a data generator, a mapper, a transmitter feed-forward equalizer and a digital-to-analog converter which are coupled in sequence;

The digital signal generated by the data generator is mapped by the mapper and filtered by the transmitter forward feedback equalizer and then is sent to the digital-to-analog converter for digital-to-analog conversion, and the output of the digital-to-analog converter is transmitted to the receiver through the link.

Further, the frequency domain filtering module of the receiver and the transmitter feed-forward equalizer are jointly designed, so that the frequency spectrums of the frequency domain filtering module of the receiver and the frequency spectrums of the analog signals received by the transmitter coincide.

Further, the bandwidth of the digital signal after discrete Fourier transform is less than or equal toAnd the center frequency satisfies the following relationship:

，

Wherein m=0, 1,2, …, (M-1), M is the number of points after discrete fourier transform, For sampling frequency,/>Is the center frequency.

The technical scheme of the invention has one or more of the following beneficial technical effects:

(1) In the receiver, the discrete Fourier transform (Discrete Fourier Transform, DFT) is utilized to transform signals from a time domain to a frequency domain, the convolution of the time domain is transformed into the multiplication of the frequency domain, and the frequency domain is equalized, so that the computational complexity is reduced;

(2) According to the invention, by increasing the tap number of the FFE in the receiver, no extra complexity is added for frequency domain multiplication, so that the FFE in the receiver can be increased as much as possible to obtain better performance, and the problem of FFE complexity in the receiver of the current high-baud rate large-attenuation channel is solved;

(3) The receiver replaces convolution of a plurality of modules (such as a forward feedback equalizer and a floating tap forward equalizer in the receiver in the prior art) in time domain equalization by multiplication of frequency domain filtering, so that one module is saved, and the complexity is further reduced;

(4) The frequency domain filtering modules of the transmitter and the receiver are designed in a combined mode, and after proper DFT points are selected, frequency bands of spectrum leakage are avoided, filtering effect is improved, overlapping adding modules in front of FFEs can be removed, and delay of signals is reduced.

Furthermore, other advantageous effects that the present invention has will be mentioned in the specific embodiments.

Drawings

FIG. 1 is a typical ADC-based SerDes system;

FIG. 2 is a schematic diagram of a SerDes system based on a frequency domain equalizer according to a preferred embodiment of the present invention;

FIG. 3 is a flow chart of an FFE implementation in the frequency domain in accordance with a preferred embodiment of the present invention;

Fig. 4 is a flowchart of an information receiving method according to the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Numerous specific details are set forth in the following description in order to provide a better understanding of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, methods, means, components, and circuits that are well known to those skilled in the art have not been described in detail in order to not obscure the present invention.

An equalizer for inserting into the baseband or intermediate frequency part of the SerDes system to reduce inter-symbol interference, corresponding to a compensating filter. Further, the filter with compensation function is a finite length unit impulse response filter, also called a non-recursive filter, which is the most basic component in the field of high-speed data transmission, and the unit sampling response is finite length, so that the filter can guarantee any amplitude-frequency characteristic and has strict linear phase-frequency characteristic.

Fig. 2 is a schematic diagram of a SerDes system including a transmitter and a receiver based on a frequency domain equalizer according to a preferred embodiment of the present invention.

The transmitter includes a data generator, a mapper, a transmitter forward feedback equalizer (TRANSCEIVER FEED Forward Equalizer, TX FFE), a digital-to-analog converter (Digital to Analog Converter, DAC) coupled in sequence. The digital signal generated by the data generator is mapped by the mapper and filtered by the transmitter forward feedback equalizer and then sent to the DAC for conversion, and the output of the DAC is transmitted to the receiver through the link.

The receiver comprises an ADC, a discrete Fourier transform module, a frequency domain filtering module, an inverse discrete Fourier transform and a feedback decision equalization module which are sequentially coupled on a main data path. Wherein the ADC converts the analog signal received by the receiver into a digital signal.

The input of the blocking module is coupled with the output of the ADC, and the digital signal after ADC conversion is blocked.

The discrete Fourier transform module performs DFT processing on the segmented signals to transform the segmented signals from the time domain to the frequency domain.

An input of the frequency domain filtering module is coupled to an output of the fourier transform module for frequency domain filtering.

An inverse discrete fourier transform (INVERSE DISCRETE Fourier Transform, IDFT) module converts the frequency domain filtered signal back to the time domain.

And the feedback decision equalization module performs DFE and decision processing on the IDFT signals.

Further, the receiver also comprises an updating module for updating coefficients or/and errors of the frequency domain filtering module.

Optionally, the receiver further includes a CDR circuit, an input terminal of the CDR circuit is coupled to an output terminal of the ADC, the CDR circuit feeds back the recovered clock signal and the recovered data signal to the ADC, and the ADC converts an analog signal received by the receiver into a digital signal based on the recovered clock signal and the recovered data signal of the CDR circuit, so as to reduce an error rate and improve system accuracy.

Optionally, the present invention completes the function of the Floating Tap FFE simultaneously in the frequency domain multiplication of FFE in the receiver, and omits a module (Floating Tap FFE), thereby further reducing complexity.

Compared with the prior art, the invention converts the convolution when FFE and flowing Tap FFE in the receiver carry out time domain filtering into multiplication when frequency domain filtering, and the time domain operation of convolving the weight coefficient and the input signal is equivalent to the frequency domain operation of multiplying the weight coefficient and the input signal, thereby greatly reducing the computational complexity under the condition of not reducing the performance.

Meanwhile, the number of taps cannot be seen in the frequency domain, and for frequency domain multiplication, the number of taps of the FFE and the flowing Tap FFE in the receiver is increased without increasing extra complexity.

The invention applies discrete Fourier transform in the receiver, realizes FFE in the frequency domain, transforms the signal equalized by FFE and flowing Tap FFE of the receiver in the prior art from the time domain to the frequency domain, and equalizes in the frequency domain.

Specifically, the time domain expression of FFE in a receiver is as follows:

；

；

。

Wherein x (N) represents N time domain signals input by FFE at the current moment, N is a positive integer, and the time domain resolution is determined; y (N) represents N time domain signals output by the FFE of the current time table, e (N) represents N error signals of the current time, d (N) represents N ideal values of the signal of the current time, w (N) represents a coefficient value of the current time, w (n+1) represents a coefficient value of the next time, and u represents a step size of FFE convergence, and is generally a fixed value.

Fig. 3 is a flow chart of the FFE implementation in the frequency domain according to a preferred embodiment of the present invention. The expression for realizing FFE equalization in the frequency domain is as follows:

；

E(k) = D(k)-Y(k)；

。

Wherein X (k), Y (k), W (k), E (k) and D (k) are discrete Fourier transform values of X (n), Y (n), W (n), E (n) and D (n), respectively, wherein the meaning of X (n), Y (n), W (n), E (n) and D (n) is consistent with the meaning of FFE equalization in the time domain, Is the conjugate of X (k).

Taking x (n) as an example, the formula of the DFT transformation is:

。

Wherein N represents the current time, x (N) represents N time domain signals input by FFE in the receiver at the current time, N is a positive integer, and the time domain resolution is determined; k is the frequency of the frequency domain and exp is an exponential function.

Let the center frequency of the time domain signal generated by the data generator in the transmitter beSampling rate is/>In the receiver, the receiver receives the input signal, after being segmented, and then the input signal is transformed into the frequency domain by the discrete Fourier transform module and is filtered by the frequency domain filtering module, at this time, a rectangular window is added to the time domain signal, which may cause frequency spectrum leakage and affect the accuracy of subsequent calculation.

The discrete fourier transform module in the receiver is equivalent to a set of narrow band filters, each filter having a center frequency ofWith a bandwidth of/>. Each filter is shaped as a sinc function, also known as a sinc function. When the center frequency and bandwidth of the received signal are not matched with those of the frequency domain filtering module, a large spectrum leakage is formed. In the invention, the bandwidth of the digital signal after discrete Fourier transform is less than or equal to/>And the center frequency satisfies the following relationship:

，

Wherein m=0, 1,2, …, (M-1), M is the number of points after discrete fourier transform, For sampling frequency,/>Is the center frequency. Therefore, the frequency domain filter module can be matched with the frequency spectrum of the time domain signal generated by the data generator in the transmitter, and the problem of frequency spectrum leakage is solved.

The invention filters in the frequency domain, but can avoid the cut-off effect of the time domain signal, but needs to prevent the blocked signal from forming larger frequency spectrum leakage after DFT, thus reducing the filtering effect, under the condition that the blocking length is usually fixed, optionally, the transmitter and the frequency domain filtering module of the receiver of the invention are combined to design, and proper DFT point number and transmitter coefficient are selected, so that the frequency band of frequency spectrum leakage can be avoided, and overlapping adding modules in the receiver can be removed, and the delay of the signal is reduced.

Fig. 4 is a flowchart of an information receiving method according to the present invention. The invention also discloses an information receiving method which is applied to the SerDes system based on the ADC, and the method comprises the following steps:

step S1: converting an analog signal received by a receiver into a digital signal;

step S2: performing discrete Fourier transform on the digital signal so as to transform a time domain signal into a frequency domain signal, and performing frequency domain filtering by a frequency domain filtering module;

step S3: performing inverse discrete Fourier transform on the signals after the frequency domain filtering;

step S4: and carrying out feedback equalization and decision processing on the signal after the inverse discrete Fourier transform.

Further, the converted digital signal is blocked before the discrete fourier transform is performed in step S2.

Further, the frequency domain filtering updating module is used for updating the frequency domain coefficients or/and the frequency domain errors of the frequency domain filtering module.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. An information receiving method applied to an ADC-based SerDes system, the method comprising the steps of:

step S1: converting an analog signal received by a receiver into a digital signal;

Step S2: performing discrete Fourier transform on the digital signal so as to transform a time domain signal into a frequency domain signal, and then performing frequency domain filtering;

step S3: performing inverse discrete Fourier transform on the signals after the frequency domain filtering;

step S4: and carrying out feedback equalization and decision processing on the signal after the inverse discrete Fourier transform.

2. The information receiving method according to claim 1, characterized in that:

The converted digital signal is blocked before the discrete fourier transform is performed in step S2.

3. The information receiving method according to claim 1 or 2, characterized in that:

In the step S2, frequency domain filtering is performed based on the following formula:

；

E(k)=D(k)-Y(k)；

；

Wherein X (k), Y (k), W (k), E (k) and D (k) are discrete fourier transform values of X (N), Y (N), W (N), E (N) and D (N), respectively, X (N) represents N time domain signals input by the current time frequency domain filtering module, Y (N) represents N time domain signals output by the current time table frequency domain filtering module, E (N) represents N error signals at the current time, D (N) represents N ideal values of the current time signal, W (N) represents a coefficient value at the current time, W (n+1) represents a coefficient value at the next time, and u represents a step size of FFE convergence.

4. The information receiving method according to claim 3, wherein:

In the step S2, the bandwidth of the digital signal after discrete fourier transform is less than or equal to And the center frequency satisfies the following relationship:

；

Wherein m=0, 1,2, …, (M-1), M is the number of points after discrete fourier transform, For sampling frequency,/>Is the center frequency.

5. An ADC-based SerDes system, comprising:

the SerDes system comprises a transmitter and a receiver, wherein the output of the transmitter is transmitted to the receiver through a link;

The receiver includes:

An analog-to-digital converter for converting the analog signal received by the receiver into a digital signal;

The input end of the blocking module is coupled with the output end of the analog-to-digital converter, and the digital signal after conversion is blocked;

the input end of the discrete Fourier transform module is coupled with the output end of the blocking module, and the signals after blocking are subjected to discrete Fourier transform;

The input end of the frequency domain filtering module is coupled with the output end of the Fourier transform module so as to carry out frequency domain filtering;

The input end of the inverse discrete Fourier transform module is coupled with the output end of the frequency domain filtering module, and the signal after frequency domain filtering is subjected to inverse discrete Fourier transform;

And the input end of the feedback decision equalization module is coupled with the output end of the inverse discrete Fourier transform module so as to perform feedback equalization and decision processing.

6. The ADC-based SerDes system according to claim 5, wherein:

the discrete Fourier transform module transforms the blocked signal from the time domain to the frequency domain, and the inverse discrete Fourier transform module transforms the frequency domain filtered signal from the frequency domain back to the time domain.

7. The ADC-based SerDes system of claim 6, wherein:

The SerDes system further comprises a frequency domain filtering updating module, wherein the frequency domain filtering updating module is used for updating frequency domain coefficients or/and frequency domain errors of the frequency domain filtering module.

8. The ADC-based SerDes system according to any one of claims 5 to 7, wherein:

The SerDes system also includes a clock data recovery circuit having an input coupled to the output of the analog-to-digital converter, the clock data recovery circuit feeding back a recovered clock signal and a recovered data signal to the analog-to-digital converter.

9. The ADC-based SerDes system of claim 8, wherein:

The analog-to-digital converter converts an analog signal received by the receiver into a digital signal based on the clock signal and the data signal recovered by the clock data recovery circuit.

10. The ADC-based SerDes system of claim 9, wherein:

The transmitter comprises a data generator, a mapper, a transmitter forward feedback equalizer and a digital-to-analog converter which are coupled in sequence;

The digital signal generated by the data generator is mapped by the mapper and filtered by the transmitter forward feedback equalizer and then is sent to the digital-to-analog converter for digital-to-analog conversion, and the output of the digital-to-analog converter is transmitted to the receiver through the link.