CN118099927A - Diamond chip and preparation method thereof - Google Patents
Diamond chip and preparation method thereof Download PDFInfo
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- CN118099927A CN118099927A CN202410462122.6A CN202410462122A CN118099927A CN 118099927 A CN118099927 A CN 118099927A CN 202410462122 A CN202410462122 A CN 202410462122A CN 118099927 A CN118099927 A CN 118099927A
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- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 136
- 239000010432 diamond Substances 0.000 title claims abstract description 136
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 238000003466 welding Methods 0.000 claims abstract description 149
- 229910052751 metal Inorganic materials 0.000 claims abstract description 109
- 239000002184 metal Substances 0.000 claims abstract description 109
- 230000005496 eutectics Effects 0.000 claims abstract description 100
- 238000001465 metallisation Methods 0.000 claims abstract description 54
- 238000001816 cooling Methods 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 11
- 229910000679 solder Inorganic materials 0.000 claims description 102
- 230000017525 heat dissipation Effects 0.000 claims description 90
- 230000004888 barrier function Effects 0.000 claims description 84
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 74
- 230000003647 oxidation Effects 0.000 claims description 47
- 238000007254 oxidation reaction Methods 0.000 claims description 47
- 239000010931 gold Substances 0.000 claims description 45
- 239000000758 substrate Substances 0.000 claims description 35
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 32
- 229910052738 indium Inorganic materials 0.000 claims description 30
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 30
- 229910052737 gold Inorganic materials 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 26
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 17
- 229910045601 alloy Inorganic materials 0.000 claims description 12
- 239000000956 alloy Substances 0.000 claims description 12
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 10
- 229910052697 platinum Inorganic materials 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000003475 lamination Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 4
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- 239000010949 copper Substances 0.000 description 13
- 230000006872 improvement Effects 0.000 description 10
- 230000035882 stress Effects 0.000 description 10
- 238000005476 soldering Methods 0.000 description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention belongs to the technical field of semiconductors, and provides a diamond chip and a preparation method thereof. Through diamond selection, surface treatment and surface cleaning inspection, the diamond is placed into sputtering equipment to be plated with a metal layer, and then the metallized diamond is placed on eutectic welding equipment to realize welding, and cooling is carried out after welding. The high thermal conductivity of diamond is utilized in the product, so that the performance of the chip is better exerted, and the service life of the chip is prolonged; in addition, by further adjusting the welding process, optimizing the welding flux, changing the structure of the metallization layer and adjusting the welding flux, the stress between the diamond and the chip is released to a certain extent, chip cracking is avoided, the welding time is shortened, the chip cracking problem during welding is solved, and the chip product with qualified quality and good performance is obtained.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a diamond chip and a preparation method thereof.
Background
In chip products, taking gallium arsenide (GaAs) chips as an example, gaAs is a very important III-V group direct band gap compound semiconductor material, has higher electron mobility and excellent photoelectric performance, is widely applied to high-power semiconductor laser devices, and is applied to the fields of production and processing, laser communication, medical cosmetology, automatic control, military weapons and the like. However, with the increase in the demand for semiconductor laser performance, a new demand is also being put on the improvement in the overall performance of GaAs-based semiconductor lasers.
The electrical conversion efficiency of the common device is about 40% -50%, and if the heat dissipation effect is poor, the performance of the device is affected, and even the chip is damaged. The existing semiconductor laser chips (such as silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC) or indium phosphide (InP) chips) have limited heat dissipation performance due to direct welding of copper substrates; the heat dissipation performance of the diamond is outstanding, but the thermal expansion coefficient of the diamond is different from that of the chip, so that the chip is cracked due to stress when the diamond is welded with the chip. Therefore, there is a need for a solution to the problem of chip cracking caused by the difference in thermal expansion coefficients in the diamond bonded chip solution, so as to obtain a diamond chip product with outstanding properties such as heat dissipation.
Disclosure of Invention
The invention provides a diamond chip and a preparation method thereof, which have better heat dissipation effect and ensure that the chip is not broken.
The invention is realized in the following way:
In a first aspect, the invention provides a diamond chip, which comprises a heat dissipation substrate, a first eutectic welding layer, a diamond heat dissipation layer, a second eutectic welding layer and a chip which are arranged in a stacked manner, wherein a first metallization layer is arranged between the first eutectic welding layer and the diamond heat dissipation layer, and a second metallization layer is arranged between the diamond heat dissipation layer and the second eutectic welding layer.
As a further improvement, the first metallization layer includes a first barrier layer and a first metal bonding layer laminated on the first eutectic solder layer;
and/or the second metallization layer comprises a second metal bonding layer and a second barrier layer which are laminated and arranged on the diamond heat dissipation layer.
As a further improvement, the first eutectic solder layer comprises a gold layer and at least one first gold-tin solder layer which are laminated along a set direction, and the first gold-tin solder layer comprises a tin layer and a gold layer which are laminated along the set direction; the set direction is the direction in which the heat dissipation substrate points to the chip;
And/or the second eutectic welding layer comprises at least one layer of second gold-tin welding layer and gold layers which are arranged on all the second gold-tin welding layers in a lamination mode along the set direction, and the second gold-tin welding layer comprises gold layers and tin layers which are arranged in a lamination mode along the set direction.
As a further improvement, the first metallization layer further comprises a first metal oxidation resistant layer disposed between the first barrier layer and the first eutectic solder layer;
and/or, the second metallization layer further comprises a second metal oxidation resistant layer, and the second metal oxidation resistant layer is arranged between the second barrier layer and the second eutectic welding layer.
As a further improvement, the first eutectic solder layer comprises at least one first gold-tin solder layer, and the first gold-tin solder layer comprises a gold layer and a tin layer which are stacked along a set direction; or the first gold-tin welding layer is a gold-tin alloy layer; the set direction is the direction in which the heat dissipation substrate points to the chip;
And/or the second eutectic welding layer comprises at least one layer of second gold-tin welding layer, and the second gold-tin welding layer comprises a tin layer and a gold layer which are stacked along the set direction; or the second gold-tin welding layer is a gold-tin alloy layer.
As a further refinement, the material of the first barrier layer comprises at least one of Pt, ni, cr, W or an alloy thereof; or a first middle buffer layer is arranged between the first barrier layer and the first metal bonding layer, and the first middle buffer layer is a Cu layer or an Ag layer; the thickness of the first intermediate buffer layer is 8-12 times that of the first barrier layer;
And/or the material of the second barrier layer comprises at least one of Pt, ni, cr, W or an alloy thereof; or a second intermediate buffer layer is arranged between the second barrier layer and the second metal bonding layer, and the second intermediate buffer layer is a Cu layer or an Ag layer; the thickness of the second intermediate buffer layer is 8-12 times that of the second barrier layer;
And/or the first metal oxidation resistance layer is an Au layer, and the thickness of the first metal oxidation resistance layer is 50-70000 nm; the first metal bonding layer is a Ti layer, and the thickness of the first metal bonding layer is 50-1000 nm; the thickness of the first barrier layer is 50-1000 nm;
And/or the second metal oxidation resistance layer is an Au layer, and the thickness of the second metal oxidation resistance layer is 50-70000 nm; the second metal bonding layer is a Ti layer, and the thickness of the second metal bonding layer is 50-1000 nm; the thickness of the second barrier layer is 50-1000 nm;
and/or the thickness of the first eutectic welding layer is 8-12 mu m;
And/or the thickness of the second eutectic welding layer is 8-12 mu m.
As a further improvement, the thickness of the first barrier layer is 200-1000 nm; and/or the ratio of the thicknesses of the first metal bonding layer, the first barrier layer and the first metal oxidation resistance layer is 1:1-2:3-6;
And/or the thickness of the second barrier layer is 200-1000 nm; and/or the thickness ratio of the second metal bonding layer, the second barrier layer and the second metal oxidation resistance layer is 1:1-2:3-6.
As a further improvement, the first eutectic solder layer comprises at least one first indium layer; or the first eutectic welding layer comprises at least one first welding material layer, the first welding material layer comprises a first indium layer and the first gold-tin welding layer which are laminated along a set direction, or the first eutectic welding layer comprises a first indium layer and at least one first gold-tin welding layer which are laminated along the set direction; the set direction is the direction in which the heat dissipation substrate points to the chip;
And/or, the second eutectic solder layer comprises at least one second indium layer; or the second eutectic welding layer comprises at least one second welding material layer, the second welding material layer comprises a second gold-tin welding layer and a second indium layer arranged on the second gold-tin welding layer along the set direction, or the second eutectic welding layer comprises at least one second gold-tin welding layer and a second indium layer arranged on all the second gold-tin welding layers in a lamination mode along the set direction;
and/or the thickness of the first indium layer is 0.5-10 mu m;
and/or the thickness of the second indium layer is 0.5-10 mu m.
As a further improvement, the thermal conductivity of the diamond heat sink layer is greater than 1800W/(m×k).
In a second aspect, the present invention provides a method for manufacturing a diamond chip, comprising the steps of:
Providing a diamond heat dissipation layer;
plating a first metallization layer on the lower surface of the diamond heat dissipation layer, and plating a second metallization layer on the upper surface of the diamond heat dissipation layer;
welding the first metallization layer and the heat dissipation substrate by adopting a first eutectic welding layer, and welding the second metallization layer and the chip by adopting a second eutectic welding layer to obtain a chip structure;
and cooling the chip structure to obtain the diamond chip.
As a further improvement, the cooling treatment time is 5-300 s, and the cooling rate corresponding to the cooling treatment is 20-25 ℃/s.
The beneficial effects of the invention are as follows: the diamond chip provided by the invention comprises a heat dissipation substrate, a first eutectic welding layer, a first metallization layer, a diamond heat dissipation layer, a second metallization layer, a second eutectic welding layer and a chip which are arranged in a stacked manner, namely, the first eutectic welding layer and the first metallization layer are arranged between the heat dissipation substrate and the diamond heat dissipation layer, and the second metallization layer and the second eutectic welding layer are arranged between the chip and the diamond heat dissipation layer; because the laminated first eutectic welding layer and the first metallization layer are arranged between the heat radiating substrate and the diamond heat radiating layer, the chip fragmentation problem caused by the difference between the thermal expansion coefficient of diamond and the thermal expansion coefficient of the chip during welding can be solved, and the chip product with qualified quality and good performance can be obtained.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an embodiment of a diamond chip according to the present invention;
FIG. 2 is a schematic view of another embodiment of a diamond chip according to the present invention;
FIG. 3 is a schematic view of another embodiment of a diamond chip according to the present invention;
FIG. 4 is a schematic view of another embodiment of a diamond chip according to the present invention;
FIG. 5 is a schematic view of another embodiment of a diamond chip according to the present invention;
FIG. 6 is a schematic view of another embodiment of a diamond chip according to the present invention;
FIG. 7 is a schematic view of another embodiment of a diamond chip according to the present invention;
FIG. 8 is a schematic view of another embodiment of a diamond chip according to the present invention;
FIG. 9 is a schematic flow chart of an embodiment of a method for fabricating a diamond chip according to the present invention;
FIG. 10 is a graph of current versus output power for example 1 and comparative example 1 provided by the present invention;
fig. 11 is a graph for testing the electro-optic conversion efficiency of example 1 and comparative example 1 provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a diamond chip provided by the present invention, the diamond chip includes a heat dissipation substrate 1, a first eutectic solder layer 2, a diamond heat dissipation layer 3, a second eutectic solder layer 4, and a chip 5 stacked together, a first metallization layer 6 is disposed between the first eutectic solder layer 2 and the diamond heat dissipation layer 3, and a second metallization layer 7 is disposed between the diamond heat dissipation layer 3 and the second eutectic solder layer 4.
The heat dissipation substrate 1 is a copper substrate or an aluminum alloy substrate, and may be made of different materials according to the requirements of different products. The chip 5 and the heat dissipating substrate 1 are both subjected to a metal treatment before processing.
The chip 5 is a semiconductor material chip such as a chip of silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or indium phosphide (InP).
In some embodiments, the thickness of the diamond heat dissipation layer 3 is 50 μm to 1mm, and the surface of the diamond heat dissipation layer 3 is defect-free, so that the bonding force is ensured, and the welding void rate is reduced.
In this scheme, the thermal conductivity of diamond heat dissipation layer 3 is greater than 1800W/(m K), through with diamond heat dissipation layer 3 welding to chip 5 on can improve the thermal conductivity, promote the radiating effect of chip 5, prevent chip 5 overheated, can better exert the performance of chip 5 and increase the life-span of chip 5 simultaneously.
Further, the double-sided roughness of the diamond heat dissipation layer 3 is smaller than 1nm, the flatness is smaller than 1/4λ, λ represents wavelength, namely, a white light interferometer is adopted, 632.8nm wavelength is used for measuring surface flatness, the number of interference fringes is observed, and 1/4λ refers to 1/4 of the number of interference fringes; by the arrangement, the contact area is increased, and the binding force of the coating is ensured.
In some embodiments, as shown in fig. 2, the first metallization layer 6 includes a first barrier layer 62 and a first metal bonding layer 61 that are stacked on the first eutectic solder layer 2; the second metallization layer 7 includes a second metal bonding layer 71 and a second barrier layer 72 stacked on the diamond heat sink layer 3.
In another embodiment, as shown in fig. 3, the first metallization layer 6 includes a first metal oxidation-resistant layer 63, a first barrier layer 62, and a first metal bonding layer 61 that are stacked on the heat-dissipating substrate 1. Or as shown in fig. 3, the second metallization layer 7 includes a second metal bonding layer 71, a second barrier layer 72, and a second metal oxidation resistant layer 73 stacked on the diamond heat sink layer 3. Or as shown in fig. 3, the first metallization layer 6 includes a first metal bonding layer 61, a first barrier layer 62, and a first metal oxidation resistant layer 63 laminated on the diamond heat sink layer 3.
In an embodiment, the material of the first barrier layer 62 includes at least one of Pt, ni, cr, W or an alloy thereof; and/or the material of the second barrier layer 72 comprises at least one of Pt, ni, cr, W or an alloy thereof.
In another embodiment, referring to fig. 1 and fig. 4 in combination, a first intermediate buffer layer 81 is further disposed between the first barrier layer 62 and the first metal bonding layer 61, the first intermediate buffer layer 81 is a Cu layer or an Ag layer, and the thickness of the first intermediate buffer layer 81 is 8-12 times that of the first barrier layer 62; and/or, a second intermediate buffer layer 82 is further arranged between the second barrier layer 72 and the second metal bonding layer 71, and the second intermediate buffer layer 82 is a Cu layer or an Ag layer; the thickness of the second intermediate buffer layer 82 is 8 to 12 times the thickness of the second barrier layer 72.
By providing the intermediate buffer layer (including the first intermediate buffer layer 81 and the second intermediate buffer layer 82) and the barrier layer (including the first barrier layer 62 and the second barrier layer 72) with the thicknesses as described above, that is, the thicknesses of the Cu layer/Ag layer are 8 to 12 times the thicknesses of the barrier layer formed by at least one of Pt, ni, cr, W or an alloy thereof, a superior thermal expansion coefficient can be achieved, a better stress release effect can be obtained in welding cooling and use, not only the release of stress is facilitated, but also an anti-seepage effect can be played to the weld.
In yet another embodiment, the first metal bonding layer 61 is a Ti layer, and the thickness of the first barrier layer 62 is 50-1000 nm; and/or the second metal bonding layer 71 is a Ti layer, and the thickness of the second barrier layer 72 is 50-1000 nm.
Further, the blocking effect is poor due to the fact that the thickness of the blocking layer is too thin, the blocking effect of blocking the lower movement of the upper metal is not achieved due to the fact that the strength is insufficient during welding, and therefore the thickness of the blocking layer is set to be larger than 200nm; and if the thickness of the barrier layer is too thick, heat dissipation is affected, so that the thickness of the barrier layer is set to be 200-1000 nm.
The metal bonding layer (comprising the first metal bonding layer 61 and the second metal bonding layer 71) ensures the bonding force between the metal and the diamond heat dissipation layer 3, and the bonding force is strong because Ti and the diamond heat dissipation layer 3 form TiC covalent compounds.
Further, if the thickness of the metal bonding layer is too thin, the bonding force with the upper layer is insufficient; if the thickness of the metal bonding layer is too thick, the thermal resistance is increased, and the thickness of the metal bonding layer is set to 50 to 1000nm, i.e., the thickness of the first metal bonding layer 61 is 50 to 1000nm, and the thickness of the second metal bonding layer 71 is 50 to 1000nm.
The material of the metal oxidation resistant layer (comprising the first metal oxidation resistant layer 63 and the second metal oxidation resistant layer 73) adopts Au, namely the metal oxidation resistant layer is an Au layer, and the solderability is strong, and the antioxidation effect is achieved. In addition, the thickness of the metal oxidation resistant layer is too thin to cause insufficient soldering strength, i.e., too thick of the Au layer causes large thermal resistance, so the thickness of the Au layer is set to 50 to 70000 nm, i.e., the thicknesses of the first metal oxidation resistant layer 63 and the second metal oxidation resistant layer 73 are set to 50 to 70000 nm.
In some embodiments, the thickness of the first barrier layer 62 is 200-1000 nm; and/or the ratio of the thicknesses of the first metal bonding layer 61, the first barrier layer 62 and the first metal oxidation resistant layer 63 is 1:1-2:3-6;
in some embodiments, the thickness of the second barrier layer 72 is 200-1000 nm; and/or the thickness ratio of the second metal bonding layer 71, the second barrier layer 72 and the second metal oxidation resistant layer 73 is 1:1-2:3-6.
In some embodiments, the thickness of the first eutectic solder layer 2 is 8-12 μm.
In an embodiment, referring to fig. 1 and fig. 5 in combination, the first eutectic solder layer 2 includes at least one first indium layer 22, the first indium layer 22 is disposed between the heat dissipation substrate 1 and the first metal anti-oxidation layer 63, and the thickness of the first indium layer 22 is 0.5-10 μm.
In another embodiment, as shown in fig. 6, the first eutectic solder layer 2 includes a gold layer 23 and at least one first gold-tin solder layer 21 stacked along a set direction, and the first gold-tin solder layer 21 includes a tin layer 212 and a gold layer 211 stacked along the set direction; the set direction is the direction in which the heat dissipation substrate 1 points to the chip 5. For example, the first eutectic solder layer 2 includes 1 gold layer 23 and 2 first gold-tin solder layers 21 stacked, i.e., the first eutectic solder layer 2 includes gold layer 23, tin layer 212, gold layer 211 stacked, and is referred to as a "gold-tin-gold" solder layer.
In yet another embodiment, as shown in fig. 7, the first eutectic solder layer 2 includes at least one first au-sn solder layer 21, and the first au-sn solder layer 21 includes an au layer 211 and a sn layer 212 stacked along a set direction; or the first gold-tin welding layer 21 is a gold-tin alloy layer; the first metallization layer 6 thereof is provided with a first metal bonding layer 61, a first metal barrier layer 62 and a first metal oxidation resistant layer 63. The set direction is the direction in which the heat dissipation substrate 1 points to the chip 5.
In some embodiments, the thickness of the second eutectic solder layer 4 is 8-12 μm.
In an embodiment, referring to fig. 1 and fig. 5 in combination, the second eutectic solder layer 2 includes at least one second indium layer 42, the second indium layer 42 is disposed between the chip 5 and the second metal oxidation resistant layer 73, and the thickness of the second indium layer 42 is 0.5-10 μm.
In another embodiment, as shown in fig. 6, the second eutectic solder layer 4 includes at least one second gold-tin solder layer 41 and gold layers 43 stacked on all the second gold-tin solder layers 41 along a set direction, and the second gold-tin solder layer 41 includes a gold layer 411 and a tin layer 412 stacked along the set direction.
In yet another embodiment, as shown in fig. 7, the second eutectic solder layer 4 includes at least one layer of a second gold-tin solder layer 41, and the second gold-tin solder layer 41 includes a tin layer 412 and a gold layer 411 stacked along a set direction; or the second gold-tin solder layer 41 is a gold-tin alloy layer; the second metallization layer 7 thereof is provided with a second metal bonding layer 71, a second barrier layer 72 and a second metal oxidation resistant layer 73.
Further, the gold content in the gold-tin solder layer (including the first gold-tin solder layer 21 and the second gold-tin solder layer 41) is 73-75%.
The bonding surface of the chip 5, the heat dissipation substrate 1 and the diamond heat dissipation layer 3 is provided with a metallized gold layer, if a gold-tin alloy layer is used as the eutectic solder layer, during welding, gold atoms at the bottom of the chip 5 and gold atoms of the metallized layer on the diamond heat dissipation layer 3 migrate to the eutectic solder layer, so that the proportion of gold content in the eutectic solder layer is increased, the melting point is increased, and a gold-tin alloy with a new proportion is formed. At the same time, tin can also alloy with the barrier layer (e.g., pt), which is required to ensure that the barrier layer cannot be too thin, otherwise, pt and tin react completely, and gold is still penetrating down, affecting the soldering effect.
The eutectic welding layer is generally made of welding materials with the characteristics of high heat conductivity, high welding strength, good ductility, stable chemical property and the like. Specifically, the eutectic solder layer selects a hard solder (such as gold-tin solder) having high soldering strength as the solder, and the selected gold-tin solder has high thermal conductivity in the hard solder. The increase of the thickness of the eutectic welding layer can improve the welding strength, but the thermal resistance is large; the thickness of the eutectic welding layer is too thin, so that the welding void ratio is increased, and the welding strength is reduced; therefore, the thickness of the eutectic solder layer may need to be tightly controlled to adjust the bond strength versus thermal resistance.
In yet another embodiment, as shown in fig. 8, the first eutectic solder layer 2 includes at least one first solder layer, the first solder layer includes a first indium layer 22 and a first gold-tin solder layer 21 stacked along a set direction, or the first eutectic solder layer 2 includes a first indium layer 22 and at least one first gold-tin solder layer 21 stacked along a set direction; the set direction is the direction in which the heat dissipation substrate 1 points to the chip 5. And/or the second eutectic solder layer 4 includes at least one second solder layer including a second gold-tin solder layer 41 and a second indium layer 42 provided on the second gold-tin solder layer 41 along the set direction, or the second eutectic solder layer 4 includes at least one second gold-tin solder layer 41 and a second indium layer 42 provided on all the second gold-tin solder layers 41 stacked along the set direction.
The poor ductility of the gold-tin solder is liable to induce stress, and in order to prevent the chip 5 from chipping due to thermal stress when the chip 5 is soldered, the problem of the ductility of the gold-tin solder is solved by adding soft solder. Specifically, the soft solder may be In solder, the thickness of the In solder is 0.5-10 μm, and preferably, the thickness of the In solder is about 1 μm; by adopting the scheme of adding indium into gold and tin, the welded chip 5 is not easy to crack, and the welding effect is improved.
Referring to fig. 1 and fig. 9 in combination, fig. 9 is a schematic flow chart of an embodiment of a method for manufacturing a diamond chip according to the present invention, and the method for manufacturing a diamond chip further includes the following steps:
S1: a diamond heat sink layer 3 is provided.
S2: a first metallization layer 6 is plated on the lower surface of the diamond heat sink layer 3, and a second metallization layer 7 is plated on the upper surface of the diamond heat sink layer 3.
S3: and welding the first metallization layer 6 and the heat dissipation substrate 1 by adopting the first eutectic welding layer 2, and welding the second metallization layer 7 and the chip 5 by adopting the second eutectic welding layer 4 to obtain a chip structure.
S4: and cooling the chip structure to obtain the diamond chip.
In some embodiments, the surface treatment of the diamond heat sink layer 3 comprises: firstly, acetone is adopted for ultrasonic treatment for 15min, deionized water is adopted for cleaning for 15min, ethanol is adopted for ultrasonic treatment for 15min, deionized water is adopted for ultrasonic treatment for 15min, and finally nitrogen is adopted for drying the diamond heat dissipation layer 3.
The acetone and ethanol are adopted to clean and remove organic impurities, and after the large-area organic molecules are removed, deionized water is further adopted to clean invisible hydrocarbon left by the previous step, so that the subsequent treatment effect is improved.
In some embodiments, cleaning inspection of the surface of the diamond heat sink layer 3 includes: in a thousand-level clean room, a metallographic microscope is used to observe whether an abnormal condition exists on the surface of the diamond heat dissipation layer 3, such as: whether there are spots, watermarks/stains, dirt or particles, etc.; if the surface of the diamond heat dissipation layer 3 has no abnormal condition (i.e. the surface of the diamond has no spots, watermarks/stains, dirt or particles), the diamond heat dissipation layer is judged to be qualified in cleaning, otherwise, the diamond heat dissipation layer is cleaned again.
In some embodiments, the diamond heat sink layer 3 bonds the die 5 and the heat sink substrate 1 in two bonding schemes: 1. simultaneously welding; 2. the diamond heat dissipation layer 3 is welded with the chip 5 firstly, and after welding, solder with a melting point lower than that of the first welding solder is used to prevent the chip from falling off during welding; the application is preferably realized by adopting a simultaneous welding mode.
Further, the water contact angle can be used to measure whether the surface cleaning process of the diamond heat dissipation layer 3 is finished; for example, if it is detected that the water contact angle of the surface of the diamond heat dissipation layer 3 is less than 16 °, it is determined that the current diamond heat dissipation layer 3 has been cleaned.
For the treatment of the surface of the diamond heat dissipation layer 3 and the inspection of the cleaning condition, intelligent detection can be adopted; such as: a detection model for detecting whether the cleaning is clean is trained in advance, and the detection model can detect whether water stains, particles, spots, watermarks, dirt, particles or water contact angle and the like exist; after the current cleaning is completed, a metallographic microscope is used for collecting an image of the current diamond, and the image is input into a monitoring model, such as an automatic optical inspection (Automated Optical Inspection, AOI) technology, so that whether the current cleaning is qualified or not is detected in a comparison mode.
In some embodiments, the post-weld cooling process time (denoted cooling time) is 5-300 seconds, and the cooling process corresponds to a cooling rate of 20-25 ℃/s.
The structure of the diamond chip will be described in detail.
As shown in fig. 1, the diamond chip includes a heat dissipation substrate 1, a first eutectic solder layer 2, a diamond heat dissipation layer 3, a second eutectic solder layer 4 and a chip 5, which are stacked, wherein a first metallization layer 6 is disposed between the first eutectic solder layer 2 and the diamond heat dissipation layer 3, and a second metallization layer 7 is disposed between the diamond heat dissipation layer 3 and the second eutectic solder layer 4.
The heat dissipation substrate 1 is a copper substrate or an aluminum alloy substrate, and may be made of different materials according to the requirements of different products. The chip 5 and the heat dissipating substrate 1 are both subjected to a metal treatment before processing.
In some embodiments, the thickness of the diamond heat dissipation layer 3 is 50 μm to 1mm, and the surface of the diamond heat dissipation layer 3 is defect-free, so that the bonding force is ensured, and the welding void rate is reduced.
In this scheme, the thermal conductivity of diamond heat dissipation layer 3 is greater than 1800W/(m K), through with diamond heat dissipation layer 3 welding to chip 5 on can improve the thermal conductivity, promote the radiating effect of chip 5, prevent chip 5 overheated, can better exert the performance of chip 5 and increase the life-span of chip 5 simultaneously.
Further, the double-sided roughness of the diamond heat dissipation layer 3 is smaller than 1nm, the flatness is smaller than 1/4λ, λ represents wavelength, namely, a white light interferometer is adopted, 632.8nm wavelength is used for measuring surface flatness, the number of interference fringes is observed, and 1/4λ refers to 1/4 of the number of interference fringes; by the arrangement, the contact area is increased, and the binding force of the coating is ensured.
In some embodiments, referring to fig. 1 and 4 in combination, the first metallization layer 6 includes a first metal oxidation resistant layer 63, a first barrier layer 62, and a first metal bonding layer 61 stacked on the first eutectic solder layer 2; the second metallization layer 7 includes a second metal bonding layer 71, a second barrier layer 72, and a second metal oxidation resistant layer 73 stacked on the diamond heat sink layer 3.
Further, the material of the first barrier layer 62 includes at least one of Pt, ni, cr, W or an alloy thereof; the material of the second barrier layer 72 includes at least one of Pt, ni, cr, W or an alloy thereof.
In other embodiments, referring to fig. 1 and 4 in combination, a first intermediate buffer layer 81 is further disposed between the first barrier layer 62 and the first metal bonding layer 61; a second intermediate buffer layer 82 is also provided between the second barrier layer 72 and the second metal bonding layer 71.
Further, the first intermediate buffer layer 81 is a Cu layer or an Ag layer; the thickness of the first intermediate buffer layer 81 is 8 to 12 times the thickness of the first barrier layer 62. The second intermediate buffer layer 82 is a Cu layer or an Ag layer; the thickness of the second intermediate buffer layer 72 is 8 to 12 times the thickness of the second barrier layer 72.
By providing the intermediate buffer layer (including the first intermediate buffer layer 81 and the second intermediate buffer layer 82) and the barrier layer (including the first barrier layer 62 and the second barrier layer 72) with the thicknesses as described above, that is, the thicknesses of the Cu layer/Ag layer are 8 to 12 times the thicknesses of the barrier layer formed by at least one of Pt, ni, cr, W or an alloy thereof, a superior thermal expansion coefficient can be achieved, a better stress release effect can be obtained in welding cooling and use, not only the release of stress is facilitated, but also an anti-seepage effect can be played to the weld.
In some embodiments, the first metal oxidation resistant layer 63 is an Au layer, and the thickness of the first metal oxidation resistant layer 63 is 50-70000 nm; the first metal bonding layer 61 is a Ti layer, and the thickness of the first metal bonding layer 61 is 50-1000 nm; the thickness of the first barrier layer 62 is 50 to 1000nm. The second metal oxidation resistant layer 73 is an Au layer, and the thickness of the second metal oxidation resistant layer 73 is 50-70000 nm; the second metal bonding layer 71 is a Ti layer, and the thickness of the second metal bonding layer 71 is 50-1000 nm; the thickness of the second barrier layer 72 is 50 to 1000nm.
Further, the thickness of the barrier layer is too thin to provide a poor barrier effect, so that the thickness of the barrier layer is set to be larger than 200nm, and the thickness of the barrier layer is too thick to influence heat dissipation, so that the thickness of the barrier layer is set to be 200-1000 nm.
The metal bonding layer (comprising the first metal bonding layer 61 and the second metal bonding layer 71) ensures the bonding force between the metal and the diamond heat dissipation layer 3, and Ti and diamond form TiC covalent compounds, so that the bonding force is strong.
Further, if the thickness of the bonding layer is too thin, the bonding force with the previous layer is insufficient, and if the thickness of the bonding layer is too thick, the thermal resistance is increased, and the thickness of the bonding layer is set to 50-1000 nm.
The material of the metal oxidation resistant layer (comprising the first metal oxidation resistant layer 63 and the second metal oxidation resistant layer 73) adopts Au, namely the metal oxidation resistant layer is an Au layer, and the solderability is strong, and the antioxidation effect is achieved. Too thin a metal oxidation-resistant layer results in insufficient soldering strength, i.e., too thick an Au layer results in a large thermal resistance, so the Au layer is set to a thickness of 50 to 70000 nm.
In some embodiments, the thickness of the first barrier layer 62 is 200-1000 nm; the ratio of the thicknesses of the first metal bonding layer 61, the first barrier layer 62 and the first metal oxidation resistant layer 63 is 1:1 to 2:3 to 6. The thickness of the second barrier layer 72 is 200-1000 nm; the ratio of the thicknesses of the second metal bonding layer 71, the second barrier layer 72 and the second metal oxidation resistant layer 73 is 1:1 to 2:3 to 6.
The bonding surface of the chip 5, the heat dissipation substrate 1 and the diamond heat dissipation layer 3 is provided with a metallized gold layer, if a gold-tin alloy layer is used as the eutectic solder layer, during welding, gold atoms at the bottom of the chip 5 and gold atoms of the metallized layer on the diamond heat dissipation layer 3 migrate to the eutectic solder layer, so that the proportion of gold content in the eutectic solder layer is increased, the melting point is increased, and a gold-tin alloy with a new proportion is formed. At the same time, tin can also alloy with the barrier layer (e.g., pt), which is required to ensure that the barrier layer cannot be too thin, otherwise, pt and tin react completely, and gold is still penetrating down, affecting the soldering effect.
The eutectic welding layer is generally made of welding materials with the characteristics of high heat conductivity, high welding strength, good ductility, stable chemical property and the like. Specifically, the eutectic solder layer selects a hard solder (such as gold-tin solder) having high soldering strength as the solder, and the selected gold-tin solder has high thermal conductivity in the hard solder. The increase of the thickness of the eutectic welding layer can improve the welding strength, but the thermal resistance is large; the thickness of the eutectic welding layer is too thin, so that the welding void ratio is increased, and the welding strength is reduced; therefore, the thickness of the eutectic solder layer may need to be tightly controlled to adjust the bond strength versus thermal resistance.
The present invention provides the following examples, which are specifically described below, based on the diamond chip having the above-described structure and the method for manufacturing the same.
Example 1
S11: a diamond die with a double-sided roughness less than 1nm and a flatness less than 1/4 lambda is provided.
S12: and carrying out surface treatment and surface cleaning inspection on the diamond bare chip until the water contact angle is smaller than 16 degrees after cleaning, thereby obtaining the diamond heat dissipation layer.
S13: and fixing the diamond heat dissipation layer on the tray, and putting the tray into a magnetron sputtering device for sputtering treatment to form a first metallization layer and a second metallization layer on the upper surface and the lower surface of the diamond heat dissipation layer respectively.
The first metallization layer and the second metallization layer comprise a Ti layer, a Pt layer and an Au layer which are stacked.
S14: and taking out the sputtered diamond heat dissipation layer, fixing the diamond heat dissipation layer on a tray, and putting the diamond heat dissipation layer into an electron beam evaporation device to perform evaporation of a second gold-tin welding layer.
S15: and taking out the manufactured diamond heat dissipation layer.
S16: and (3) stacking the radiating substrate, the evaporated diamond radiating layer, the indium sheet and the chip into a eutectic furnace, and performing eutectic welding treatment.
In this step, the temperature of the eutectic soldering treatment was 300 ℃, and the corresponding down-pressure height of the eutectic soldering treatment was 5cm (i.e., the down-pressure distance of the device was 5cm after the chip was placed on the eutectic solder layer).
S17: and (3) cooling the device obtained in the step (S16) for 15S at a cooling rate of 23 ℃/S to obtain the diamond chip.
Example 2
The preparation method of the diamond chip provided in this example is similar to that in example 1, except that: in this example, the welding temperature of S16 was increased by 10℃compared with example 1, and the welding cooling time was less than 1min.
Example 3
The preparation method of the diamond chip provided in this example is similar to that in example 1, except that: in this example, the welding temperature was increased by 10℃compared with example 1, the welding height was increased by 1 μm (i.e., the depression height was reduced by 1 μm) compared with example 1, and the cooling time was less than 1min.
Example 4
The preparation method of the diamond chip provided in this example is similar to that in example 1, except that: in this example, the welding temperature was increased by 10℃compared to example 2, the welding height was increased by 1 μm compared to example 1, and the cooling time was less than 1min.
Example 5: the diamond chip was prepared by referring to example 1, the materials of the first and second metallization layers were TiPt (AuSn) n (n. Gtoreq.1), i.e., it comprises a Ti layer, a Pt layer and at least 1 AuSn layer, which are laminated, the AuSn layer comprises an Au layer and an Sn layer; the eutectic welding layer adopts gold-tin solder, and the cooling time is less than 1min.
Example 6: in the preparation method of the diamond chip, referring to the embodiment 1, the first metallization layer and the second metallization layer are TiCuPtAu, the eutectic welding layer adopts gold-tin solder, and the cooling time is less than 1min.
Example 7: the preparation method of the diamond chip refers to the embodiment 1, wherein the eutectic welding layer adopts gold-tin solder and indium solder, and the cooling time is less than 1min.
Comparative example 1
S71: a copper substrate is provided.
S72: and depositing solder on the copper substrate to obtain a welding layer.
S73: and placing the chip on the welding layer to realize welding, so as to obtain the chip A.
Example 1 by using a general metallization layer and eutectic solder layer, the cooling time was controlled to meet the manufacturing requirements; examples 2-7 can also meet the manufacturing requirements by changing the welding materials, welding parameters (including welding temperature and welding height) or the structure of the metallization layer, and setting the corresponding cooling time; the embodiments 1-7 can avoid chip fragmentation and have the effect of improving the high thermal conductivity of the chip. Whereas the finished product obtained in the scheme of comparative example 1 had a problem of chip breakage after cooling.
In the test, the current is gradually applied to the chip, the output power is measured, the electro-optical conversion efficiency is calculated, experimental data of the example 1 and the comparative example 1 shown in fig. 10-11 can be obtained, and compared with the chip a, the diamond chip prepared in the example 1 and adopting the diamond heat dissipation layer has improved output power (P) and electro-optical conversion efficiency (photo-to-electron conversion efficiency, PCE) and better performance.
According to the scheme provided by the invention, the welding process is adjusted, the welding flux is optimized, the structure of the metallization layer is changed, or the welding flux (gold-tin welding flux) is adjusted, and the mixed welding flux (Jin Xijia indium welding flux) is used, so that the stress caused by different thermal expansion coefficients between the diamond heat dissipation layer and the chip is released in a stepped manner, and the chip is prevented from being broken; on one hand, the stress between the chip and the diamond heat dissipation layer and the stress of the eutectic welding layer can be released to a certain extent by strictly controlling the cooling time after welding, so that chip fragmentation is avoided; on the other hand, the chip cracking problem caused by stress after welding is further optimized by changing the composition and thickness proportion of the metallization layer, the welding cooling time is shortened, the cooling time is optimized, and the processing efficiency is improved.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The utility model provides a diamond chip, its characterized in that includes heat dissipation base plate, first eutectic welding layer, diamond heat dissipation layer, second eutectic welding layer and the chip of range upon range of setting, first eutectic welding layer with be provided with first metallization layer between the diamond heat dissipation layer, diamond heat dissipation layer with be provided with the second metallization layer between the second eutectic welding layer.
2. The diamond chip according to claim 1, wherein the diamond chip,
The first metallization layer comprises a first barrier layer and a first metal bonding layer which are stacked on the first eutectic welding layer;
and/or the second metallization layer comprises a second metal bonding layer and a second barrier layer which are laminated and arranged on the diamond heat dissipation layer.
3. The diamond chip of claim 2, wherein the first eutectic solder layer comprises a gold layer and at least one first gold-tin solder layer stacked along a set direction, the first gold-tin solder layer comprising a tin layer and a gold layer stacked along the set direction; the set direction is the direction in which the heat dissipation substrate points to the chip;
And/or the second eutectic welding layer comprises at least one layer of second gold-tin welding layer and gold layers which are arranged on all the second gold-tin welding layers in a lamination mode along the set direction, and the second gold-tin welding layer comprises gold layers and tin layers which are arranged in a lamination mode along the set direction.
4. The diamond chip according to claim 2, wherein,
The first metallization layer further comprises a first metal oxidation resistant layer, and the first metal oxidation resistant layer is arranged between the first barrier layer and the first eutectic welding layer;
and/or, the second metallization layer further comprises a second metal oxidation resistant layer, and the second metal oxidation resistant layer is arranged between the second barrier layer and the second eutectic welding layer.
5. The diamond chip of claim 4, wherein the first eutectic solder layer comprises at least one first gold-tin solder layer, the first gold-tin solder layer comprising a gold layer and a tin layer stacked along a set direction; or the first gold-tin welding layer is a gold-tin alloy layer; the set direction is the direction in which the heat dissipation substrate points to the chip;
And/or the second eutectic welding layer comprises at least one layer of second gold-tin welding layer, and the second gold-tin welding layer comprises a tin layer and a gold layer which are stacked along the set direction; or the second gold-tin welding layer is a gold-tin alloy layer.
6. The diamond chip according to claim 4, wherein,
The material of the first barrier layer comprises at least one of Pt, ni, cr, W or an alloy thereof; or a first middle buffer layer is arranged between the first barrier layer and the first metal bonding layer, and the first middle buffer layer is a Cu layer or an Ag layer; the thickness of the first intermediate buffer layer is 8-12 times that of the first barrier layer;
And/or the material of the second barrier layer comprises at least one of Pt, ni, cr, W or an alloy thereof; or a second intermediate buffer layer is arranged between the second barrier layer and the second metal bonding layer, and the second intermediate buffer layer is a Cu layer or an Ag layer; the thickness of the second intermediate buffer layer is 8-12 times that of the second barrier layer;
And/or the first metal oxidation resistance layer is an Au layer, and the thickness of the first metal oxidation resistance layer is 50-70000 nm; the first metal bonding layer is a Ti layer, and the thickness of the first metal bonding layer is 50-1000 nm; the thickness of the first barrier layer is 50-1000 nm;
And/or the second metal oxidation resistance layer is an Au layer, and the thickness of the second metal oxidation resistance layer is 50-70000 nm; the second metal bonding layer is a Ti layer, and the thickness of the second metal bonding layer is 50-1000 nm; the thickness of the second barrier layer is 50-1000 nm;
and/or the thickness of the first eutectic welding layer is 8-12 mu m;
And/or the thickness of the second eutectic welding layer is 8-12 mu m.
7. The diamond chip according to claim 6, wherein the diamond chip,
The thickness of the first barrier layer is 200-1000 nm; and/or the ratio of the thicknesses of the first metal bonding layer, the first barrier layer and the first metal oxidation resistance layer is 1:1-2:3-6;
And/or the thickness of the second barrier layer is 200-1000 nm; and/or the thickness ratio of the second metal bonding layer, the second barrier layer and the second metal oxidation resistance layer is 1:1-2:3-6.
8. The diamond chip according to any one of claim 1,2 or 4,
The first eutectic solder layer comprises at least one first indium layer; or the first eutectic welding layer comprises at least one first welding material layer, the first welding material layer comprises a first indium layer and a first gold tin welding layer which are stacked along a set direction, or the first eutectic welding layer comprises a first indium layer and at least one first gold tin welding layer which are stacked along the set direction; the set direction is the direction in which the heat dissipation substrate points to the chip;
And/or, the second eutectic solder layer comprises at least one second indium layer; or the second eutectic welding layer comprises at least one second welding material layer, the second welding material layer comprises a second gold-tin welding layer and a second indium layer arranged on the second gold-tin welding layer along the set direction, or the second eutectic welding layer comprises at least one second gold-tin welding layer and a second indium layer arranged on all the second gold-tin welding layers in a lamination mode along the set direction;
and/or the thickness of the first indium layer is 0.5-10 mu m;
and/or the thickness of the second indium layer is 0.5-10 mu m.
9. The preparation method of the diamond chip is characterized by comprising the following steps of:
Providing a diamond heat dissipation layer;
plating a first metallization layer on the lower surface of the diamond heat dissipation layer, and plating a second metallization layer on the upper surface of the diamond heat dissipation layer;
Welding the first metallization layer and the heat dissipation substrate by adopting a first eutectic welding layer, and welding the second metallization layer and the chip by adopting a second eutectic welding layer to obtain a chip structure;
and cooling the chip structure to obtain the diamond chip.
10. The method for manufacturing a diamond chip according to claim 9, wherein the cooling treatment is performed for 5-300 seconds, and the cooling rate corresponding to the cooling treatment is 20-25 ℃/s.
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