CN118092068A - Method, apparatus and medium for light source mask optimization - Google Patents

Method, apparatus and medium for light source mask optimization Download PDF

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Publication number
CN118092068A
CN118092068A CN202410529554.4A CN202410529554A CN118092068A CN 118092068 A CN118092068 A CN 118092068A CN 202410529554 A CN202410529554 A CN 202410529554A CN 118092068 A CN118092068 A CN 118092068A
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mask
light source
pattern
wafer
patterns
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CN118092068B (en
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Advanced Manufacturing EDA Co Ltd
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Advanced Manufacturing EDA Co Ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

Methods, apparatus, and media for light source mask optimization are provided according to example embodiments of the present disclosure. The method comprises the following steps: acquiring information of a mask layout comprising a plurality of mask patterns and a light source; generating a plurality of wafer patterns formed on the wafer by using the mask layout and the light source through lithography simulation, wherein the plurality of wafer patterns respectively correspond to the plurality of mask patterns; determining an imaging cost associated with the formation of the plurality of wafer patterns; and determining a target illumination pattern of the light source and the mask layout by changing a target size of at least one of the plurality of mask patterns based on the imaging cost. In this way, no manual adjustment of the target size is required, and the SMO processing efficiency is improved.

Description

Method, apparatus and medium for light source mask optimization
Technical Field
Embodiments of the present disclosure relate generally to the field of integrated circuits and, more particularly, relate to layout processing methods, apparatuses, and media.
Background
A circuit layout (which may be simply referred to as a layout) is a series of geometric figures converted from a designed and simulated optimized circuit, and includes physical information data related to devices such as integrated circuit dimensions, topology definitions of various layers, and the like. The integrated circuit manufacturer manufactures a mask from this data. The layout pattern on the mask determines the feature size of the on-chip device or the link physical layer. At the same time, the lithographic resolution also determines the dimensions of these features on the chip.
Light Source Mask Optimization (SMO) is a resolution enhancement technique for ultra-small size pattern lithography. The optical performance is enhanced by improving the lithography process window in the ultra-small size node by co-optimizing the light source and mask in the lithography process during SMO.
Disclosure of Invention
In a first aspect of the present disclosure, a method for light source mask optimization is provided. The method comprises the following steps: acquiring information of a mask layout comprising a plurality of mask patterns and a light source; generating a plurality of wafer patterns formed on the wafer by using the mask layout and the light source through lithography simulation, wherein the plurality of wafer patterns respectively correspond to the plurality of mask patterns; determining an imaging cost associated with the formation of the plurality of wafer patterns; and determining a target illumination pattern of the light source and the mask layout by changing a target size of at least one of the plurality of mask patterns based on the imaging cost.
In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor, and a memory coupled to the processor. The memory has instructions stored therein that, when executed by the processor, cause the electronic device to perform a method according to the first aspect of the present disclosure.
In a third aspect of the present disclosure, a computer-readable storage medium is provided. The computer readable storage medium has a computer program stored thereon. The computer program, when executed by a processor, implements a method according to the first aspect of the present disclosure.
As will be appreciated from the following description, according to embodiments of the present disclosure, a target size of a mask pattern may be taken as a variable, and the light source and the mask layout may be optimized by adjusting the target size. In this way, the post engineer does not need to manually adjust the target size, which advantageously increases SMO efficiency and further facilitates increasing wafer yield.
It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:
FIG. 1A shows a schematic diagram of an example environment in which embodiments of the present disclosure can be implemented;
FIG. 1B shows a schematic diagram of an example illumination pattern of a light source;
FIG. 1C illustrates a schematic diagram of another example illumination pattern of a light source;
FIG. 2 illustrates a flow chart of a method for light source mask optimization in accordance with some embodiments of the present disclosure;
FIG. 3 illustrates a flow chart of a method of determining imaging costs according to some embodiments of the present disclosure;
FIG. 4 illustrates a flow chart of a method of determining an error cost component according to some embodiments of the present disclosure;
FIG. 5 illustrates a flowchart of a method of determining an imaging error corresponding to a mask pattern, according to some embodiments of the present disclosure; and
Fig. 6 illustrates a block diagram of an electronic device in which one or more embodiments of the disclosure may be implemented.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.
As used herein, the term "illumination mode" refers to the spatial intensity distribution of a light beam in a pupil plane of an illumination system, which is centered with respect to an axis or optical axis of the illumination system. The illumination modes may include various types, such as a conventional illumination mode, an annular illumination mode, a two-pole illumination mode, a four-pole illumination mode. The illumination pattern may also be referred to as a "light source shape". In embodiments of the present disclosure, "determining a lighting pattern" or similar expressions means determining the type of lighting pattern and parameters defining its specific shape. For example, for an annular illumination mode, the parameters include an inner diameter and an outer diameter of the annular shape. "determining a target illumination pattern" means determining various parameters of the light source.
FIG. 1A illustrates a schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented. In example environment 100, electronic device 110 takes mask layout 102 as input. Mask layout 102 includes a plurality of mask patterns, such as test patterns. In the example of FIG. 1A, mask layout 102 is shown to include two mask patterns 1021 and 1022 having a predetermined pitch (pitch). Of course, it should be understood that the form of such a mask layout 102 is merely illustrative and is not intended to limit the scope of the present disclosure. In embodiments of the present disclosure, mask layout 102 may include any number and shape of mask patterns, or mask patterns that are prone to problems in lithography.
The electronic device 110 also obtains information of the light source, also referred to as light source information 104, for example, the light source information 104 may include a light source map and/or various suitable light source parameters. The light source information 104 is generated by the light source in the illumination mode. The light source information 104 may describe the intensity distribution of light emitted by the light source in the lithography system in any suitable manner for use in lithography simulation.
The electronic device 110 may perform SMO to determine the target lighting pattern 107. In particular, the electronic device 110 may determine what type of illumination pattern the target illumination pattern 107 is and one or more parameters for that type of illumination pattern. For example, the target illumination 107 may be determined to be a ring illumination pattern and values of the inner and outer diameters of the ring. For illustrative purposes only, fig. 1B shows an example annular illumination pattern 121 and fig. 1C shows an example quadrupole illumination pattern 122, as examples. Embodiments of the present disclosure may be applicable to any suitable type of illumination pattern.
In the example environment 100, the electronic device 110 may be any type of device having computing capabilities, including a terminal device or a server device. The terminal device may be any type of mobile terminal, fixed terminal, or portable terminal, including a mobile handset, desktop computer, laptop computer, notebook computer, netbook computer, tablet computer, media computer, multimedia tablet, personal Communication System (PCS) device, personal navigation device, personal Digital Assistant (PDA), audio/video player, digital camera/camcorder, positioning device, television receiver, radio broadcast receiver, electronic book device, game device, or any combination of the preceding, including accessories and peripherals for these devices, or any combination thereof. The server devices may include, for example, computing systems/servers, such as mainframes, edge computing nodes, computing devices in a cloud environment, and so forth.
It should be understood that the structure and function of environment 100 are described for illustrative purposes only and are not meant to suggest any limitation as to the scope of the disclosure. Example embodiments according to the present disclosure will be described in detail below with reference to fig. 2 to 4.
As briefly mentioned above, in SMO processes, the light source and mask patterns need to be co-optimized in order to obtain a clearer wafer pattern. In conventional SMOs, the user is required to give the target size of the graphic. Then, in the SMO process, an optimal solution of the light source information and the mask pattern is calculated according to a given target size. However, in some cases, the optimal solution of the light source and the mask pattern may not be determined at a given target size, or the determined optimal solution may not be implemented in an actual process (e.g., the process window determined according to the given target size is too small to exceed the process accuracy). For this case, it is also necessary that a post engineer empirically make manual adjustments to the target dimensions, and then re-optimize the light source and mask pattern based on the adjusted target dimensions. However, since the adjusted target size is empirically derived, the adjustment of the target size may not be accurate. This also requires the user to make multiple adjustments to the target size, which severely impacts the optimization efficiency of SMO.
To this end, embodiments of the present disclosure provide a solution for light source mask optimization to address or at least partially address the above-mentioned problems and/or other potential problems in conventional approaches. According to an embodiment of the present disclosure, information of a mask layout including a plurality of mask patterns and a light source is acquired; generating a plurality of wafer patterns formed on the wafer by using the mask layout and the light source through lithography simulation, wherein the plurality of wafer patterns respectively correspond to the plurality of mask patterns; determining an imaging cost associated with the formation of the plurality of wafer patterns; and determining a target illumination pattern of the light source and the mask layout by changing a target size of at least one of the plurality of mask patterns based on the imaging cost. In this way, the target size of the mask pattern can be used as a variable, and the light source and mask layout can be optimized by adjusting the target size. In this way, the post engineer does not need to manually adjust the target size, which advantageously increases SMO efficiency and further facilitates increasing wafer yield.
Example embodiments of the present disclosure are described in detail below with continued reference to the drawings.
Fig. 2 illustrates a flow chart of a method 200 for light source mask optimization according to some embodiments of the present disclosure. In some embodiments, the method 200 may be performed by the electronic device 110 as shown in fig. 1A, and the method 200 will be described below with reference to fig. 1A for illustrative purposes only. It should be understood that method 200 may also include additional blocks not shown and/or may omit certain block(s) shown, the scope of the present disclosure not being limited in this respect.
At block 210, electronic device 110 obtains information, i.e., light source information 104, for a mask layout 102 including a plurality of mask patterns and a light source. In some embodiments, the electronic device 110 may also obtain initial values of target sizes of the plurality of mask patterns. For example, the initial value may be initially set by the user, or determined by a previous round of optimization. Mask layout 102 may include the shape of each mask pattern and the location of each mask pattern in the mask. In some embodiments, the light source information 104 may describe an intensity distribution of light emitted by the light source in the lithography system. For example, the light source information 104 may include a light source map and/or various suitable light source parameters. The light source map may describe, for example, the light intensity distribution in one or more planes of the wafer.
In some embodiments, the light source information 104 may be an initial value entered by a user into the electronic device during the optimization process. In some other embodiments, the light source information 104 may also be an intermediate result in the history optimization process. For example, the light source information 104 may be light source information 104 determined in an optimization based on a previous round or rounds. Similarly, mask layout 102 may be a user-supplied initial mask layout or a preliminary optimized layout obtained after one or more calculations, which may be considered as an intermediate result of SMO.
At block 220, the electronic device 110 generates a plurality of wafer patterns formed on the wafer using the mask layout 102 and the light source via lithography simulation, the plurality of wafer patterns corresponding to the plurality of mask patterns, respectively. That is, the wafer patterns are in one-to-one correspondence with the mask patterns. Each wafer pattern may be considered as a pattern that the corresponding mask pattern would form on the wafer under the current light source parameters. In block 220, any suitable lithographic simulation model or tool may be utilized, embodiments of the present disclosure are not limited in this respect.
At block 230, the electronic device 110 determines an imaging cost associated with the formation of the plurality of wafer patterns. The imaging cost may be represented by a cost function. The cost function is used to evaluate the simulation or optimization results. The imaging cost may include one or more cost components, each of which may relate to any suitable parameter for assessing a process window or imaging quality.
In some embodiments, the imaging cost may include an error cost component, the magnitude of which may be used to evaluate the imaging quality of the wafer pattern (e.g., the sharpness of the wafer pattern). The imaging of the wafer pattern may be optimized by minimizing the error cost component. Further, in some embodiments, the Error cost component may include an Edge Placement Error (EPE) cost. How the error cost component is determined will be described in detail below in connection with fig. 3 and 4.
Alternatively or additionally, in some embodiments, the imaging cost may also include components associated with other parameters. For example, cost components associated with depth of focus (DOF), exposure Latitude (EL), imaging light Intensity Log Slope (ILS), mask Error Enhancement Factor (MEEF), etc. may be included.
As an example and without intending to be limiting, the cost function may be calculated according to:
CF（1）
Where CF represents the cost of the imaging, Representing EPE cost component,/>Weights representing EPE cost components,/>Representing normalized imaging light intensity log slope (NILS) cost component,/>Representing the weights of the NILS cost components.
At block 240, the electronic device 110 determines a target illumination pattern 107 of the light source and the mask layout 102 by changing a target size of at least one mask pattern of the plurality of mask patterns based on the imaging cost. For example, the target size of the at least one mask pattern may be changed from an initial value of the target size of the at least one mask pattern in a manner that reduces imaging costs. That is, the light source and mask layout are optimized with the target size of at least one mask pattern as a variable. Thus, an optimized light source and an optimized mask layout can be determined. The specific shape, size, and location of the mask pattern may vary in the optimized mask layout as compared to before the optimization. One or more parameters of the optimized light source may be changed compared to before the optimization. These optimized parameters define the target illumination pattern 107.
In some embodiments, the mask patterns (i.e., at least one of the above-mentioned mask patterns) whose target size is used as a variable may include all mask patterns. In some embodiments, the mask pattern for which the target size is used as a variable may be selected from a plurality of mask patterns according to the imaging quality of the wafer pattern. Such embodiments will be described in detail below.
In some embodiments, a gradient of the imaging cost may be determined. Further, the optimized light source and the optimized mask layout may be determined by reducing the gradient.
In some embodiments, the solution optimization problem performed at block 240. Specifically, the electronic device 110 may determine the minimized imaging cost as an optimization target for the optimization problem, and may determine the target size of the at least one mask pattern as a variable for the optimization problem. In this manner, electronic device 110 may determine the light source parameters and mask layout for the illumination pattern of the light source through the optimization problem.
In addition, in order to solve the optimization problem, a termination condition of the optimization problem may also be set. In some embodiments, the termination condition may be to reduce the imaging cost to less than a predetermined threshold. In some other embodiments, the termination condition may be optimizing up to a predetermined number of rounds.
In some embodiments, the target size of the mask pattern may not be taken as a variable at the initial optimization. If the optimized light source parameters are not available or the resulting light source parameters do not meet the process requirements in this case (e.g., the process window corresponding to minimizing the imaging cost is too small to meet the process requirements), the electronic device 110 may determine the target size of at least one mask pattern as a variable of the optimization problem to optimize the light source and layout.
Finally, the electronic device 110 may output the optimally adjusted light source (e.g., the target illumination pattern 107 of the light source) and the optimally adjusted mask layout 102.
The general example process of light source mask optimization is described above. Example embodiments for determining imaging costs are described below.
Fig. 3 illustrates a flow chart of a method 300 for determining imaging costs according to some embodiments of the present disclosure. In some embodiments, the method 300 may be performed by the electronic device 110 as shown in fig. 1A. It should be understood that method 300 may also include additional blocks not shown and/or may omit certain block(s) shown, the scope of the present disclosure not being limited in this respect. The method 300 may be considered an example implementation of, or at least a portion of, the block 230.
At block 310, the electronic device 110 determines, for each of the plurality of wafer patterns, a simulated size corresponding to the target size. For example, electronic device 110 may simulate a plurality of mask patterns on mask layout 102 to obtain wafer patterns corresponding to the plurality of mask patterns on mask layout 102, respectively. Further, the electronic device 110 may also obtain the simulated dimensions corresponding to the wafer pattern.
At block 320, the electronic device 110 determines an error cost component as at least a portion of the imaging cost based on the respective simulated dimensions of the plurality of wafer patterns and the respective target dimensions of the plurality of mask patterns. In some embodiments, the electronic device 110 may determine the error cost component based on the target size of the mask pattern and the simulated size of the corresponding wafer pattern resulting from the simulation. For example, the electronic device 110 may determine the error cost component based at least on a difference of the target size and the corresponding simulated size.
In some embodiments, the error cost component may include an EPE cost component, e.g., as shown in equation (1). The electronic device 110 may determine the EPE cost component based on the target size of the mask pattern and the simulated size of the corresponding wafer pattern.
An example of determining the error cost component is described below with reference to fig. 4. Fig. 4 illustrates a flow chart of a method 400 for determining an error cost component according to some embodiments of the present disclosure. In some embodiments, the method 400 may be performed by the electronic device 110 as shown in fig. 1A. It should be understood that method 400 may also include additional blocks not shown and/or may omit certain block(s) shown, the scope of the present disclosure not being limited in this respect.
Method 400 may be viewed as an example implementation of block 320. Specifically, to determine the error cost component, the electronic device 110 may perform block 410 and block 420 in method 400 for each of a plurality of mask patterns, thereby obtaining a plurality of imaging errors corresponding to the plurality of mask patterns, respectively.
As shown in fig. 4, at block 410, the electronic device 110 determines an imaging quality of a wafer pattern of the plurality of wafer patterns that corresponds to the mask pattern. In some embodiments, the imaging quality may include an Intensity Log Slope (ILS) of the wafer pattern. Of course, ILS is only one example of imaging quality, and other suitable parameters may be used to represent imaging quality of a wafer pattern. The ILS will be described below as an example, but it should be understood that other imaging quality parameters are possible.
At block 420, an imaging error corresponding to the mask pattern is determined based on the target size of the mask pattern, the simulated size of the wafer pattern corresponding to the mask pattern, and the imaging quality.
Fig. 5 illustrates a flowchart of a method 500 of determining an imaging error corresponding to a mask pattern according to some embodiments of the present disclosure, in some embodiments, the method 500 may be performed by the electronic device 110 as illustrated in fig. 1A. It should be understood that method 500 may also include additional blocks not shown and/or may omit certain block(s) shown, the scope of the present disclosure not being limited in this respect. Method 500 may be viewed as an example implementation of block 420.
At block 510, the electronic device 110 determines an edge placement error EPE corresponding to the mask pattern based on the target size of the mask pattern and the simulated size of the wafer pattern corresponding to the mask pattern. As an example, the edge placement error of the ith mask pattern may be represented as EPE i, and EPE i may be determined based on the difference between the target size of the ith mask pattern and the simulated size of the corresponding wafer pattern of the ith mask pattern.
At block 520, the electronic device 110 determines an error adjustment factor based on the imaging quality of the wafer pattern corresponding to the mask pattern. As mentioned above, for example, the imaging quality may include the ILS of the wafer pattern. As an example, the error adjustment factor corresponding to the i-th mask pattern may be represented as ES i. The imaging quality of the wafer pattern corresponding to the ith mask pattern may be denoted as ILS i.
In some embodiments, the error adjustment factor ES i may be determined based on the relationship of the imaging quality ILS i to the threshold quality C 3. Specifically, for the ith mask pattern, the electronic device 110 may determine whether the imaging quality of the wafer pattern corresponding to the mask pattern is higher than the threshold quality C 3. If the imaging quality is greater than or equal to the threshold quality C 3, the electronic device 110 may determine the first adjustment value (which may be preset) as the error adjustment factor ES i. If the imaging quality is below the threshold quality C 3, the electronic device 110 may calculate an error adjustment factor ES i based on the second adjustment value (which may be preset) and the imaging quality. For example, the product of the second adjustment value and the imaging quality may be determined as the error adjustment factor ES i.
As an example, the error adjustment factor ES i may be determined according to:
（2）
Wherein the first adjustment value C 1, the second adjustment value C 2, and the threshold mass C 3 are each associated with a lithographic process, C 1、C2、C3 may each be adjusted based on the particular lithographic process.
At block 530, the electronic device 110 may calculate an imaging error corresponding to the mask pattern based on the edge placement error determined at block 510 and the error adjustment factor determined at block 520. For example, EPE divided by the error adjustment factor may be used as the imaging error. As an example, the imaging error of the ith mask pattern may be calculated as。
With continued reference to fig. 4. At block 430, the electronic device 110 may derive an error cost component based on the plurality of imaging errors and the number of the plurality of mask patterns. As an example, the error cost component of mask layout 102 may be represented as an EPE cost, and the EPE cost may be determined according to the following equation.
（3）
Where EPE i is the edge placement error of the ith mask pattern, ES i is the error adjustment factor of the ith mask pattern, and n is the number of multiple mask patterns in mask layout 102.
Thus, an error cost component EPE cost can be obtained, and an imaging cost can be obtained by substituting it into equation (1) and combining other optional components.
As briefly mentioned above, in some embodiments, a mask pattern whose target size is used as a variable may be selected from a plurality of mask patterns according to the imaging quality of the corresponding wafer pattern. Specifically, the electronic device 110 may determine at least one mask pattern from the plurality of mask patterns for the target size change based on respective imaging qualities (e.g., ILS) of the plurality of wafer patterns. For example, the electronic device 110 may set the target size of the mask pattern corresponding to the wafer pattern with the poor imaging quality as a variable, and may set the target size of the mask pattern corresponding to the wafer pattern with the good imaging quality as a fixed. In such an embodiment, a portion of the mask pattern is selected based on imaging quality so that the target size of all mask patterns need not be changed during the optimization process. This may reduce the complexity and computational effort of the optimization, further contributing to improved SMO efficiency.
In some embodiments, for each wafer pattern, electronic device 110 may determine whether the imaging quality (e.g., ILS) of the wafer pattern is below a threshold quality. If the imaging quality of the wafer pattern is below the threshold quality, the electronic device 110 may determine the mask pattern corresponding to the modified wafer pattern as one of the at least one mask pattern. For example, if the imaging quality of a certain wafer pattern (e.g., the imaging quality ILS j of the wafer pattern corresponding to the jth mask pattern) is less than the threshold quality C 3, the jth mask pattern may be determined as a mask pattern requiring a change in the target size.
In some alternative embodiments, the electronic device 110 may determine a predetermined number of wafer patterns having a low imaging quality based on respective imaging qualities of the plurality of wafer patterns. The electronic device 110 determines mask patterns corresponding to a predetermined number of wafer patterns, respectively, for the target size change. For example, the electronic device 110 may further screen out a predetermined number (e.g., 10) of wafer patterns with the worst imaging quality from the imaging qualities (e.g., ILS 1～ILSn) of the wafer patterns corresponding to the plurality of mask patterns, and determine the mask patterns corresponding to the wafer patterns as mask patterns that need to change the target size.
From the above description, in some embodiments of the present disclosure, a simulated size of each of a plurality of wafer patterns is calculated and an error cost component is determined in conjunction with a target size of a corresponding mask pattern of a plurality of mask patterns. The error cost component is then considered as at least a portion of the imaging cost to optimize the light source (e.g., the target illumination pattern of the light source) and the mask layout (e.g., the respective shapes of the mask patterns and their locations in the mask plate) as a whole. In the optimization, the electronic device may be variable with a target size of at least a portion of the mask pattern. In this way, the electronic equipment can optimize the target size when performing SMO optimization processing, so that the processing efficiency of SMO is improved, on the other hand, the target size can be used as a variable, the situation that a user needs to adjust the target value according to experience is avoided, the working intensity of the user is reduced, and meanwhile, lower imaging cost can be obtained through more calculation times. In addition, the critical patterns with poor process window in the process can be improved through optimizing the target size, so that the yield is improved.
Fig. 6 illustrates a block diagram of an electronic device 600 in which one or more embodiments of the disclosure may be implemented. The electronic device 600 may be used, for example, to implement the electronic device 110 shown in fig. 1A. It should be understood that the electronic device 600 illustrated in fig. 6 is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein.
As shown in fig. 6, the electronic device 600 is in the form of a general-purpose electronic device. The components of electronic device 600 may include, but are not limited to, one or more processors 610 or processing units, memory 620, storage 630, one or more communication units 640, one or more input devices 650, and one or more output devices 660. The processing unit may be a real or virtual processor and is capable of performing various processes according to programs stored in the memory 620. In a multiprocessor system, multiple processing units execute computer-executable instructions in parallel to increase the parallel processing capabilities of electronic device 600.
The electronic device 600 typically includes a number of computer storage media. Such a medium may be any available medium that is accessible by electronic device 600, including, but not limited to, volatile and non-volatile media, removable and non-removable media. The memory 620 may be volatile memory (e.g., registers, cache, random Access Memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 630 may be a removable or non-removable media and may include machine-readable media such as flash drives, magnetic disks, or any other media that may be capable of storing information and/or data (e.g., training data for training) and may be accessed within electronic device 600.
The electronic device 600 may further include additional removable/non-removable, volatile/nonvolatile storage media. Although not shown in fig. 6, a magnetic disk drive for reading from or writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk may be provided. In these cases, each drive may be connected to a bus (not shown) by one or more data medium interfaces. Memory 620 may include a computer program product having one or more program modules configured to perform the various methods or acts of the various embodiments of the present disclosure.
The communication unit 640 enables communication with other electronic devices through a communication medium. Additionally, the functionality of the components of the electronic device 600 may be implemented in a single computing cluster or in multiple computing machines capable of communicating over a communication connection. Thus, the electronic device 600 may operate in a networked environment using logical connections to one or more other servers, a network Personal Computer (PC), or another network node.
The input device 650 may be one or more input devices such as a mouse, keyboard, trackball, etc. The output device 660 may be one or more output devices such as a display, speakers, printer, etc. The electronic device 600 may also communicate with one or more external devices (not shown), such as storage devices, display devices, etc., with one or more devices that enable a user to interact with the electronic device 600, or with any device (e.g., network card, modem, etc.) that enables the electronic device 600 to communicate with one or more other electronic devices, as desired, via the communication unit 640. Such communication may be performed via an input/output (I/O) interface (not shown).
According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which one or more computer instructions are stored, wherein the one or more computer instructions are executed by a processor to implement the method described above.
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various implementations of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The foregoing description of implementations of the present disclosure has been provided for illustrative purposes, is not exhaustive, and is not limited to the implementations disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various implementations described. The terminology used herein was chosen in order to best explain the principles of each implementation, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand each implementation disclosed herein.

Claims (13)

1. A method for light source mask optimization, comprising:
Acquiring information of a mask layout comprising a plurality of mask patterns and a light source;
Generating a plurality of wafer patterns formed on a wafer by using the mask layout and the light source through photoetching simulation, wherein the plurality of wafer patterns respectively correspond to the plurality of mask patterns;
Determining an imaging cost associated with formation of the plurality of wafer patterns; and
Based on the imaging cost, a target illumination pattern of the light source and the mask layout are determined by changing a target size of at least one mask pattern of the plurality of mask patterns.
2. The method for light source mask optimization of claim 1, wherein determining an imaging cost associated with formation of the plurality of wafer patterns comprises:
determining a simulation size corresponding to the target size for each of the plurality of wafer patterns; and
An error cost component is determined as at least a portion of the imaging cost based on respective simulated dimensions of the plurality of wafer patterns and respective target dimensions of the plurality of mask patterns.
3. The method for light source mask optimization of claim 2, wherein determining an error cost component comprises:
For each of the plurality of mask patterns, performing the following operations to obtain a plurality of imaging errors respectively corresponding to the plurality of mask patterns, respectively:
determining imaging quality of a wafer pattern corresponding to the mask pattern in the plurality of wafer patterns;
determining an imaging error corresponding to the mask pattern based on a target size of the mask pattern, a simulated size of a wafer pattern corresponding to the mask pattern, and the imaging quality; and
The error cost component is derived based on the plurality of imaging errors and the number of the plurality of mask patterns.
4. A method for light source mask optimization as defined in claim 3, wherein said determining an imaging error corresponding to the mask pattern comprises:
Determining an edge placement error corresponding to the mask pattern based on a target size of the mask pattern and a simulated size of a wafer pattern corresponding to the mask pattern;
determining an error adjustment factor based on the imaging quality of the wafer pattern corresponding to the mask pattern; and
The imaging error corresponding to the mask pattern is calculated based on the edge placement error and the error adjustment factor.
5. The method for light source mask optimization of claim 4, wherein determining an error adjustment factor comprises:
determining whether the imaging quality of a wafer pattern corresponding to the mask pattern is higher than a threshold quality;
Determining a first adjustment value as the error adjustment factor in response to the imaging quality being greater than or equal to the threshold quality; and
The error adjustment factor is calculated based on a second adjustment value and the imaging quality in response to the imaging quality being below the threshold quality.
6. The method for light source mask optimization of claim 5, wherein the first adjustment value, the second adjustment value, and the threshold quality are related to a lithographic process.
7. The method for light source mask optimization of claim 2, wherein the imaging quality comprises an Intensity Log Slope (ILS) of the wafer pattern.
8. The method for light source mask optimization of claim 1, further comprising:
The at least one mask pattern is determined from the plurality of mask patterns for target size change based on respective imaging qualities of the plurality of wafer patterns.
9. The method for light source mask optimization of claim 8, wherein determining the at least one mask pattern from the plurality of mask patterns comprises:
Determining, for a given wafer pattern of the plurality of wafer patterns, whether an imaging quality of the given wafer pattern is below a threshold quality; and
In response to the imaging quality of the given wafer pattern being below the threshold quality, a mask pattern corresponding to the given wafer pattern is determined to be one of the at least one mask pattern.
10. The method for light source mask optimization of claim 8, wherein determining the at least one mask pattern from the plurality of mask patterns comprises:
Determining a predetermined number of wafer patterns with low imaging quality according to the corresponding imaging quality of the plurality of wafer patterns; and
Mask patterns corresponding to the predetermined number of wafer patterns, respectively, are determined for target size change.
11. The method for light source mask optimization of claim 1, wherein determining the target illumination pattern of the light source and the mask layout comprises:
Determining the imaging cost minimized as an optimization objective of an optimization problem;
Determining a target size of the at least one mask pattern as a variable of the optimization problem; and
And determining light source parameters of the illumination mode of the light source and the mask layout by solving the optimization problem.
12. An electronic device, comprising:
At least one processing unit; and
At least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, which when executed by the at least one processing unit, cause the electronic device to perform the method of any one of claims 1 to 11.
13. A computer readable storage medium, having stored thereon a computer program, characterized in that the computer program is executable by a processor to implement the method according to any of claims 1 to 11.
CN202410529554.4A 2024-04-28 2024-04-28 Method, apparatus and medium for light source mask optimization Active CN118092068B (en)

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