CN118074641A - Programmable gain amplifying circuit and control method - Google Patents
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Abstract
The invention relates to the technical field of amplifiers, in particular to a programmable gain amplifying circuit and a control method. Wherein the circuit comprises: the memristor feedback array comprises a target amplifying circuit, a memristor feedback array and a control module; the first input end of the target amplifying circuit is connected with a signal source; the second input end of the target amplifying circuit is connected with the memristor feedback array; the output end of the target amplifying circuit is connected with the memristor feedback array; the control module is connected with the memristor feedback array and is used for responding to the adjusting instruction, adjusting the resistance state of the memristor in the memristor feedback array according to the adjusting instruction, so that the resistance value of the memristor feedback array reaches a target resistance value, and the problem of high hardware resource consumption of the traditional programmable gain amplifying circuit is solved.
Description
Technical Field
The invention relates to the technical field of amplifiers, in particular to a programmable gain amplifying circuit and a control method.
Background
Amplification circuits are widely used in electronic circuits in a variety of different fields, such as the field of audio processing, the field of wireless communication, the field of measurement and instrumentation, the field of data processing of sensors, etc., for amplitude amplifying an input weak signal for signal processing. Along with the development of technology, the requirements of electronic circuits in various fields on the sensitivity and dynamic range of weak signals are gradually increased, and in order to avoid the difficulty in flexibly adjusting the weak signals of the traditional fixed gain amplifier, the prior art adopts a programmable gain amplifying circuit to realize the flexible adjustment of the amplitude of the weak signals by regulating and controlling the gain.
The existing Programmable gain amplifying circuit, such as PGA (Programmable GAIN AMPLIFIER), is implemented by externally connecting a large number of resistors with different resistance values, and by switching the on states of the resistors with different resistance values. However, this approach requires a large amount of hardware resources consuming resistor and circuit space, and thus, a new programmable gain amplifier circuit is necessary.
Disclosure of Invention
The invention provides a programmable gain amplifying circuit and a control method, which are used for solving the problem of high hardware resource consumption of the conventional programmable gain amplifying circuit.
In one aspect, the present invention provides a programmable gain amplification circuit comprising: the memristor feedback array comprises a target amplifying circuit, a memristor feedback array and a control module;
the first input end of the target amplifying circuit is connected with a signal source;
The second input end of the target amplifying circuit is connected with the memristor feedback array;
The output end of the target amplifying circuit is connected with the memristor feedback array;
The control module is connected with the memristor feedback array and is used for responding to the adjusting instruction, adjusting the resistance state of the memristor in the memristor feedback array according to the adjusting instruction, and enabling the resistance value of the memristor feedback array to reach a target resistance value.
Optionally, the memristor feedback array is provided with a first port, a second port, a first programming interface and a second programming interface; the first port is connected with the output end of the target amplifying circuit; the second port is connected with a second input end of the target amplifying circuit; the first programming interface and the second programming interface are respectively connected with the control module;
The memristor feedback array includes at least one array element including: a first transistor, a second transistor, a third transistor, a fourth transistor, an inverter, and a memristor;
a first end of the first transistor is connected with the first port;
The second end of the first transistor is connected with the positive electrode of the memristor;
A third terminal of the first transistor is connected with a third terminal of the second transistor and with the first programming interface;
The first end of the second transistor is connected with the negative electrode of the memristor;
A second end of the second transistor is connected with the second port;
A first end of the third transistor is connected with a negative electrode of the memristor, and a second end of the third transistor is connected with one end of the inverter;
A third terminal of the third transistor is connected to a third terminal of the fourth transistor and to the second programming interface;
the first end of the fourth transistor is connected with the positive electrode of the memristor, and the second end of the fourth transistor is connected with the inverter and the control module.
Optionally, when the number of array units is at least two; each array unit is connected through the first port, the second port, the first programming interface and the second programming interface.
Optionally, the target amplifying circuit comprises a voltage series negative feedback circuit;
the voltage series negative feedback circuit comprises a first operational amplifier, a first resistor and a first load resistor;
The non-inverting input end of the first operational amplifier is connected with the signal source;
The inverting input end of the first operational amplifier is respectively connected with the second port of the memristor feedback array and one end of the first resistor;
the output end of the first operational amplifier is respectively connected with a first port of the memristor feedback array and one end of the first load resistor;
the other end of the first resistor and the other end of the first load resistor are respectively grounded.
Optionally, the target amplifying circuit comprises a current series negative feedback circuit; the current series negative feedback circuit comprises: a second operational amplifier, a second load resistor;
the non-inverting input end of the second operational amplifier is connected with the signal source;
The inverting input end of the second operational amplifier is connected with the first port of the memristor feedback array; a second port of the memristor feedback array is grounded;
The output end of the second operational amplifier is connected with one end of the second load resistor; the other end of the second load resistor is connected with the first port of the memristor feedback array.
Optionally, the target amplifying circuit comprises a voltage parallel negative feedback circuit; the voltage parallel negative feedback circuit comprises: a third operational amplifier, a third load resistor;
The non-inverting input end of the third operational amplifier is connected with one end of the third load resistor and grounded; the other end of the third load resistor is connected with the output end of the third operational amplifier;
The inverting input end of the third operational amplifier is respectively connected with the second port of the memristor feedback array and the signal source; and a first port of the memristor feedback array is connected with the output end of the third operational amplifier.
Optionally, the target amplifying circuit comprises a current parallel negative feedback circuit; the current parallel negative feedback circuit comprises: a fourth operational amplifier, a fourth load resistor, and a third resistor;
The inverting input end of the fourth operational amplifier is respectively connected with the second port of the memristor feedback array and the signal source; the first port of the memristor feedback array is respectively connected with one end of the third resistor and one end of the fourth load resistor; the other end of the fourth load resistor is connected with the output end of the fourth operational amplifier;
and the non-inverting input end of the fourth operational amplifier is connected with the other end of the third resistor and grounded.
Optionally, the third terminal of the first transistor is a gate, and the third terminal of the second transistor is a gate.
Optionally, the third terminal of the third transistor is a gate, and the third terminal of the fourth transistor is a gate.
Another aspect of the present invention provides a control method of a programmable gain amplifying circuit, the method being applied to the circuit as described above, the control method comprising:
generating a first control signal, a second control signal and a third control signal according to an adjustment instruction in response to the adjustment instruction;
inputting the first control signal into a memristor feedback array to enable the resistance state of the memristor feedback array to obtain a target resistance state; and then, inputting the second control signal into the memristor feedback array to enable the resistance value of the memristor feedback array to reach a target resistance value, and then, inputting the third control signal into the memristor feedback array to enable the memristor feedback array to output the target resistance value.
From the above technical scheme, the invention has the following advantages:
The invention provides a programmable gain amplifying circuit, comprising: the memristor feedback array comprises a target amplifying circuit, a memristor feedback array and a control module; the first input end of the target amplifying circuit is connected with a signal source; the second input end of the target amplifying circuit is connected with the memristor feedback array; the output end of the target amplifying circuit is connected with the memristor feedback array; the control module is connected with the memristor feedback array and is used for responding to the adjusting instruction, adjusting the resistance state of the memristor in the memristor feedback array according to the adjusting instruction, and enabling the resistance value of the memristor feedback array to reach a target resistance value.
In the invention, a first input end of a target amplifying circuit is connected with a signal source and is used for receiving a signal to be processed; the second input end of the target amplifying circuit is connected with the memristor feedback array; the output end of the target amplifying circuit is connected with the memristor feedback array, so that the memristor feedback array forms a negative feedback link of the target amplifying circuit; the control module is connected with the memristor feedback array and is used for responding to the adjusting instruction, adjusting the resistance state of the memristor in the memristor feedback array according to the adjusting instruction, so that the resistance value of the memristor feedback array reaches a target resistance value to flexibly adjust the output resistance value of the memristor feedback array, the amplification factor is flexibly changed, the effect of adjustable gain is achieved, a large amount of resistance resources are not needed, occupation of circuit space resources is reduced, hardware resource consumption of the whole circuit system is reduced, and the problem of high hardware resource consumption of the existing programmable gain amplifying circuit is solved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a schematic diagram of a programmable gain amplifying circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a programmable gain amplifying circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a memristor feedback array provided by an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a voltage series negative feedback amplifying circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a current series negative feedback amplifying circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a voltage parallel negative feedback amplifying circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a current parallel negative feedback amplifying circuit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of simulation results of a voltage series negative feedback circuit according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of simulation results of a current series negative feedback circuit according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of simulation results of a voltage parallel negative feedback circuit according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of simulation results of a current parallel negative feedback circuit according to an embodiment of the present invention;
fig. 12 is a flowchart of a control method of a programmable gain amplifying circuit according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a programmable gain amplifying circuit and a control method, which are used for solving the problem of high hardware resource consumption of the conventional programmable gain amplifying circuit.
In order to make the objects, features and advantages of the present invention more comprehensible, the technical solutions in the embodiments of the present invention are described in detail below with reference to the accompanying drawings, and it is apparent that the embodiments described below are only some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-2, a programmable gain amplifying circuit provided by an embodiment of the present invention includes a target amplifying circuit 1, a memristor feedback array 2, and a control module 3; a first input end of the target amplifying circuit 1 is connected with a signal source 4; the second input end of the target amplifying circuit 1 is connected with the memristor feedback array 2; the output end of the target amplifying circuit 1 is connected with the memristor feedback array 2; the control module 3 is connected with the memristor feedback array 2 and is used for responding to the adjusting instruction, and adjusting the resistance state of the memristors in the memristor feedback array 2 according to the adjusting instruction, so that the resistance value of the memristor feedback array 2 reaches a target resistance value.
The target amplification circuit 1 is a negative feedback amplification circuit including no feedback resistor. The feedback resistor refers to a resistor in the negative feedback amplifying circuit, which is connected with the inverting input end and the output end of the operational amplifier. The signal source 4 is a signal to be amplified. The negative feedback is used for adding and subtracting the feedback quantity and the input quantity, so as to adjust the net input quantity and the output quantity of the circuit.
The memristor feedback array 2 includes memristors and transistors for switching memristor states. Memristors are nonvolatile devices which can adjust the conductivity state by applying external excitation, and can automatically adjust the internal resistance value according to the external excitation, so that the memristors have the property of multiple resistance states. Therefore, in this embodiment, by adjusting the resistance state of the memristor, the memristor can display different resistance values, so that the memristor feedback array 2 can provide richer resistance value selection, flexible adjustment is realized, and the memristor is a nanoscale device, and the structure of the memristor can realize high integration and miniaturization, and occupies smaller circuit space resources.
The working principle of the embodiment is as follows: as shown in fig. 2, the input signal of the target amplifying circuit 1 is referred to as a net input amount, which depends on the input amount provided by the signal source 4 and the feedback amount provided by the memristor feedback array 2; the output signal of the target amplifying circuit 1 is called as output quantity and is used as the input signal of the memristor feedback array 2, the feedback quantity and the input quantity are subjected to the addition and subtraction operation of the target amplifying circuit 1, the net input quantity and the output quantity of the target amplifying circuit 1 can be adjusted, so that the output signal of the target amplifying circuit 1 is amplified, the amplified signal meets the precision requirement of a circuit system, the output resistance value of the memristor feedback array 2 is adjusted, the feedback quantity output by the memristor feedback array 2 can be changed, the net input quantity and the output quantity of the target amplifying circuit 1 are changed, the amplification factor is flexibly changed, and the gain adjustable effect is achieved. Therefore, in this embodiment, the memristor feedback array 2 is programmed to output different resistance values so as to generate different feedback amounts to affect the net input amount of the basic amplifying circuit, so that different feedback coefficients and voltage amplification factors are output, and compared with the existing fixed-gain negative feedback amplifying circuit, the adjusting flexibility is greatly improved.
Wherein, the feedback quantity is taken from the output voltage, so that the output voltage is stable; the feedback is taken from the output current, which will stabilize the output current. If the feedback quantity is taken from the output voltage, the feedback quantity is called voltage feedback; if taken from the output current, it is called current feedback. If the feedback quantity and the input quantity are overlapped in a voltage mode, the feedback quantity and the input quantity are called series feedback; if superimposed in a current fashion, it is called parallel feedback. The negative feedback amplifying circuit has four configurations including voltage series connection, voltage parallel connection, current series connection and current parallel connection.
In this embodiment, a first input end of the target amplifying circuit 1 is connected to the signal source 4, and is configured to receive a signal to be processed; the second input end of the target amplifying circuit 1 is connected with the memristor feedback array 2; the output end of the target amplifying circuit 1 is connected with the memristor feedback array 2, so that the memristor feedback array 2 forms a negative feedback link of the target amplifying circuit 1 and is used for adjusting the gain of the target amplifying circuit 1; the control module 3 is connected with the memristor feedback array 2 and is used for responding to the adjusting instruction, and adjusting the resistance state of the memristors in the memristor feedback array 2 according to the adjusting instruction, so that the resistance value of the memristor feedback array 2 reaches a target resistance value to flexibly adjust the output resistance value of the memristor feedback array 2, thereby realizing the flexible change of the amplification factor, achieving the effect of adjustable gain, avoiding using a large amount of resistance resources, reducing the occupation of circuit space resources and solving the problem of high hardware resource consumption of the existing programmable gain amplifying circuit.
In a specific embodiment, referring to fig. 1-3, the memristor feedback array 2 is provided with a first port 11, a second port 12, a first programming interface OUTRES, a second programming interface PROG; the first port 11 is connected with the output end of the target amplifying circuit 1; the second port 12 is connected with the inverting input terminal of the target amplifying circuit 1; the first programming interface OUTRES and the second programming interface PROG are respectively connected with the control module 3;
The memristor feedback array 2 includes at least one array cell 10, the array cell 10 including: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, an inverter, and a memristor M1;
A first terminal of the first transistor T1 is connected to the first port 11;
the second end of the first transistor T1 is connected with the positive electrode of the memristor M1;
The third terminal of the first transistor T1 is connected to the third terminal of the second transistor T2 and to the first programming interface OUTRES;
The first end of the second transistor T2 is connected with the cathode of the memristor M1;
a second terminal of the second transistor T2 is connected to the second port 12;
a first end of the third transistor T3 is connected with a negative electrode of the memristor M1, and a second end of the third transistor T3 is connected with one end of the inverter;
The third terminal of the third transistor T3 is connected to the third terminal of the fourth transistor T4 and to the second programming interface PROG;
The first end of the fourth transistor T4 is connected to the positive electrode of the memristor M1, and the second end of the fourth transistor T4 is connected to the inverter and to the control module 3.
It should be noted that, as shown in fig. 3, 11 is a first port, 12 is a second port, OUTERS is a first programming interface, and PROG is a second programming interface. The memristor feedback array 2 may be provided with at least one array cell 10, each array cell 10 including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and an inverter.
Taking the leftmost array unit 10 in fig. 3 as an example, the working principle of this embodiment is described as follows:
The first programming interface OUTRES is used for inputting a turn-off signal to turn off the first transistor T1 and the second transistor T2, the second programming interface PROG is used for inputting a turn-on signal to turn on the third transistor T3 and the fourth transistor T4, so that the memristor M1 is IN a resistance programmable state, the control module 3 outputs a resistance switching signal to the joint IN0 of the fourth transistor T4 and the inverter, so that the resistance of the memristor M1 is changed, and after the resistance of the memristor M1 is adjusted to a target resistance, the control module 3 inputs a turn-on signal to the first programming interface OUTRES to turn on the first transistor T1 and the second transistor T2, and inputs a turn-off signal to the second programming interface PROG to turn off the third transistor T3 and the fourth transistor T4, so that the memristor M1 reaching the target resistance is connected with an external target amplifying circuit 1 through the first port 11 and the second port 12, and the amplification factor of the amplifying circuit is flexibly adjusted, and the gain is flexibly adjustable.
The on signal may be a high level signal, and the off signal may be a low level signal.
In a particular embodiment, the type of memristor M1 may be either a digital control type or an analog control type. The memristor M1 may have a high-low binary resistance state, a three-value resistance state, or a multi-value resistance state, where different resistance states represent different resistance values, and the embodiment uses the memristor M1 with a digitally controlled high-low binary resistance state as an example as follows:
When a low resistance value needs to be output, the control module 3 inputs a low level signal to the first programming interface OUTRES, inputs a high level signal to the second programming interface PROG, turns off the first transistor T1 and the second transistor T2, turns on the third transistor T3 and the fourth transistor T4, then inputs a high level signal to a junction of the fourth transistor T4 and the inverter, and makes the memristor M1 in a low resistance state, so that the resistance value of the memristor M1 is low, and then the control module 3 inputs a high level signal to the first programming interface OUTRES, and inputs a low level signal to the second programming interface PROG, so that the memristor feedback array 2 outputs a low resistance value.
When a high resistance value needs to be output, the control module 3 inputs a low level signal to the first programming interface OUTRES and inputs a high level signal to the second programming interface PROG, then, the control module 3 inputs a low level signal to the junction of the fourth transistor T4 and the inverter, so that the memristor M1 is in a high resistance state, and the resistance value of the memristor M1 is high, and then, the control module 3 inputs a high level signal to the first programming interface OUTRES and inputs a low level signal to the second programming interface PROG, and thus, the memristor feedback array 2 outputs a high resistance value.
In a specific embodiment, when the number of array elements 10 is at least two; each array unit 10 is connected through a first port 11, a second port 12, a first programming interface OUTRES, and a second programming interface PROG.
It should be noted that, the number of array units 10 in the memristor feedback array 2 may be plural, and in this embodiment, 4 array units 10 are taken as an example for illustration as follows:
As shown in fig. 3, the first transistor T1 and the second transistor T2 in each array unit 10 are connected to the first port 11 and the second port 12, respectively, so that memristors M1 in four array units 10 are connected in parallel. The third terminals of the first and second transistors T1 and T2 in each array unit 10 are respectively connected to the first programming port, so that the on and off of the first and second transistors T1 and T2 in each array unit 10 can be simultaneously controlled through the first programming port. Third terminals of the third transistor T3 and the fourth transistor T4 in each array unit 10 are connected to the second programming port, respectively, so that the on and off of the third transistor T3 and the fourth transistor T4 can be simultaneously controlled through the second programming port. The connection positions IN0, IN1, IN2 and IN3 of the fourth transistor T4 and the inverter IN each array unit 10 are respectively connected with the control module 3, so that the resistance state of each memristor is switched through the control module 3, the resistance of each memristor output IN parallel IN the memristor feedback array 2 is regulated, and the resistance of the integral output of the memristor feedback array 2 reaches a target resistance. Therefore, the gain-adjustable amplifying circuit in the embodiment can more flexibly adjust the amplifying power of the amplifying circuit and reduce the occupation of circuit space resources.
In one application example, it is assumed that the memristor adopted in the embodiment is in a digitally controlled and high-low binary resistance state, wherein the resistance corresponding to the high resistance state is 10000 Ω, the resistance corresponding to the low configuration is 100 Ω, the positive threshold voltage is 1.5V, and the negative threshold voltage is-1.5V.
When the 4 memristors in the 4 array units 10 are in a low resistance state, the overall output resistance value of the memristor feedback array 2 is 25Ω; when 3 memristors are in a low resistance state and 1 memristor is in a high resistance state in the 4 array units 10, the resistance value output by the whole memristor array is 10000/301 omega approximately 33 omega; when 2 memristors are in a low resistance state and 2 memristors are in a high resistance state in the 4 array units 10, the resistance value of the whole output of the memristor array is 10000/202 omega approximately equal to 49.5; when 3 memristors are in a low resistance state and 1 memristor is in a high resistance state in the 4 array units 10, the resistance value output by the whole memristor array is 10000/103 omega-97 omega; when the 4 memristors in the 4 array units 10 are all in a high resistance state, the overall output resistance value of the memristor feedback array 2 is 10000/4Ω=2500Ω.
The control module 3 may change the number of memristors in a high resistance state and the number of memristors in a low resistance state in the memristor feedback array 2 by changing the high and low levels input to the connection part of the fourth transistor T4 and the inverter in the array unit 10, so as to change the resistance value output by the memristor feedback array 2. For example: the control module 3 can make the memristor feedback array 2 have one memristor IN a high resistance state and three memristors IN a low resistance state by inputting 1000 or 0100 or 0010 or 0001 to the junctions IN0, IN1, IN2, IN3 of the fourth transistor T4 and the inverters IN each array unit 10.
In a specific embodiment, the third terminal of the first transistor T1 is a gate, and the third terminal of the second transistor T2 is a gate.
The gates of the first transistor T1 and the second transistor T2 are connected to each other and to the first programming interface OUTRES.
In a specific embodiment, the third terminal of the third transistor T3 is a gate, and the third terminal of the fourth transistor T4 is a gate.
The gates of the third transistor T3 and the fourth transistor T4 are connected to the second programming interface PROG.
In a specific embodiment, the inverter employs an inverter gate.
The inverter uses an inverter gate in a logic gate circuit.
In a specific embodiment, the target amplifying circuit 1 comprises a voltage series negative feedback circuit;
the voltage series negative feedback circuit comprises a first operational amplifier, a first resistor R1 and a first load resistor RL1;
The non-inverting input end of the first operational amplifier is connected with the signal source 4;
The inverting input end of the first operational amplifier is respectively connected with the second port 12 of the memristor feedback array 2 and one end of the first resistor R1;
The output end of the first operational amplifier is respectively connected with the first port 11 of the memristor feedback array 2 and one end of the first load resistor RL 1;
the other end of the first resistor R1 and the other end of the first load resistor RL1 are grounded.
It should be noted that, the first input terminal of the target amplifying circuit 1 is a non-inverting input terminal of the first operational amplifier; the second input of the target amplifying circuit 1 is the inverting input of the first operational amplifier.
Referring to fig. 4, assuming that the resistance value output by the memristor feedback array 2 is R2, the calculation formula of the feedback coefficient of the voltage series negative feedback circuit is:
Wherein F is a feedback coefficient.
The voltage amplification factor of the voltage series negative feedback circuit is as follows:
Wherein A is voltage amplification factor.
Therefore, the voltage feedback coefficient and the voltage amplification factor of the voltage series negative feedback circuit can be adjusted by changing the resistance value output by the memristor feedback array 2, and the flexible adjustment of the gain is realized.
IN one application example, a voltage series negative feedback circuit simulation model is constructed by taking the memristor feedback array 2of fig. 3 as an example, the input frequency is set to 1000Hz, the amplitude is set to 0.005V, the initial voltage is set to 0V, r1 is set to 5 Ω, RL1 is set to 100 Ω, the low resistance state of the memristor M1 is represented by ON, the high resistance state of the memristor M1 is represented by OFF, a low level signal is input to the first programming interface OUTRES, a high level signal is input to the second programming interface PROG, and the input signals of the junctions IN0, IN1, IN2, IN 3of the fourth transistor T4 and the inverter IN each array unit 10 are set to 1111, 1110, 1100, 1000, so that the states of the memristors IN the memristor feedback array 2 are set to 4ON, 3ON1OFF, 2ON2OFF and 1ON3OFF respectively, and then a high level signal is input to the first programming interface OUTRES, a low level signal is input to the second programming interface PROG, so that the resistances output by the memristor feedback array 2 are set to 25, 33.5, 33.05, and 0.0.0.0.09, and 0.0.7 respectively; and the magnifications obtained according to formula (2) are 6, 7.7, 11.1 and 20, respectively. The simulation result diagram is shown in fig. 8, wherein (a) is a voltage series negative feedback circuit simulation result diagram when the amplification factor is 6, (b) is a voltage series negative feedback circuit simulation result diagram when the amplification factor is 7.7, and (c) is a voltage series negative feedback circuit simulation result diagram when the amplification factor is 11.1 in fig. 8; (d) And a simulation result diagram of the voltage series negative feedback circuit when the amplification factor is 20.
In a specific embodiment, the target amplifying circuit 1 comprises a current series negative feedback circuit; the current series negative feedback circuit comprises: a second operational amplifier, a second load resistor RL2;
The non-inverting input end of the second operational amplifier is connected with the signal source 4;
The inverting input end of the second operational amplifier is connected with the first port 11 of the memristor feedback array 2; the second port 12 of the memristor feedback array 2 is grounded;
the output end of the second operational amplifier is connected with one end of a second load resistor RL 2; the other end of the second load resistor RL2 is connected with the first port 11 of the memristor feedback array 2.
It should be noted that, the first input terminal of the target amplifying circuit 1 is a non-inverting input terminal of the second operational amplifier; the second input of the target amplifying circuit 1 is the inverting input of the second operational amplifier. The first port 11 is the input end 1 of the memristor feedback array 2; the second port 12 is the output 2 of the memristor feedback array.
Referring to fig. 5, assuming that the resistance value output by the memristor feedback array 2 is R, the calculation formulas of the feedback coefficient and the voltage amplification factor of the current series negative feedback circuit are respectively:
F＝R (3)
wherein F is a feedback coefficient, and A is a voltage amplification factor.
From the above, the voltage feedback coefficient and the voltage amplification factor of the current series negative feedback circuit can be adjusted by changing the resistance value output by the memristor feedback array 2, so that the gain is flexibly adjusted.
IN one application example, a current series negative feedback circuit simulation model is constructed by taking the memristor feedback array 2of fig. 3 as an example, the input frequency is set to 1000Hz, the amplitude is set to 0.005V, the initial voltage is set to 0V, the rl2 is set to 100 Ω, the low resistance state of the memristor M1 is represented by ON, the high resistance state of the memristor M1 is represented by OFF, the low level signal is input to the first programming interface OUTRES, the high level signal is input to the second programming interface PROG, the input signals of the junctions IN0, IN1, IN2, IN 3of the fourth transistor T4 and the inverter IN each array unit 10 are set to 1111, 1110, 1100, 1000 respectively, so that the states of the memristor IN the memristor feedback array 2 are set to 4 Ω, 3ON1OFF, 2ON2OFF, and 1ON3OFF respectively, and then the high level signal is input to the first programming interface OUTRES, the low level signal is input to the second programming interface PROG, so that the resistance output by the resistor feedback array 2 is set to 25 Ω, 33.3 Ω, 33.5, 49.5, 97, and 3.97, and 3.33.97, and 25.97 are obtained respectively according to the formulas; and the magnifications obtained according to the formula (4) are 4, 3, 2 and 1, respectively. The simulation result diagram is shown in fig. 9, wherein (a) is a simulation result diagram of the current series negative feedback circuit when the amplification factor is 4, (b) is a simulation result diagram of the current series negative feedback circuit when the amplification factor is 3, and (c) is a simulation result diagram of the current series negative feedback circuit when the amplification factor is 2; (d) And the simulation result diagram is a simulation result diagram of the current series negative feedback circuit simulation result diagram when the amplification factor is 1.
In a specific embodiment, the target amplifying circuit 1 comprises a voltage parallel negative feedback circuit; the voltage parallel negative feedback circuit comprises: a third operational amplifier, a third load resistor RL3;
The non-inverting input end of the third operational amplifier is connected with one end of a third load resistor RL3 and grounded; the other end of the third load resistor RL3 is connected with the output end of the third operational amplifier;
The inverting input end of the third operational amplifier is respectively connected with the second port 12 of the memristor feedback array 2 and the signal source 4; the first port 11 of the memristor feedback array 2 is connected to the output of the first operational amplifier.
The first input terminal and the second input terminal of the target amplifying circuit 1 are both inverting input terminals of the first operational amplifier. The first port 11 is the input end 1 of the memristor feedback array 2; the second port 12 is the output 2 of the memristor feedback array.
Referring to fig. 6, assuming that the resistance value output by the memristor feedback array 2 is R, the calculation formula of the feedback coefficient of the voltage parallel negative feedback circuit is:
Wherein F is a feedback coefficient.
The voltage amplification factor of the voltage parallel negative feedback circuit is as follows:
Wherein A is voltage amplification factor.
From the above, the adjustment of the voltage feedback coefficient and the voltage amplification factor of the voltage parallel negative feedback circuit can be realized by changing the resistance value output by the memristor feedback array 2, and the flexible adjustment of the gain is realized.
IN an application example, a voltage parallel negative feedback circuit simulation model is constructed by taking a memristor feedback array 2of fig. 3 as an example, the input frequency is set to 1000Hz, the amplitude is set to 0.005V, the initial voltage is set to 0V, the internal resistance Rs of the power supply is set to 5 Ω, the low resistance state of the memristor M1 is represented by ON, the high resistance state of the memristor M1 is represented by OFF, a low level signal is input to a first programming interface OUTRES, a high level signal is input to a second programming interface PROG, input signals of junctions IN0, IN1, IN2, IN 3of the fourth transistor T4 and the inverter IN each array unit 10 are set to 1111, 1110, 1100, 1000 respectively, so that the states of the memristors IN the memristor feedback array 2 are set to 4 Ω, 3ON1OFF, 2ON2OFF and 1ON3OFF respectively, then, a high level signal is input to the first programming interface OUTRES, a low level signal is input to the second programming interface PROG, so that the resistances output by the memristor feedback array 2 are set to 25 Ω, 33.3 Ω, 33.5.03-0.03 and 0.01-0.03-0.01 respectively; and the magnifications obtained according to formula (6) were-5, -6.66, -9.9 and-19.4, respectively. The simulation result diagram is shown in fig. 10, wherein (a) is a voltage parallel negative feedback circuit simulation result diagram when the amplification factor is-5, (b) is a voltage parallel negative feedback circuit simulation result diagram when the amplification factor is-6.66, and (c) is a voltage parallel negative feedback circuit simulation result diagram when the amplification factor is-9.9; (d) And when the amplification factor is-19.4, the simulation result diagram of the voltage parallel negative feedback circuit is provided.
In a specific embodiment, the target amplifying circuit 1 comprises a current parallel negative feedback circuit; the current parallel negative feedback circuit comprises: a fourth operational amplifier, a fourth load resistor RL4 and a third resistor R3;
The inverting input end of the fourth operational amplifier is respectively connected with the second port 12 of the memristor feedback array 2 and the signal source 4; the first port 11 of the memristor feedback array 2 is respectively connected with one end of the third resistor R3 and one end of the fourth load resistor RL 4; the other end of the fourth load resistor RL4 is connected with the output end of the fourth operational amplifier;
The non-inverting input terminal of the fourth operational amplifier is connected with the other end of the third resistor R3 and grounded.
The first input terminal and the second input terminal of the target amplifying circuit 1 are both inverting input terminals of the fourth operational amplifier. The first port 11 is the input end 1 of the memristor feedback array 2; the second port 12 is the output 2 of the memristor feedback array.
Referring to fig. 7, assuming that the resistance value output by the memristor feedback array 2 is R2, the calculation formulas of the feedback coefficient and the voltage amplification factor of the current parallel negative feedback circuit are respectively:
Wherein F is a feedback coefficient, A is a voltage amplification factor, and Rs is the internal resistance of the power supply.
From the above, the voltage feedback coefficient and the voltage amplification factor of the current parallel negative feedback circuit can be adjusted by changing the resistance value output by the memristor feedback array 2, so that the gain is flexibly adjusted.
IN one application example, a current parallel negative feedback circuit simulation model is constructed by taking the memristor feedback array 2of fig. 3 as an example, the input frequency is set to 1000Hz, the amplitude is set to 0.005V, the initial voltage is 0V, the internal resistance rs=5Ω, RL 4=5Ω, r3=5Ω, the low resistance state of the memristor M1 is represented by ON, the high resistance state of the memristor M1 is represented by OFF, a low level signal is input to the first programming interface OUTRES, a high level signal is input to the second programming interface PROG, and the input signals of the junctions IN0, IN1, IN2, IN 3of the fourth transistor T4 and the inverter IN each array unit 10 are respectively 1111, 1110, 1100, 1000, so that the states of the memristors IN the memristor feedback array 2 are respectively IN the states of 4ON, 3ON1OFF, 2ON2OFF and 1ON3OFF, and then the high level signal is input to the first programming interface OUTRES, and the low level signal is input to the second programming interface PROG, so that the output of the memristor feedback array 2 is respectively IN the states of 4ON, 3ON 2, 2ON2OFF and 1ON3OFF, and 3, and 0.0.0.0-0.0-7, and 7.0-7, and 7-0.0.0 are respectively, respectively; and the magnifications obtained according to formula (8) are-6, -7.7, -9.9 and-20, respectively. The simulation result diagram is shown in fig. 9, wherein in fig. 9, (a) is a simulation result diagram of the current parallel negative feedback circuit when the amplification factor is-6, (b) is a simulation result diagram of the current parallel negative feedback circuit when the amplification factor is-7.7, and (c) is a simulation result diagram of the current parallel negative feedback circuit when the amplification factor is-9.9; (d) And the simulation result diagram is a simulation result diagram of the current parallel negative feedback circuit simulation result diagram when the amplification factor is-20.
Referring to fig. 12, an embodiment of the present invention provides a control method of a programmable gain amplifying circuit, which is applied to the circuit of the above embodiment, wherein the control method includes:
101. In response to the adjustment instruction, a first control signal, a second control signal, and a third control signal are generated in accordance with the adjustment instruction.
It should be noted that, the adjusting instruction includes a target resistance value to be adjusted, and the control module generates a corresponding first control signal, a second control signal and a third control signal according to the adjusting instruction.
102. Inputting a first control signal into the memristor feedback array to enable the resistance state of the memristor feedback array to obtain a target resistance state; and then, inputting a second control signal into the memristor feedback array to enable the resistance value of the memristor feedback array to reach a target resistance value, and then, inputting a third control signal into the memristor feedback array to enable the memristor feedback array to output the target resistance value.
It should be noted that the first control signal is used to turn off a transistor in the memristor feedback array connected to the first programming interface, and is used to turn on a transistor in the memristor feedback array connected to the second programming interface. The second control signal is used for adjusting the resistance value of each memristor in the memristor feedback array, so that the resistance value output by the memristor feedback array is consistent with the target resistance value. The third control signal is used to turn on a transistor in the memristor feedback array that is connected to the first programming interface and to turn off a transistor in the memristor feedback array that is connected to the second programming interface.
According to the control method of the programmable gain amplifying circuit, provided by the embodiment, the first control signal, the second control signal and the third control signal are generated according to the adjusting instruction by responding to the adjusting instruction, and the first control signal is input into the memristor feedback array, so that the resistance state of the memristor feedback array is enabled to obtain a target resistance state; and then, inputting a second control signal into the memristor feedback array to enable the resistance value of the memristor feedback array to reach a target resistance value, and inputting a third control signal into the memristor feedback array to enable the memristor feedback array to output the target resistance value, so that the gain of the programmable gain amplifying circuit is flexibly adjusted.
From the foregoing, the embodiment of the invention provides a programmable gain amplifying circuit and a control method, which can reduce hardware equipment, and can adjust the amplification factor of the programmable gain amplifying circuit according to the requirement through programming, so that the full-scale signal of an a/D converter is more uniform, the measurement accuracy is greatly improved, the 'automatic switching of the range' is realized, and the specific requirements of subsequent circuits and systems are further met.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
The terms "first," "second," "third," "fourth," and the like in the description of the application and in the above figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be further noted that, in the description of the present invention, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are based on directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific direction, be configured and operated in the specific direction, and thus should not be construed as limiting the present invention.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A programmable gain amplification circuit, comprising: the memristor feedback array comprises a target amplifying circuit, a memristor feedback array and a control module;
the first input end of the target amplifying circuit is connected with a signal source;
The second input end of the target amplifying circuit is connected with the memristor feedback array;
The output end of the target amplifying circuit is connected with the memristor feedback array;
The control module is connected with the memristor feedback array and is used for responding to the adjusting instruction, adjusting the resistance state of the memristor in the memristor feedback array according to the adjusting instruction, and enabling the resistance value of the memristor feedback array to reach a target resistance value.
2. The circuit of claim 1, wherein the memristor feedback array is provided with a first port, a second port, a first programming interface, and a second programming interface; the first port is connected with the output end of the target amplifying circuit; the second port is connected with a second input end of the target amplifying circuit; the first programming interface and the second programming interface are respectively connected with the control module;
The memristor feedback array includes at least one array element including: a first transistor, a second transistor, a third transistor, a fourth transistor, an inverter, and a memristor;
a first end of the first transistor is connected with the first port;
The second end of the first transistor is connected with the positive electrode of the memristor;
A third terminal of the first transistor is connected with a third terminal of the second transistor and with the first programming interface;
The first end of the second transistor is connected with the negative electrode of the memristor;
A second end of the second transistor is connected with the second port;
A first end of the third transistor is connected with a negative electrode of the memristor, and a second end of the third transistor is connected with one end of the inverter;
A third terminal of the third transistor is connected to a third terminal of the fourth transistor and to the second programming interface;
the first end of the fourth transistor is connected with the positive electrode of the memristor, and the second end of the fourth transistor is connected with the inverter and the control module.
3. The circuit of claim 2, wherein when the number of array units is at least two, each of the array units is connected through the first port, the second port, the first programming interface, the second programming interface.
4. A circuit according to claim 3, wherein the target amplification circuit comprises a voltage series negative feedback circuit;
the voltage series negative feedback circuit comprises a first operational amplifier, a first resistor and a first load resistor;
The non-inverting input end of the first operational amplifier is connected with the signal source;
The inverting input end of the first operational amplifier is respectively connected with the second port of the memristor feedback array and one end of the first resistor;
the output end of the first operational amplifier is respectively connected with a first port of the memristor feedback array and one end of the first load resistor;
the other end of the first resistor and the other end of the first load resistor are respectively grounded.
5. A circuit according to claim 3, wherein the target amplification circuit comprises a current series negative feedback circuit; the current series negative feedback circuit comprises: a second operational amplifier, a second load resistor;
the non-inverting input end of the second operational amplifier is connected with the signal source;
The inverting input end of the second operational amplifier is connected with the first port of the memristor feedback array; a second port of the memristor feedback array is grounded;
The output end of the second operational amplifier is connected with one end of the second load resistor; the other end of the second load resistor is connected with the first port of the memristor feedback array.
6. The circuit of claim 3, wherein the target amplification circuit comprises a voltage parallel negative feedback circuit; the voltage parallel negative feedback circuit comprises: a third operational amplifier, a third load resistor;
The non-inverting input end of the third operational amplifier is connected with one end of the third load resistor and grounded; the other end of the third load resistor is connected with the output end of the third operational amplifier;
The inverting input end of the third operational amplifier is respectively connected with the second port of the memristor feedback array and the signal source; and a first port of the memristor feedback array is connected with the output end of the third operational amplifier.
7. A circuit according to claim 3, wherein the target amplification circuit comprises a current parallel negative feedback circuit; the current parallel negative feedback circuit comprises: a fourth operational amplifier, a fourth load resistor, and a third resistor;
The inverting input end of the fourth operational amplifier is respectively connected with the second port of the memristor feedback array and the signal source; the first port of the memristor feedback array is respectively connected with one end of the third resistor and one end of the fourth load resistor; the other end of the fourth load resistor is connected with the output end of the fourth operational amplifier;
and the non-inverting input end of the fourth operational amplifier is connected with the other end of the third resistor and grounded.
8. The circuit of claim 2, wherein the third terminal of the first transistor is a gate and the third terminal of the second transistor is a gate.
9. The circuit of claim 2, wherein the third terminal of the third transistor is a gate and the third terminal of the fourth transistor is a gate.
10. A control method of a programmable gain amplifying circuit, characterized in that the method is applied to the circuit according to any one of claims 1 to 9, the control method comprising:
generating a first control signal, a second control signal and a third control signal according to an adjustment instruction in response to the adjustment instruction;
inputting the first control signal into a memristor feedback array to enable the resistance state of the memristor feedback array to obtain a target resistance state; and then, inputting the second control signal into the memristor feedback array to enable the resistance value of the memristor feedback array to reach a target resistance value, and then, inputting the third control signal into the memristor feedback array to enable the memristor feedback array to output the target resistance value.
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