CN118074501A

CN118074501A - Soft start circuit of power converter and power converter

Info

Publication number: CN118074501A
Application number: CN202410033483.9A
Authority: CN
Inventors: 顾阳; 詹丹; 吴皓楠
Original assignee: Junying Semiconductor Shanghai Co ltd
Current assignee: Junying Semiconductor Shanghai Co ltd
Priority date: 2024-01-09
Filing date: 2024-01-09
Publication date: 2024-05-24

Abstract

The invention discloses a soft start circuit for a power converter and the power converter. The soft start circuit includes: the internal soft start module is used for generating rising internal soft start voltage; the external soft start module is connected with the external soft start terminal and is used for generating external soft start voltage; and a voltage switching module for comparing the internal soft start voltage with the external soft start voltage and switching the soft start voltage signal according to the smaller one of the two, wherein the external soft start terminal is used for connecting an external capacitor or a voltage source for providing an external reference voltage so as to allow the external capacitor or the external reference voltage to at least partially control the rising time of the soft start voltage signal during circuit start, thereby providing soft start voltage signals with different rising slopes during circuit start, and adopting the internal reference voltage, the external capacitor or the external reference voltage to set different soft start times according to different application scenes.

Description

Soft start circuit of power converter and power converter

Technical Field

The present invention relates to the field of power management, and in particular, to a soft start circuit for a power converter and a power converter.

Background

With the development of power electronics and semiconductor technology, power management chips are widely used in the fields of communication, consumption, computing, and the like. DC-DC converters, which are among the most common ones in power management chips, typically comprise one or more switches that are selectively actuated to provide a controlled DC output voltage or current based on a received DC input, the output power of the circuit being regulated by controlling the pulse width or the time of the signal provided to the one or more switches of the converter according to an error signal. There are a large number of capacitors in the DC-DC converter circuit, which are typically connected in parallel with the driven load at the output of the converter, stabilizing the converter output voltage and providing a source for the load current. However, at circuit power-up, the output capacitor is first discharged, and at this time the difference between the output voltage and the desired value is large, resulting in the pulse width modulation control providing a large current value output, resulting in a large inrush current of the output capacitor during start-up, which may damage the output capacitor, affecting the stability of the circuit. Therefore, a soft start technique is required to control the start-up process of the DC-DC converter, thereby limiting the inrush current supplied to the output capacitor during start-up.

Fig. 1 shows a schematic circuit diagram of a power converter according to the prior art. The DC-DC converter 100 includes a power circuit including a power switch Mx and a diode D1 connected in series between an input terminal and a ground terminal, an inductor Lx connected between an intermediate node of the power switch Mx and the diode D1 and an output terminal, and an output capacitor Cout connected between the output terminal and the ground terminal. The input terminal of the DC-DC converter 100 receives an input voltage Vin and the output terminal provides an output voltage Vout. The control circuit of the DC-DC converter 100 is used to provide a switching control signal to the power switch Mx.

In the control circuit of the DC-DC converter 100, the feedback circuit 130 generates a feedback voltage FB according to the output voltage Vout, the error amplifier EA generates an error amplified signal Vea according to the feedback voltage FB and a soft start voltage signal Vss provided by the soft start circuit 140, and the PWM comparator 120 generates a pulse width modulation signal PWM according to the error amplified signal Vea and the ripple signal Vramp to control the on state of the power switch Mx.

A typical soft start circuit may employ the structure of fig. 2, and fig. 3 shows a waveform schematic diagram of a conventional soft start circuit. As shown in fig. 2, the soft start circuit 140 includes a current source Iss, a capacitor Css, an NMOS transistor M1, and resistors R1 and R2. The current source Iss and the capacitor Css are connected in series between the power supply voltage VDD and the ground, the NMOS transistor M1, the resistor R1 and the resistor R2 are connected in series between the bandgap reference voltage VBG inside the DC-DC converter and the ground, the gate of the NMOS transistor M1 and one end of the capacitor Css are connected to the point a, the resistors R1 and R2 are sequentially connected between the source of the NMOS transistor M1 and the ground, and the point E between the resistors R1 and R2 is the reference potential output end of the error amplifier EA.

In the conventional soft start circuit 140, the capacitor Css is charged by the current source Iss, a linearly rising voltage Va is generated at one end of the capacitor Css, and when the voltage Va is higher than the threshold voltage of the NMOS transistor M1, the NMOS transistor M1 is turned on, the soft start voltage signal Vss slowly rises, and finally, the voltage rises to a fixed voltage value obtained by dividing the band gap reference voltage VBG by a resistor.

However, existing soft start circuits typically only provide a fixed or predetermined soft start time during which the output current of the circuit is limited and the desired soft start timing specification is different for different applications. For example, the maximum tolerated level of the inrush current may be determined by the particular output capacitor used by the circuit. Thus, there is a need for improvements to existing soft start circuits so that they can set different soft start times by one or more external components.

Disclosure of Invention

In view of the above, it is an object of the present invention to provide a soft start circuit for a power converter and a power converter, providing a combination of internal soft start control, external soft start control and voltage tracking functionality, allowing a user to set different soft start times according to different applications.

According to an aspect of the present invention, there is provided a soft start circuit for a power converter for providing a rising soft start voltage signal during start-up of the circuit, the power converter further comprising an error amplifier for obtaining a difference between a feedback signal and the soft start voltage signal, wherein the soft start circuit comprises: the internal soft start module is used for generating rising internal soft start voltage; the external soft start module is connected with the external soft start terminal and is used for generating external soft start voltage; and a voltage switching module for comparing the internal soft start voltage with the external soft start voltage and switching the soft start voltage signal according to the smaller of the two, wherein the external soft start terminal is used for connecting an external capacitor or a voltage source for providing an external reference voltage so as to allow the external capacitor or the external reference voltage to at least partially control the rising time of the soft start voltage signal during circuit start-up.

Optionally, the internal soft start voltage has a fixed first rising slope and the external soft start voltage has at least a second rising slope associated with the external capacitor.

Optionally, the soft start circuit further includes: and the external soft start module is used for comparing the external soft start voltage with a first reference voltage to generate a tracking indication signal and controlling the output of the external soft start module according to the tracking indication signal, wherein when the tracking indication signal is valid, the external soft start module generates the external soft start voltage equal to the external reference voltage, and when the tracking indication signal is invalid, the external soft start module generates the rising external soft start voltage.

Optionally, the soft start circuit further includes: and the pin short circuit detection module is used for comparing the external soft start voltage with a second reference voltage so as to generate a short circuit indication signal and controlling the opening and closing of the internal soft start module and the voltage switching module according to the short circuit indication signal, wherein the second reference voltage is smaller than the first reference voltage.

Optionally, the external soft start module includes: a first current source, a first transistor, and a second current source connected in series between a power supply voltage and ground, an intermediate node of the first transistor and the second current source for outputting the external soft start voltage; the inverting input end of the operational amplifier is connected with the first reference voltage, the non-inverting input end of the operational amplifier is connected with the output node of the external soft start voltage and the external soft start terminal, the enabling end of the operational amplifier is connected with the tracking indication signal, and the output end of the operational amplifier is connected with the control end of the first transistor; and a second transistor connected between an output node of the external soft start voltage and ground, a control terminal of the second transistor being connected with an inverted signal of the first enable signal.

Optionally, the internal soft start module includes: a third current source and a first capacitor connected in series between a power supply voltage and ground, and an intermediate node of the third current source and the first capacitor is used for outputting the internal soft start voltage; and a third transistor connected between an output node of the internal soft start voltage and ground, a control terminal of the third transistor being connected to the short circuit indication signal.

Optionally, the external tracking voltage detection module includes: the non-inverting input end of the first comparator is connected with the external soft start voltage, the inverting input end of the first comparator is connected with the first reference voltage, and the enabling end of the first comparator is connected with a first enabling signal; the data end of the D trigger is connected with the output end of the first comparator, the clock end of the D trigger is connected with the second enabling signal, and the reset end of the D trigger is connected with the first enabling signal; the input end of the first inverter is connected with the output end of the D trigger; and a first and circuit, wherein a first input end of the first and circuit is connected with an output end of the first inverter, a second input end of the first and circuit is connected with the second enabling signal, and an output end of the first and circuit is used for generating the tracking indication signal, wherein an effective edge of the second enabling signal lags behind an effective edge of the first enabling signal.

Optionally, the pin short circuit detection module includes: the non-inverting input end of the second comparator is connected with the external soft start voltage, the inverting input end of the second comparator is connected with the second reference voltage, and the enabling end of the second comparator is connected with a first enabling signal; the first input end of the second AND gate circuit is connected with the output end of the second comparator, and the second input end of the second AND gate circuit is connected with a second enabling signal; and the input end of the second inverter is connected with the output end of the second AND gate circuit, and the output end of the second inverter is used for generating the short circuit indication signal.

Optionally, the voltage switching module includes: a third comparator for comparing the internal soft start voltage with the external soft start voltage to generate a transmission gate switching signal; the input end of the transmission gate is connected with the internal soft start voltage and the external soft start voltage, the control end of the transmission gate is connected with the switch signal of the transmission gate, and the output end of the transmission gate is connected with the output end of the soft start voltage signal; a second capacitor connected between an output terminal of the soft start voltage signal and ground; and a fourth transistor connected between the output end of the soft start voltage signal and the ground, wherein the control end of the fourth transistor is connected with the short circuit indication signal.

According to another aspect of the present invention, there is provided a power converter, including the soft start circuit.

In summary, the soft start circuit provided by the present invention can provide soft start voltage signals with different rising slopes during the circuit start, and set different soft start times by using an internal reference voltage, an external capacitor or an external reference voltage according to different application scenarios, so as to adaptively reduce the surge current at the output capacitor during the circuit start. In addition, the soft start circuit also has the output voltage tracking (output voltage traking, TRK for short) function, so that the reference level of the output voltage can be adjusted by adjusting an external voltage source at an external soft start terminal, the output voltage does not need to be adjusted through a resistor voltage division network, the design of a power management circuit is simplified, the efficiency of the circuit can be improved, and the performance and the reliability of a system can be improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Fig. 1 shows a schematic circuit diagram of a power converter according to the prior art.

Fig. 2 shows a circuit schematic of a soft start circuit according to the prior art.

Fig. 3 shows a waveform schematic diagram of a prior art soft start circuit.

Fig. 4 shows a circuit schematic of a power converter control circuit with soft start circuitry according to an embodiment of the invention.

Fig. 5 shows a circuit schematic of a soft start circuit according to an embodiment of the invention.

Fig. 6a shows a circuit schematic of an external soft start module according to an embodiment of the invention.

Fig. 6b shows a waveform schematic of an external soft start signal according to an embodiment of the invention.

Fig. 7a shows a circuit schematic of an internal soft start module according to an embodiment of the invention.

Fig. 7b shows a waveform schematic of an internal soft start signal according to an embodiment of the invention.

Fig. 8 shows a circuit schematic of an external tracking voltage detection module according to an embodiment of the invention.

Fig. 9 shows a circuit schematic of a pin short detection module according to an embodiment of the invention.

Fig. 10 shows a circuit schematic of a voltage switching module according to an embodiment of the invention.

FIG. 11 shows a timing diagram of a soft start circuit during an internal soft start according to an embodiment of the present invention.

Fig. 12 shows a timing diagram of a soft start circuit during an external soft start according to an embodiment of the invention.

FIG. 13 shows a timing diagram of a soft start circuit during tracking voltage according to an embodiment of the invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.

Numerous specific details of the invention, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

The embodiment of the invention firstly provides a power converter control circuit with a soft start circuit, which is used for PWM control of a DC-DC converter. Various exemplary examples are illustrated and described below in connection with a Buck-converter type system, but the invention is not limited in this regard and the various concepts disclosed herein may be used in connection with any type of DC-DC converter architecture, including Buck-type (Buck) converters, boost-type (Boost) converters, flyback-type (Flyback-Boost) converters, and the like, depending on the topology classification of the power circuit, for example. Furthermore, while complementary PWM control of the high-side switching device and the low-side switching device is utilized in the illustration of the embodiments of the present invention, the concepts described herein can be implemented in power converters that use only a single switching device and/or in power converters that employ more than two pulse width modulations.

Fig. 4 illustrates a circuit schematic of a power converter control circuit 200, which may be implemented as an integrated circuit having various terminals or pins, for interconnection with other components of a DC-DC converter system, as shown, in accordance with an embodiment of the present invention. Furthermore, in the example of fig. 4, integrated circuit 200 includes power conversion devices S1 and S2, and corresponding high-side driver 224 and low-side driver 226, but in other possible examples, one or all of these components may be external to integrated circuit 200. Similarly, the control circuit 200 in fig. 4 also provides terminals 206, 208, and 210 to connect to the output inductor L1, the output capacitor C3, the bootstrap capacitor C2, and the feedback circuits R2, R3, and C1 of the external buck converter, although other examples are possible, and one or more of these components may be provided in the integrated circuit 200.

The system shown in fig. 4 implements a peak current mode buck converter operated by the integrated circuit 200, wherein the control circuit 200 provides the output voltage VOUT to the load 207 in parallel with the output capacitor C3, based on the advantages of soft start control and closed loop feedback control of the output voltage VOUT. Furthermore, in this embodiment, the control circuit 200 regulates the output voltage VOUT in accordance with the soft start voltage signal Vss, but other embodiments are possible, wherein the control circuit 200 may provide an external pin or terminal (not shown) for regulating the output in accordance with an externally supplied set point signal. By connection of the DC voltage VIN to the power input terminal 202, power is input to the control circuit 200, and the control circuit 200 further includes a power ground connection terminal 212 to be connected to a circuit ground. In addition, the control circuit 200 may further include an enable input terminal (not shown) for receiving an enable signal, allowing the operation of the control circuit 200 and the DC-DC converter to be selectively enabled or disabled. Illustratively, the control circuit 200 activates the internal reference voltage generator circuit 218, which IN turn provides an internal reference voltage ss_in for regulating the output of the DC-DC converter, IN accordance with an enable signal received at an enable input terminal. The input voltage VIN from pin 202 is also connected to a Low Drop Out (LDO) regulator circuit 220 that provides an output to power switch drivers 224 and 226, with the high-side driver 224 connected to the output of the regulator circuit 220 via diode D2 for bootstrap operation.

The high-side output switch S1 and the low-side output switch S2 are connected in series with each other between the input voltage terminal 202 and the power ground terminal 212. The output switches S1 and S2 are NMOS transistors with corresponding diodes D1 and D2 connected as shown in fig. 4, but the invention is not limited thereto, other embodiments are possible in which different types of switches are used, and/or the switches S1 and S2 may be integrated outside the control circuit 200. The pulse width modulated gate control signals are provided to switches S1 and S2 by corresponding high side driver 224 and low side driver 226, respectively, wherein drivers 224 and 226 receive the high side driver signal and the low side driver signal from corresponding outputs HSDR and LSDR, respectively, of controller 222. An inductor output terminal 206 (LX) is used for connection of the external inductor L1 between the control circuit 200 and the load 207, wherein the output terminal 206 is connected to a common connection of the high side output switch S1 and the low side output switch S2 as shown.

The control circuit 200 also provides a bootstrap terminal 210 (BST) for connection of the bootstrap capacitor C2 between the output terminal 206 (LX) and the upper supply rail used by the high side driver 224. In this embodiment, the high-side switch S1 is an NMOS device, and therefore, the gate voltage of the high-side switch S1 needs to be higher than the output voltage at the LX terminal to be turned on. In operation, when the low-side switch S2 is turned on, the lower terminal of the bootstrap capacitor C2 is grounded, and the upper terminal of the bootstrap capacitor C2 is connected to the output voltage of the LDO regulator 220 through the diode D3, such that the bootstrap capacitor C2 is charged up to the regulated voltage output (minus the diode drop of the diode D3). When the high-side switch S1 is then turned on and the low-side switch S2 is turned off, the voltage at LX terminal 106 (at the lower terminal of bootstrap capacitor C2) is connected to the input voltage VIN, while the voltage at BST terminal 210 will be a voltage exceeding the input voltage VIN, the high-side driver 224 is thus connected to this higher voltage, enabling to provide a sufficient gate signal to the high-side switch S1 with sufficient voltage to turn on the high-side switch S1.

As further shown in fig. 4, the control circuit 200 includes a pulse generation circuit including an error amplifier 240, a peak current detection circuit 231, an off-time control circuit 228, a PWM modulation circuit 236, a soft start circuit 242, and an external soft start terminal (SS) 204. Error amplifier 240 includes a non-inverting input that receives soft-start voltage signal Vss and an inverting input that receives feedback signal FB, which is representative of the output condition of the DC-DC converter (as in this example, output voltage VOUT). Error amplifier 240 has an output terminal providing an error amplifier output signal 241, signal 241 representing the difference between feedback signal FB and soft-start voltage signal Vss. In operation, error amplifier 240 amplifies a difference between feedback signal FB applied at an inverting input and soft-start voltage signal Vss applied at a non-inverting input to generate error amplifier output signal 241. Further, the output signal 241 is optionally connected to a loop compensation circuit (not shown in the figure) and provided as an input to the peak current detection circuit 231. The peak current detection circuit 231 is configured to convert the error amplifier output signal 241 into a corresponding current value, the current value is used to characterize the peak value of the inductor current, and compare the current value with a set peak current, and when the current value reaches the set peak current, the peak current detection circuit 231 provides the turn-off signal 235 for turning off the high-side switch S1 to the PWM modulation circuit 236. The off-time control circuit 228 is configured to start timing when the high-side switch S1 is turned off, and to provide the PWM modulation circuit 236 with the on signal 235 for turning on the high-side switch S1 when the off-time of the high-side switch S1 reaches a time threshold value, which may be determined according to an input voltage and an output voltage of the DC-DC converter, for example. The PWM modulation circuit 236 has a first input terminal receiving the off signal 235 and a second input terminal receiving the on signal 232 from the off-time control circuit 228, and an output terminal providing a pulse width modulated output signal 236a in accordance with the off signal 235 and the on signal 232. In operation, PWM output signal 236a is low when off signal 235 is on and PWM output signal 236a is high when on signal 232 is on. Finally, a pulse stream is provided in the output signal 236a, wherein the pulse width (the percentage of time that the signal 236a is high) will be substantially proportional to the level of the error amplifier output signal 241.

Furthermore, in steady state operation of the DC-DC converter system, the level of the error amplifier output signal 241 will represent an error indicating the difference between the feedback signal FB and the soft start voltage signal Vss. In the embodiment shown in fig. 4, the resistive divider circuit is provided by external resistors R2 and R3 and a stabilizing or filtering capacitor C1, providing a feedback signal FB to the inverting input of error amplifier 240 via terminal 208 through the connection of R2 and C1 to the output voltage at load 207 (as indicated by the dashed line in fig. 4). The controller 222 receives the PWM control signal 236a from the PWM modulation circuit 236 and generates complementary high-side driver signal HSDR and low-side driver signal LSDR, which are provided as inputs to the high-side driver 224 and the low-side driver 226, respectively. This closed loop configuration allows the pulse width in the output signal 236a to be adjusted to drive the output voltage VOUT at the load 207 such that the output voltage VOUT corresponds to the reference level represented by the soft-start voltage signal Vss.

However, during system start-up, the output capacitor C3 in fig. 4 starts in a discharged state, and thus, a closed loop operation strictly in accordance with the feedback signal FB may result in an excessive inrush current level at the capacitor C3. Thus, control circuit 200 also includes soft-start circuit 242, soft-start circuit 242 being configured to apply a substantially rising voltage on soft-start voltage signal Vss during circuit start-up (i.e., when unregulated input voltage VIN is applied to pin 202), and the rate of change of soft-start voltage signal Vss will be a fixed rate. The soft start circuit 242 is further connected to the internal reference voltage generator circuit 218 to control the rising time of the soft start voltage signal Vss according to the internal reference voltage Vref generated by the internal reference voltage generator circuit 218 during the start-up of the control circuit 200. In addition, the soft start circuit 242 is also used in connection with the external soft start terminal 204, the external soft start segment 204 being allowed to connect with a current source or external capacitor Cext that generates an external reference voltage VTRK to allow the circuit to control the rise time of the soft start voltage signal Vss in accordance with the external reference voltage VTRK or external capacitor Cext during start-up of the control circuit 200.

When an external reference voltage VTRK is applied at the external soft-start terminal 204, the soft-start circuit 242 is configured to control the rise time of the soft-start voltage signal Vss in accordance with the external reference voltage VTRK. When an external capacitor Cext is connected at the external soft-start terminal 204, the soft-start circuit 242 is configured to control the rise time of the soft-start voltage signal Vss in accordance with the external capacitor Cext to provide a longer soft-start time for the circuit. When the external reference voltage VTRK is not applied at the external soft-start terminal 204 and the external capacitor Cext is not connected (or the capacitance of the external capacitor Cext is small), the soft-start circuit 242 is configured to control the rising time of the soft-start voltage signal Vss according to the internal reference voltage Vref.

Thus, the soft start circuit 242 of the present invention may not only use a combination of internal soft start control functions and external soft start control functions, allowing a user to apply the internal soft start functions and associated fixed soft start times or connect one or more external components to the control circuit 200 to set different (e.g., longer) soft start times to further limit the inrush current of the output capacitor, but also have an output voltage tracking (output voltage traking, TRK) function such that the reference level of the output voltage VOUT may be adjusted by adjusting the external voltage source at the external soft start terminal 204, without adjusting the output voltage VOUT through a resistive voltage divider network, simplifying the design of the power management circuit, and may improve the efficiency of the circuit, thereby improving the performance and reliability of the system.

With further reference to fig. 5, fig. 5 schematically illustrates a circuit schematic of a soft start circuit 242 in accordance with an embodiment of the present invention. As shown in fig. 5, the soft start circuit 242 includes an external soft start module 401, an external soft start module 402, an external tracking voltage detection module 403, a pin short detection module 404, and a voltage switching module 405.

Wherein the external soft start module 401 is connected to the external soft start terminal 204 for generating an external soft start voltage vss_ext during circuit start-up from an external reference voltage VTRK applied on the external soft start terminal 204 or a connected external capacitor Cext. Specifically, when the external reference voltage VTRK is applied to the external soft start terminal 204, the external reference voltage VTRK needs to be higher than the first reference voltage Vref1, and the external soft start module 401 outputs the external soft start voltage vss_ext equal to the external reference voltage VTRK. When no external reference voltage VTRK is applied across the external soft-start terminal 204, the external soft-start module 401 is configured to generate a rising external soft-start voltage vss_ext having a first slope by charging the external capacitor Cext.

The internal soft start module 402 is configured to generate a rising internal soft start voltage vss_int having a fixed second slope during circuit start-up.

The external tracking voltage detection module 403 is configured to compare the external soft start voltage generated by the external soft start module 402 with the first reference voltage Vref1, and generate a tracking indication signal trk_n according to the comparison result, where the tracking indication signal trk_n is used to control the working state of the external soft start module 401. For example, when the external soft start voltage is greater than the first reference voltage Vref1, the external tracking voltage detection module 403 generates a tracking indication signal trk_n that is valid (e.g., low level) indicating that the circuit has enabled the voltage tracking function, at which time the external soft start voltage vss_ext output by the external soft start module 401 is equal to the external reference voltage VTRK. When the external soft start voltage vss_ext is smaller than the first reference voltage Vref1, the external tracking voltage detection module 403 generates an inactive (e.g., high level) tracking indication signal trk_n indicating that the circuit has not enabled the voltage tracking function, at which time the external soft start voltage vss_ext output by the external soft start module 401 linearly rises.

The voltage switching module 405 is used to compare the internal soft start voltage vss_int and the external soft start voltage vss_ext during circuit start-up and switch the smaller of the two to the signal at the non-inverting input of the error amplifier 240. For example, when the internal soft start voltage vss_int is smaller than the external soft start voltage vss_ext, the voltage conversion module 405 outputs the internal soft start voltage vss_int to the non-inverting input terminal of the error amplifier 240, and at this time, the soft start voltage signal Vss at the non-inverting input terminal of the error amplifier 240 linearly rises with a second slope; when the internal soft start voltage vss_int is greater than the external soft start voltage vss_ext, the voltage switching module 405 outputs the external soft start voltage vss_ext to the non-inverting input terminal of the error amplifier 240, and at this time, the soft start voltage signal Vss at the non-inverting input terminal of the error amplifier 240 linearly rises with a first slope or is equal to the external reference voltage VTRK.

The pin short circuit detection module 404 is configured to compare the external soft start voltage vss_ext generated by the external soft start module 402 with a second reference voltage Vref2 smaller than the first reference voltage Vref1, and generate a short circuit indication signal ss_short according to the comparison result, where the short circuit indication signal ss_short is used to control the working states of the internal soft start module 402 and the voltage switching module 405. For example, when the external soft start voltage vss_ext is less than the second reference voltage Vref2, the pin short detection module 404 determines that a short event occurs at the external soft start terminal 204 and outputs a valid (e.g., high level) short indication signal ss_short to turn off the internal soft start module 402 and the voltage switching module 405; when the external soft start voltage is greater than the second reference voltage Vref2, the pin short detection module 404 outputs an invalid (e.g., low level) short indication signal ss_short to control the internal soft start module 402 and the voltage switching module 405 to operate normally.

Therefore, soft start voltage signals with different rising slopes can be provided during circuit starting, and different soft start times are set by adopting the internal reference voltage Vref, the external capacitor Cext or the external reference voltage VTRK according to different application scenes so as to adaptively reduce surge current at the output capacitor during circuit starting. In addition, the soft start circuit 242 of the present invention can also set the reference level of the output voltage VOUT according to the external reference voltage VTRK after the circuit is started, so that different output voltages VOUT can be set conveniently.

Fig. 6a and 6b show a schematic circuit diagram and a schematic waveform diagram, respectively, of an external soft start module 401 according to an embodiment of the present invention.

Referring to fig. 6a, the external soft start module 401 of the present embodiment includes current sources 411 and 412, a PMOS transistor M1, an NMOS transistor M2, and an operational amplifier OP1. The current source 411, the PMOS transistor M1 and the current source 412 are connected in series between the power supply voltage VDD and the ground, the source of the PMOS transistor M1 is connected to the current source 411, the drain of the PMOS transistor M1 is connected to the current source 412, and the intermediate node of the PMOS transistor M1 and the current source 412 is used for outputting the external soft start voltage vss_ext. The operational amplifier OP1 has an inverting input terminal receiving the first reference voltage Vref1, a non-inverting input terminal connected to the intermediate node of the PMOS transistor and the current source 412 and the external soft start terminal 204, an enable terminal for receiving the tracking indication signal trk_n, and an output terminal connected to the gate of the PMOS transistor M1. The drain of the NMOS transistor M2 is connected to the output node of the external soft start voltage vss_ext, the gate of the NMOS transistor M2 is connected to the inverted signal en1_n of the first enable signal EN1, and the source of the NMOS transistor M2 is connected to ground. The NMOS transistor M2 is configured to maintain a conductive state before the first enable signal EN1 turns to a high level, so as to discharge and initialize the capacitor on the external soft start terminal 204 to a zero potential, prevent the residual voltage on the capacitor from misjudging the external tracking voltage detection module 403, and ensure that the external soft start voltage vss_ext can rise from the zero potential, and ensure that the working state of the circuit is correct through initialization setting.

The enable terminal of the operational amplifier OP1 of the present embodiment is configured to be active high, so when the tracking indication signal trk_n is active (e.g., low), the operational amplifier OP1 is turned off, and the external soft start voltage vss_ext is equal to the external reference voltage VTRK; when the tracking indication signal trk_n is inactive (e.g., high level), the operational amplifier OP1 is enabled, a negative feedback loop formed by the operational amplifier OP1 and the PMOS transistor M1 starts to be established, the external capacitor Cext is charged, the charging current is equal to the difference of the output currents of the current sources 411 and 412, and thus the external soft-start voltage vss_ext linearly rises from 0V to the first reference voltage Vref1 according to the slope (Ib 1-Ib 2)/Cext (where Ib1 is the output current of the current source 411, ib2 is the output current of the current source 412, cext represents the capacitance value of the external capacitor), as shown in fig. 6 b.

Fig. 7a and 7b show a schematic circuit diagram and a schematic waveform diagram, respectively, of an internal soft start module 402 according to an embodiment of the present invention.

Referring to fig. 7a, the internal soft start module 402 of the present embodiment includes a current source 413, a capacitor C1, and an NMOS transistor M3. Wherein the current source 413 and the capacitor C1 are connected in series between the power supply voltage VDD and ground, and an intermediate node thereof is used to output the internal soft start voltage vss_int. The drain of the NMOS transistor M3 is connected to the current source 413 and the intermediate node of the capacitor C1, the gate of the NMOS transistor M3 is connected to the short indication signal ss_short, and the source of the NMOS transistor M3 is connected to ground.

When the short indication signal ss_short is active, the NMOS transistor M3 is turned on, and the internal soft start voltage vss_int is pulled down to 0V, which cannot be established. When the short indication signal ss_short is inactive, the NMOS transistor M3 is turned off, the capacitor C1 is charged by the current source 413, and the internal soft start voltage vss_int linearly rises from 0V to the power supply voltage VDD according to a slope Ib3/C1 (where Ib3 represents the output current of the current source 413, and C1 represents the capacitance value of the capacitor C1), as shown in fig. 7 b.

Fig. 8 to 10 are schematic circuit diagrams of an external tracking voltage detection module 403, a pin short detection module 404, and a voltage switching module 405 according to an embodiment of the present invention.

Referring to fig. 8, the external tracking voltage detection module 403 includes a comparator COMP1, a D flip-flop DFF, an inverter INV1, AND an AND circuit AND1. The non-inverting input terminal of the comparator COMP1 is configured to receive the external soft start voltage vss_ext, the inverting input terminal of the comparator COMP1 is configured to receive the first reference voltage Vref1, and the enabling terminal of the comparator COMP1 is configured to receive the first enable signal EN1. The data terminal D of the D flip-flop DFF is connected to the output terminal of the comparator COMP1, the clock terminal Clk of the D flip-flop DFF is configured to receive the second enable signal EN2, the Reset terminal Reset of the D flip-flop DFF is configured to receive the first enable signal EN1, and the output terminal Q of the D flip-flop DFF is configured to output the signal TRK. An input terminal of the inverter INV1 is connected to the output terminal Q of the D flip-flop DFF, an output terminal of the inverter INV1 is connected to a first input terminal of the AND circuit AND1, a second input terminal of the AND circuit AND1 is connected to the second enable signal EN2, AND an output terminal of the AND circuit AND1 is used for outputting the tracking instruction signal trk_n.

The first enable signal EN1 and the second enable signal EN2 are used to control the start timing of the circuit, and the rising edge of the second enable signal EN2 is later than the rising edge of the first enable signal EN 1. If the output voltage tracking function of the circuit is to be enabled, a DC voltage source VTRK is required to be applied to the external soft-start terminal 204 before the circuit is operated, at which time the external soft-start voltage Vss_ext is equal to the external reference voltage VTRK. When the first enable signal EN1 is inverted to a high level, the comparator COMP1 is enabled, and since the general external reference voltage VTRK is higher than the first reference voltage Vref1, the comparator COMP1 outputs a high level. Then when the rising edge of the second enable signal EN2 arrives, the D flip-flop DFF transmits the high level of the data terminal D to the output terminal Q, the signal TRK is inverted to the high level, the output of the inverter INV1 is inverted to the low level, AND then the valid (e.g., low level) tracking indication signal trk_n is obtained at the output terminal of the AND circuit AND1, otherwise, when the rising edge of the second enable signal EN2 arrives, the valid (e.g., high level) tracking indication signal trk_n is obtained at the output terminal of the AND circuit AND 1.

Referring to fig. 9, the pin short detection block 404 includes a comparator COMP2, an AND circuit AND2, AND an inverter INV2. The positive input end of the comparator COMP2 is configured to receive the external soft start voltage vss_ext, the negative input end of the comparator COMP2 is configured to receive the second reference voltage, the enable end of the comparator COMP2 is configured to receive the first enable signal EN1, the output end of the comparator COMP2 is connected to the first input end of the AND circuit AND2, the second input end of the AND circuit AND2 is connected to the second enable signal EN2, the output end of the AND circuit AND2 is configured to output the signal ss_ shortb, the input end of the inverter INV2 is connected to the output end of the AND circuit AND2, AND the output end of the inverter INV2 is configured to output the short circuit indication signal ss_short.

When the rising edge of the first enable signal EN1 arrives, the comparator COMP2 is enabled to compare the external soft start voltage vss_ext with the second reference voltage Vref2, if the external soft start terminal 204 has a short circuit event, the external soft start voltage vss_ext is smaller than the second reference voltage Vref2, so that the comparator COMP2 outputs a low level, AND when the rising edge of the second enable signal EN2 arrives, the signal ss_ shortb output by the AND circuit AND2 is at a low level, AND finally, a valid (e.g., high level) short circuit indication signal ss_short is obtained at the output end of the nand gate INV 2. If no short circuit event occurs at the external soft start terminal 204, the external soft start voltage vss_ext is greater than the second reference voltage Vref2, so that the comparator COMP2 outputs a high level, AND the signal ss_ shortb output from the AND circuit AND2 is a high level when the rising edge of the second enable signal EN2 arrives, AND finally, the short circuit indication signal ss_short that is invalid (e.g., low level) is obtained at the output terminal of the nand gate INV 2.

Referring to fig. 10, the voltage switching module 405 includes a transmission gate composed of a comparator COMP3, an inverter INV3, NMOS transistors M4 and M5, an NMOS transistor M6, and a capacitor C2. The non-inverting input terminal of the comparator COMP3 is configured to receive the internal soft start voltage vss_int, the inverting input terminal of the comparator COMP3 is configured to receive the external soft start voltage vss_ext, the output terminal of the comparator COMP3 is configured to output the transmission gate switching signal Q, the input terminal of the inverter INV3 is configured to receive the signal Q, and the output terminal of the inverter INV3 is configured to output the inverted signal Qb of the signal Q. In the transmission gate, the drain of the NMOS transistor M4 is connected to the internal soft start voltage vss_int, the gate of the NMOS transistor M4 is connected to the signal Qb, the source of the NMOS transistor M4 is connected to the output of the soft start voltage signal Vss, the drain of the NMOS transistor M5 is connected to the external soft start voltage vss_ext, the gate of the NMOS transistor M5 is connected to the signal Q, and the source of the NMOS transistor M5 is connected to the output of the soft start voltage signal Vss. A first terminal of the capacitor C2 is connected to the output terminal of the soft start voltage signal Vss, and a second terminal of the capacitor C2 is connected to ground. The drain of the NMOS transistor M6 is connected to the output terminal of the soft start voltage signal Vss, the source of the NMOS transistor M6 is connected to ground, and the gate of the NMOS transistor M6 is connected to the short indication signal ss_short.

When the internal soft start voltage vss_int is smaller than the external soft start voltage vss_ext, the comparator COMP3 outputs a low level, so that the NMOS transistor M4 is turned on, the NMOS transistor M5 is turned off, and the transmission gate transmits the internal soft start voltage vss_int to the output terminal of the soft start voltage signal, so that the soft start voltage signal Vss rises linearly according to the slope of the internal soft start voltage vss_int. When the internal soft start voltage vss_int is greater than the external soft start voltage vss_ext, the comparator COMP3 outputs a high level, so that the NMOS transistor M4 is turned off, the NMOS transistor M5 is turned on, and the transmission gate switches the soft start voltage signal Vss from the internal soft start voltage vss_int to the external soft start voltage vss_ext, thereby realizing smooth switching of the soft start voltage.

Fig. 11 to 13 respectively show timing diagrams of the soft start circuit in different soft start processes according to the embodiment of the invention. In which the timing diagrams of the tracking indication signal trk_n, the external soft start voltage vss_ext, the short circuit indication signal ss_short, the internal soft start voltage vss_int, the output of the comparator COMP3, and the soft start voltage signal Vss are shown, respectively. The operation principle of the soft start circuit according to the embodiment of the present invention is described in detail with reference to the above description and fig. 11 to 13.

Referring to fig. 11, when the soft start circuit 242 operates under the internal soft start function, the capacitance value of the external capacitor Cext connected to the external soft start terminal 204 is required to be smaller, so as to ensure that the slope of the external soft start voltage vss_ext is larger than that of the internal soft start voltage vss_int. Since the external soft start terminal 204 has no external voltage source, the output of the comparator COMP1 is low level, and the tracking indication signal trk_n is turned inactive (i.e., high level) when the rising edge of the second enable signal EN2 comes. At this time, the external soft start module 401 is enabled and the external soft start voltage vss_ext is linearly increased from 0V with an increasing slope of (Ib 1-Ib 2)/Cext. When the external soft start voltage vss_ext rises to the second reference voltage Vref2 (e.g., 50 mV), the short indication signal ss_short changes from high level to low level, and then the internal soft start module is enabled to be activated, and the internal soft start voltage vss_int rises linearly from 0V with a rising slope of Ib3/C1. Since the internal soft start voltage vss_int is smaller than the external soft start voltage vss_ext, the soft start voltage signal Vss is switched to the internal soft start voltage vss_int to linearly rise with the rising slope Ib3/C1. Since the maximum value of the external soft start voltage vss_ext is equal to the first reference voltage Vref1, i.e., the external soft start voltage vss_ext will not change any more when the external soft start voltage vss_ext rises to the first reference voltage Vref1 (e.g., 600 mV), the soft start voltage signal Vss is switched to the external soft start voltage vss_ext when the internal soft start voltage vss_int rises to 600mV, i.e., the soft start voltage signal Vss is equal to the first reference voltage Vref1 and does not change any more. It can be seen that when the soft start circuit 242 operates under the internal soft start function, the soft start time is equal to the time for the internal soft start voltage vss_int to rise from 0V to the first reference voltage Vref1, for example, 1ms.

Referring to fig. 12, when the soft start circuit 242 operates under the external soft start function, the capacitance value of the external capacitor Cext connected to the external soft start terminal 204 is required to be relatively large, so as to ensure that the slope of the external soft start voltage vss_ext is smaller than that of the internal soft start voltage vss_int. Since the external soft start terminal 204 has no external voltage source, the output of the comparator COMP1 is low level, and the tracking indication signal trk_n is turned inactive (i.e., high level) when the rising edge of the second enable signal EN2 comes. At this time, the external soft start module 401 is enabled and the external soft start voltage vss_ext is linearly increased from 0V with an increasing slope of (Ib 1-Ib 2)/Cext. When the external soft start voltage vss_ext rises to the second reference voltage Vref2 (e.g., 50 mV), the short indication signal ss_short changes from high level to low level, and then the internal soft start module is enabled to be activated, and the internal soft start voltage vss_int rises linearly from 0V with a rising slope of Ib3/C1. Because of the existence of the pin short circuit detection module, the internal soft start voltage vss_int is slightly delayed from the external soft start voltage vss_ext, so that in order to obtain a smoothly rising soft start voltage signal Vss, the soft start voltage signal Vss comprises 2 slopes, the slope of the first segment is equal to the rising slope of the internal soft start voltage vss_int, the slope of the second segment is equal to the slope of the external soft start voltage vss_ext, the soft start time of the soft start voltage signal Vss is mainly determined by the slope of the second segment, and the soft start time Tss of the process can be flexibly adjusted by adjusting the capacitance value of the external capacitor Cext.

Referring to fig. 13, when the soft start circuit 242 operates under the output voltage tracking function, an external reference voltage VTRK, whose voltage value generally needs to be higher than that of the first reference voltage Vref1 (e.g., 600 mV), needs to be applied at the external soft start terminal 204 just before the rising edge of the second enable signal EN2, at which time a short circuit state at the external soft start terminal 204 does not exist, so that the soft start voltage signal Vss follows the internal soft start voltage vss_int to rise after the short circuit indication signal ss_short toggles to a low level, and when the internal soft start voltage vss_int increases to the external reference voltage VTRK, the soft start voltage signal Vss switches to the external soft start voltage vss_ext, i.e., the soft start voltage signal Vss is equal to the external reference voltage VTRK. In this process, the rising slope of the soft start voltage signal Vss is equal to the slope of the internal soft start voltage vss_int, so the soft start time Tss is mainly determined by the external reference voltage VTRK, for example, when the external reference voltage VTRK is equal to 1.2V, the soft start time tss=2ms of the circuit. After the soft start process is finished, the voltage value of the external reference voltage VTRK can be adjusted to regulate the soft start voltage signal Vss, and then the power supply automatically changes the voltage value of the output voltage VOUT through the feedback loop, so that the function of tracking the output voltage VOUT to the external reference voltage VTRK is realized.

It should be noted that although the device is described herein as an N-channel or P-channel device, or an N-type or P-type doped region, it will be appreciated by those of ordinary skill in the art that complementary devices may be implemented in accordance with the present invention. It will be appreciated by those of ordinary skill in the art that conductivity type refers to a mechanism by which electrical conduction occurs, such as by hole or electron conduction, so conductivity type does not relate to doping concentration but rather to doping type, such as P-type or N-type. It will be appreciated by those of ordinary skill in the art that the terms "during", "when" and "when … …" as used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the start of a start-up action, but rather there may be some small but reasonable delay or delays between it and the reaction action (reaction) initiated by the start-up action, such as various transmission delays and the like. The word "about" or "substantially" is used herein to mean that an element value (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation such that the value or position is difficult to strictly assume the stated value. It has been well established in the art that deviations of at least ten percent (10%) (at least twenty percent (20%)) for semiconductor doping concentrations are reasonable deviations from the exact ideal targets described. When used in connection with a signal state, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.

Furthermore, it should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A soft start circuit for a power converter for providing a rising soft start voltage signal during circuit start-up, the power converter further comprising an error amplifier for obtaining a difference between a feedback signal and the soft start voltage signal, wherein the soft start circuit comprises:

the internal soft start module is used for generating rising internal soft start voltage;

The external soft start module is connected with the external soft start terminal and is used for generating external soft start voltage; and

A voltage switching module for comparing the internal soft start voltage with the external soft start voltage and switching the soft start voltage signal according to the smaller one of the two,

Wherein the external soft start terminal is for connecting an external capacitor or a voltage source for providing an external reference voltage to allow the external capacitor or the external reference voltage to at least partially control the rise time of the soft start voltage signal during circuit start-up.

2. The soft start circuit of claim 1, wherein the internal soft start voltage has a fixed first rising slope and the external soft start voltage has at least a second rising slope associated with the external capacitor.

3. The soft start circuit of claim 1, further comprising:

An external tracking voltage detection module for comparing the external soft start voltage with a first reference voltage to generate a tracking indication signal and controlling the output of the external soft start module according to the tracking indication signal,

Wherein when the tracking indication signal is valid, the external soft start module generates the external soft start voltage equal to the external reference voltage,

When the tracking indication signal is invalid, the external soft start module generates a rising external soft start voltage.

4. The soft start circuit of claim 3, further comprising:

A pin short circuit detection module for comparing the external soft start voltage with a second reference voltage to generate a short circuit indication signal and controlling the internal soft start module and the voltage switching module to be turned on and off according to the short circuit indication signal,

Wherein the second reference voltage is less than the first reference voltage.

5. The soft start circuit of claim 4, wherein the external soft start module comprises:

A first current source, a first transistor, and a second current source connected in series between a power supply voltage and ground, an intermediate node of the first transistor and the second current source for outputting the external soft start voltage;

the inverting input end of the operational amplifier is connected with the first reference voltage, the non-inverting input end of the operational amplifier is connected with the output node of the external soft start voltage and the external soft start terminal, the enabling end of the operational amplifier is connected with the tracking indication signal, and the output end of the operational amplifier is connected with the control end of the first transistor; and

And a second transistor connected between an output node of the external soft start voltage and ground, a control terminal of the second transistor being connected with an inverted signal of the first enable signal.

6. The soft start circuit of claim 4, wherein the internal soft start module comprises:

a third current source and a first capacitor connected in series between a power supply voltage and ground, and an intermediate node of the third current source and the first capacitor is used for outputting the internal soft start voltage; and

And a third transistor connected between an output node of the internal soft start voltage and ground, a control terminal of the third transistor being connected to the short circuit indication signal.

7. The soft start circuit of claim 4, wherein the external tracking voltage detection module comprises:

the non-inverting input end of the first comparator is connected with the external soft start voltage, the inverting input end of the first comparator is connected with the first reference voltage, and the enabling end of the first comparator is connected with a first enabling signal;

The data end of the D trigger is connected with the output end of the first comparator, the clock end of the D trigger is connected with the second enabling signal, and the reset end of the D trigger is connected with the first enabling signal;

the input end of the first inverter is connected with the output end of the D trigger; and

A first AND gate circuit, a first input end of the first AND gate circuit is connected with an output end of the first inverter, a second input end of the first AND gate circuit is connected with the second enabling signal, an output end of the first AND gate circuit is used for generating the tracking indication signal,

Wherein the active edge of the second enable signal lags the active edge of the first enable signal.

8. The soft start circuit of claim 4, wherein the pin short detection module comprises:

The non-inverting input end of the second comparator is connected with the external soft start voltage, the inverting input end of the second comparator is connected with the second reference voltage, and the enabling end of the second comparator is connected with a first enabling signal;

The first input end of the second AND gate circuit is connected with the output end of the second comparator, and the second input end of the second AND gate circuit is connected with a second enabling signal; and

And the input end of the second inverter is connected with the output end of the second AND gate circuit, and the output end of the second inverter is used for generating the short circuit indication signal.

9. The soft start circuit of claim 4, wherein the voltage switching module comprises:

A third comparator for comparing the internal soft start voltage with the external soft start voltage to generate a transmission gate switching signal;

The input end of the transmission gate is connected with the internal soft start voltage and the external soft start voltage, the control end of the transmission gate is connected with the switch signal of the transmission gate, and the output end of the transmission gate is connected with the output end of the soft start voltage signal;

a second capacitor connected between an output terminal of the soft start voltage signal and ground; and

And a control end of the fourth transistor is connected with the short circuit indication signal.

10. A power converter comprising the soft start circuit of any one of claims 1-9.