CN116896271A - Power state detection circuit applied to DC-DC converter and DC-DC converter - Google Patents
Power state detection circuit applied to DC-DC converter and DC-DC converter Download PDFInfo
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- CN116896271A CN116896271A CN202310664366.8A CN202310664366A CN116896271A CN 116896271 A CN116896271 A CN 116896271A CN 202310664366 A CN202310664366 A CN 202310664366A CN 116896271 A CN116896271 A CN 116896271A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
Abstract
The invention discloses a power state detection circuit applied to a DC-DC converter and the DC-DC converter. Comprising the following steps: a pull-up resistor connected between an output terminal for outputting a power good signal and a pull-up power supply; a comparator configured to compare a feedback signal related to an output voltage of the DC-DC converter with a reference voltage signal to generate a first signal; a logic conversion module configured to perform logic conversion on the first signal to generate a second signal; and an output module connected between the logic conversion module and the output terminal and configured to generate a power good signal according to an enable control signal and the second signal, wherein the output module is configured to control a corresponding state of the power good signal according to a level state of the second signal in response to the valid enable control signal, so that the power good signal is not influenced by factors such as stability and rising speed of a power voltage, and is beneficial to improving working stability and precision of the power state detection circuit.
Description
Technical Field
The present invention relates to the field of power management, and in particular, to a power state detection circuit applied to a DC-DC converter and a DC-DC converter.
Background
With the development of power electronics and semiconductor technology, power management chips are widely used in the fields of communication, consumption, computing, and the like. DC-DC converters, which are among the most common ones in power management chips, typically comprise one or more switches that are selectively actuated to provide a controlled DC output voltage or current based on a received DC input, the output power of the circuit being regulated by controlling the pulse width or the time of the signal provided to the one or more switches of the converter according to an error signal.
The output voltage of the DC-DC converter is often used as a power source for supplying power to the whole system, and the stability of the output voltage directly affects the operation state of the whole system, so that a power state detection circuit (Power Good Detection Circuit, also referred to as a PG detection circuit) needs to be designed in the DC-DC converter. The PG detection circuit is a circuit for monitoring whether the system voltage reaches a preset value. When the system voltage reaches a set threshold, the PG detection circuit generates a level signal marked as PG to indicate whether the system is in a normal working state. In general, the PG signal is used as an enable signal to control the power supply module, thereby ensuring that the system voltage and current are within a normal range.
In a DC-DC converter chip, a PG detection circuit is generally powered by a power supply voltage inside the chip, and then a comparator is used to compare the difference between the output voltage of the converter and a set threshold value, and convert the comparison result into a digital signal. The conventional PG detection circuit may have a certain influence on the working performance due to the influence of factors such as stability of the power supply voltage and rising speed. For example, if the power supply voltage fluctuates or noise is large, the PG detection circuit may misjudge the system state or an abnormality may occur in actual operation. Or when the input voltage of the switching power supply rises faster, the PG detection circuit may delay response, or a missing detection condition occurs in actual operation.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a power state detection circuit applied to a DC-DC converter and a DC-DC converter, which improve the influence of a chip power supply voltage on detection accuracy.
According to an aspect of the present invention, there is provided a power state detection circuit applied to a DC-DC converter, including: a pull-up resistor connected between an output terminal for outputting a power good signal and a pull-up power supply; a comparator configured to compare a feedback signal related to an output voltage of the DC-DC converter with a reference voltage signal to generate a first signal; a logic conversion module configured to logically convert the first signal to generate a second signal; and an output module connected between the logic conversion module and the output terminal and configured to generate the power good signal according to an enable control signal and the second signal, wherein the output module is configured to control a corresponding state of the power good signal according to a level state of the second signal in response to the enable control signal being active.
Optionally, the power state detection circuit includes a power state detection circuit in a control circuit of the DC-DC converter, the control circuit further includes an internal regulator, and the enable control signal is valid when the control circuit receives a valid enable signal and the internal regulator generates a stable internal power voltage according to an input voltage of the DC-DC converter.
Optionally, the pull-up power supply is used for being connected with an internal power supply voltage of the control circuit or an external power supply voltage of a system.
Optionally, the output terminal includes a power good terminal or pin of a control circuit of the DC-DC converter formed on the integrated circuit chip.
Optionally, the output module includes: a first transistor, a first end of which is connected with the second signal, and a control end of which is connected with the enabling control signal; a first resistor and a second transistor connected in series between the output terminal and the reference ground, a control terminal of the second transistor being connected to a second terminal of the first transistor; and a third transistor and a second resistor connected in series between the output terminal and the reference ground, a control terminal of the third transistor being connected to the enable control signal.
Optionally, the method further comprises: a bias module configured to provide a bias voltage to a control terminal of the second transistor according to the input voltage, the bias module comprising: a third resistor and a fourth resistor connected in series between the input voltage and the control terminal of the second transistor; and the cathode of the diode is connected with a common node of the third resistor and the fourth resistor, and the anode of the diode is connected with the reference ground.
Optionally, the second signal and the first signal are mutually opposite signals, and the logic conversion module includes: a fourth transistor and a fifth transistor connected in series between the internal power supply voltage and a reference ground, control terminals of the fourth transistor and the fifth transistor being connected to the first signal, a second terminal of the fourth transistor and a first terminal of the fifth transistor being used for outputting the second signal.
Optionally, the resistance value of the fourth resistor is larger than the on-resistance of the first transistor and the fifth transistor.
Optionally, the first transistor, the second transistor and the fifth transistor are NMOS transistors, and the third transistor and the fourth transistor are PMOS transistors.
According to another aspect of the present invention, there is provided a DC-DC converter including: a control circuit, comprising: a power input terminal for connecting an input voltage; an internal regulator connected to the power input terminal and configured to generate an internal power supply voltage from the input voltage when activated; an enable input terminal for connecting an enable signal; a schmitt trigger connected to the enable input terminal and configured to activate the internal regulator when the enable signal is active; a feedback terminal for connecting a feedback signal of the output voltage; a power good terminal for outputting a power good signal; and a power state detection circuit according to any one of the above, the power state detection circuit being connected to the feedback terminal and the power good terminal.
The power state detection circuit applied to the DC-DC converter provided by the embodiment of the invention comprises a pull-up resistor, a comparator, a logic conversion module and an output module. The pull-up resistor is connected between an output terminal for outputting a power source good signal and a pull-up power source, the comparator is used for comparing a feedback signal of the output voltage of the DC-DC converter with a set reference voltage signal, the logic conversion module is used for carrying out logic conversion on the output signal of the comparator, the output module generates the power source good signal according to an enabling control signal and the output of the logic conversion module, and the output module is configured to output the power source good signal in a corresponding state according to the comparison result of the comparator only when the enabling control signal is valid. Compared with the traditional scheme, the power state detection circuit of the embodiment is not influenced by factors such as stability and rising speed of power voltage in the DC-DC converter, misjudgment can not occur under any power supply condition, and working stability and precision of the power state detection circuit are improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a circuit schematic of a control circuit of a DC-DC converter with a power state detection circuit according to an embodiment of the invention.
Fig. 2 shows a circuit schematic of a power state detection circuit according to an embodiment of the invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
Numerous specific details of the invention, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
The embodiment of the invention firstly provides a DC-DC converter control circuit with a power state detection circuit (also called PG detection circuit), which is used for PWM control of the DC-DC converter. Various exemplary examples are illustrated and described below in connection with a Buck-converter type system, but the invention is not limited in this regard and the various concepts disclosed herein may be used in connection with any type of DC-DC converter architecture, including Buck-type (Buck) converters, boost-type (Boost) converters, flyback-type (Flyback-Boost) converters, and the like, depending on the topology classification of the power circuit, for example. Furthermore, while complementary PWM control of the high-side switching device and the low-side switching device is utilized in the illustration of the embodiments of the present invention, the concepts described herein can be implemented in DC-DC converters that use only a single switching device and/or in DC-DC converters that employ more than two pulse width modulations.
Fig. 1 shows a circuit schematic of a control circuit 100 of a DC-DC converter according to an embodiment of the invention. In the example of fig. 1, the control circuit 100 includes self-contained power conversion devices S1 and S2, and corresponding high-side gate driver 115 and low-side gate driver 116, although in other examples, one or all of these components may be external to the integrated circuit 100.
In some embodiments, the control circuit 100 is a monolithic converter formed on an integrated circuit, wafer, chip, or die, which may be implemented as an integrated circuit having various terminals or pins, as shown, for interconnection with other components of the DC-DC converter system. Similarly, the control circuit 100 in fig. 1 provides a power input terminal 101 for connecting the input voltage VIN, an enable input terminal 102 for connecting an enable signal EN for on/off circuit operation, a power good terminal 104 for outputting a power good signal PG, and a ground terminal (PGND) 107. In addition to this, the control circuit 100 provides feedback terminals 103 for monitoring the output voltage to be connected to the feedback circuits R1, R2 and C1 of the external buck converter, and output terminal (LX) 107 to be connected to the output inductor L1 of the external buck converter, but other examples are possible, and one or more of the above components may be provided in the integrated circuit 100.
In addition, in the embodiment shown in fig. 1, the control circuit 100 generally further includes a schmitt trigger 110, an error amplifier 112, an internal regulator 113, a logic controller 114, and a power state detection circuit 120.
The schmitt trigger 110 is configured to receive the enable signal EN and provide a logic output (active high in one example) to activate the logic controller 114 and the internal regulator 113. Illustratively, the schmitt trigger 110 turns off the device when the enable signal EN at the terminal 102 is low and activates the device when the enable signal EN at the terminal 102 is high.
An input of the internal regulator 113 is connected to the power input terminal 101 for deriving an internal power supply voltage VDD from the input voltage VIN to power a plurality of modules in the control circuit 100.
Error amplifier 112 has a non-inverting input for receiving reference voltage signal VREF1 (e.g., generated by a voltage reference and current bias circuit), an inverting input for receiving feedback signal FB of the output voltage VOUT of the DC-DC converter, and an output, in the embodiment shown in fig. 1, a resistive divider circuit provided by external resistors R1 and R2 and a stabilizing or filtering capacitor C1, providing feedback signal FB to the inverting input of error amplifier 112 via feedback terminal 103 through the connection of R1 and C1 to the output voltage at load 108 (as indicated by the dashed line in fig. 1). Error amplifier 112 is configured to compare the feedback voltage VFB with the reference voltage signal VREF1 to generate a loop error signal VEA, which represents the difference between the feedback voltage VFB and the reference voltage signal VREF 1.
The logic controller 114 is for implementing a logic control function of the system, and has a first input terminal connected to the output terminal of the schmitt trigger 110, a second input terminal connected to the output terminal of the internal regulator 113, a third input terminal connected to the output terminal of the error amplifier 112, a first output terminal for outputting the high-side modulation signal HSDR, and a second output terminal for outputting the low-side modulation signal LSDR. By way of example, the logic controller 114 may include a Pulse Width Modulator (PWM) circuit or any suitable circuit capable of controlling the duty cycle of the power conversion devices S1 and S2 in the DC-DC converter. Those skilled in the art will appreciate that the logic control 114 may also be implemented by different architectures. Meanwhile, the control principle of the synchronous rectification buck DC-DC converter should be well known to those skilled in the art.
The high-side output switch S1 and the low-side output switch S2 are connected in series with each other between the power input terminal 101 and the ground terminal 107. The output switches S1 and S2 are NMOS transistors with corresponding diodes D1 and D2 connected as shown in fig. 1, but the invention is not limited thereto, other embodiments are possible in which different types of switches are used, and/or the switches S1 and S2 may be integrated outside the control circuit 100. The pulse width modulated gate control signals are provided to switches S1 and S2 by corresponding high side gate driver 115 and low side gate driver 116, respectively, wherein the drivers 115 and 116 receive the high side modulated signal and the low side modulated signal from corresponding outputs HSDR and LSDR, respectively, of the logic controller 114. An output terminal (LX) 106 is used for controlling the connection of the external inductor L1 between the circuit 100 and the load 108, wherein the output terminal 106 is connected to the common connection of the high side output switch S1 and the low side output switch S2 as shown.
In steady state operation of the DC-DC converter system, the level of the loop error signal VEA will represent an error that is indicative of the difference between the feedback signal FB and the reference voltage signal VREF 1. The logic controller 114 receives the loop error signal VEA from the error amplifier 112 and generates complementary high-side and low-side modulated signals HSDR and LSDR, which are provided as inputs to the high-side and low-side drivers 115 and 116, respectively. In an exemplary embodiment, the logic controller 114 may include a PWM comparator and an oscillator (not shown), where the PWM comparator is configured to compare the output signal VEA of the error amplifier 112 with a periodic ramp signal (e.g., the periodic ramp signal is related to an inductor current of the DC-DC converter), and obtain a PWM signal with a pulse width modulation according to the comparison result. In operation, when the loop error signal VEA is greater than the periodic ramp signal, the PWM signal is high; otherwise, the PWM signal is low and the PWM comparator may provide a certain level later. As a result, a pulse stream will be provided at the PWM signal, wherein the pulse width of the PWM signal (the percentage of time the PWM signal is high) will be substantially proportional to the level of the loop error signal VEA output by the error amplifier 112. And, the logic controller 114 generates the high side modulation signal HSDR and the low side modulation signal LSDR according to the PWM signal from the PWM comparator and the pulse stream signal from the oscillator. This closed loop configuration allows the pulse width in the PWM signal to be adjusted to drive the output voltage VOUT at the load 108 such that the output voltage VOUT corresponds to the reference level represented by the reference voltage signal VREF 1.
The power state detection circuit 120 has an input terminal connected to the feedback terminal (FB) 103, and has an output terminal connected to the terminal 104, and the terminal 104 is connected to the pull-up power supply 105 through a pull-up resistor Rup, wherein the pull-up power supply 105 may be connected to the chip internal power supply voltage VDD or the chip external power supply voltage VDC. The power state detection circuit 120 is configured to determine whether the output voltage VOUT of the DC-DC converter reaches a set range according to the feedback signal FB received at the feedback terminal 103, and when the voltage of the feedback signal FB reaches a predetermined voltage, the power state detection circuit 120 generates a high level signal labeled "PG" (generally referred to as a power good signal) via the terminal 104 to indicate whether the system is in a normal operation state. Typically, the PG signal may be used to monitor the correct output voltage of the power module or to control the start-up timing between multiple DC-DC converters. Further, the power state detection circuit 120 of the present embodiment is further configured to receive an enable control signal ldo_ok, wherein the enable control signal ldo_ok is used to indicate that the control circuit 100 receives a valid enable signal EN, and the internal regulator 113 is capable of generating a stable internal power voltage VDD. For example, the enable control signal ldo_ok may be generated by detecting an output of the internal regulator 113, enabling control of the internal regulator 113 to be turned on when the control circuit 100 receives an enable signal EN that is valid (e.g., high level), and enabling the control signal ldo_ok to be flipped to a valid state (e.g., high level) when the internal regulator 113 generates a stable voltage output. Wherein the enable control signal ldo_ok is configured to control the operation of the power state detection circuit 120, that is, when the enable control signal ldo_ok is active, the power state detection circuit 120 controls the state of the power good signal PG according to the comparison result between the feedback signal FB and the set voltage, and when the enable control signal ldo_ok is inactive, the power state detection circuit 120 keeps the power good signal PG at a low level (may also be referred to as an inactive state).
Fig. 2 shows a circuit schematic of a power state detection circuit according to an embodiment of the present invention, and as shown in fig. 2, the power state detection circuit of the present embodiment includes: comparator 121, logic conversion module 122, output module 123, and voltage bias module 124.
The comparator 121 has a positive input terminal, an inverted input terminal, an output terminal, a positive power supply terminal, and a negative power supply terminal, wherein the positive input terminal of the comparator 121 is connected to the feedback terminal of the control circuit 100 to receive the feedback signal FB, the inverted input terminal thereof is used for receiving the reference voltage signal VREF2, the positive power supply terminal thereof is connected to the power supply voltage VDD inside the chip, and the negative power supply terminal thereof is connected to the ground GND. The comparator 121 is configured to compare the feedback signal FB with the reference voltage signal VREF2, and output a first signal pg_ok at its output terminal. For example, the reference voltage signal VREF2 is generally 90% of the preset output voltage, and the first signal pg_ok output by the comparator 121 is inverted to be high when the feedback signal FB starts rising from 0 to 90% of the preset output voltage.
The logic conversion module 122 is configured to perform logic conversion on the first signal pg_ok to generate a second signal pg_ok2 that is opposite to the first signal pg_ok. For example, the logic conversion module 122 is implemented by an inverter, as shown in fig. 2, where the logic conversion module 122 includes transistors M1 and M2 connected in series between the chip internal power supply voltage VDD and the ground GND, the transistor M1 is, for example, a PMOS transistor, the transistor M2 is, for example, an NMOS transistor, gates of the transistors M1 and M2 are connected to each other and to an output terminal of the comparator 121, a source of the transistor M1 is connected to the internal power supply voltage VDD, a drain of the transistor M1 is connected to a drain of the transistor M2 and to an output terminal of the second signal pg_ok2, and a source of the transistor M2 is connected to the ground GND.
The output module 123 has a first input terminal receiving the second signal pg_ok2, a second input terminal for receiving the enable control signal ldo_ok, and an output terminal connected to the output terminal 104 of the power OK signal PG. Further, as described above, the output terminal 104 of the power good signal PG is also connected to one end of a pull-up resistor Rup, and the other end of the pull-up resistor Rup is connected to a pull-up power supply 105, and the pull-up power supply 105 may be connected to the chip internal power supply voltage VDD or the chip external power supply voltage VDC, for example. The pull-up resistor Rup is an off-chip resistor, typically having a resistance of 100kΩ or 200kΩ, for example. The output module 123 is configured to control the level state of the power good signal PG according to the second signal pg_ok2 under the control of the enable control signal ldo_ok. For example, when the enable control signal ldo_ok is inactive (e.g., low), the output module 123 maintains the power good signal PG at a low level; when the enable control signal ldo_ok is active (e.g., high), the output module 123 obtains a corresponding level of the power good signal PG according to the level state of the second signal pg_ok2.
Further, the output module 123 includes transistors M3 to M5 and resistors R5 and R6. The transistors M3 and M4 are, for example, NMOS transistors, and the transistor M5 is, for example, a PMOS transistor. The source of the transistor M3 is connected to the second signal pg_ok2, the gate of the transistor M3 is connected to the enable control signal ldo_ok, and the drain of the transistor M3 is connected to the gate of the transistor M4. The resistor R5 and the transistor M4 are connected between the output terminal 104 of the power good signal PG and the ground GND, wherein a first end of the resistor R5 is connected to the output terminal 104 of the power good signal PG, a second end of the resistor R5 is connected to the drain of the transistor M4, and a source of the transistor M4 is connected to the ground GND. The transistor M5 and the resistor R6 are connected in series between the output terminal 104 of the power good signal PG and the ground GND, the source of the transistor M5 is connected to the output terminal 104 of the power good signal PG, the gate of the transistor M5 is connected to the enable control signal ldo_ok, the drain of the transistor M5 is connected to the first end of the resistor R6, and the second end of the resistor R6 is connected to the ground GND. In this embodiment, the resistors R5 and R6 are current limiting resistors, and the resistance value thereof is generally 100 Ω or less.
The bias module 124 is configured to provide a bias voltage to the gate of the transistor M4 according to the input voltage VIN. Further, the bias module 124 includes resistors R3 and R4 and a diode D1, wherein the resistors R3 and R4 are connected in series between the input terminal of the input voltage VIN and the gate of the transistor M4, the cathode of the diode D1 is connected to the intermediate node of the resistors R3 and R4, and the anode of the diode D1 is connected to the ground GND. In this embodiment, the resistor R3 is a resistor having a resistance in the order of mega ohms, and the resistance of the resistor R4 is the sum of the on-resistances of the transistors M2 and M3, which is in the order of k Ω or much larger than 100 times.
The operation principle of the power state detection circuit 120 of the present embodiment is described in detail below with reference to fig. 2. When the pull-up power supply 105 is connected to the internal power supply voltage VDD of the chip, the power good signal PG at the terminal 104 is always at a low level as long as the internal power supply voltage VDD of the chip is not established, and false detection does not occur. When the pull-up power supply 105 is connected to the system external power supply voltage VDC, when the enable signal EN and the input voltage VIN of the DC-DC converter are both low, the enable control signal ldo_ok is low, the NMOS transistors M3 and M4 are turned off, the PMOS transistor M5 is turned on, and the power good signal PG at the terminal 104 is pulled low. When the enable signal EN is low, the input voltage VIN is lower than the on threshold of the transistor M4, the enable control signal ldo_ok is low, the NMOS transistors M3 and M4 are turned off, the PMOS transistor M5 is turned on, and the power good signal PG at the terminal 104 is pulled low. When the enable signal EN is at a low level and the input voltage VIN is higher than the on threshold of the transistor M4, the enable control signal ldo_ok is at a low level, the NMOS transistor M3 is turned off, the NMOS transistor M4 is turned on by the input voltage VIN, and the gate of the NMOS transistor M4 is not damaged by the overvoltage due to the protection of the diode D1, and the NMOS transistor M4 pulls the power good signal PG at the terminal 104 low to a low level. When the enable signal EN is high, but the input voltage VIN is low (i.e., the power supply voltage VDD inside the chip has not yet been established), the enable control signal ldo_ok is still low, so the voltage at the terminal 104 is still pulled low by the PMOS transistor M5. When the enable signal EN is at a high level and the input voltage VIN is higher, the power supply voltage VDD inside the chip is stably established, the enable control signal ldo_ok is turned to a high level, the PMOS transistor M5 is turned off, if the feedback signal FB is lower than the reference voltage signal VREF2, the first signal pg_ok is at a low level, the second signal pg_ok2 output by the logic conversion module 122 is at a high level, the NMOS transistor M4 is turned on, the power good signal PG at the terminal 104 is pulled down to a low level, if the feedback signal FB is higher than the reference voltage signal VREF2, the first signal pg_ok is at a high level, the second signal pg_ok2 output by the logic conversion module 122 is at a low level, and the NMOS transistor M3 is turned on at this time, as long as the on-resistance of the NMOS transistors M2 and M3 is guaranteed to be far smaller than the resistance value of the resistor R2, the NMOS transistor M4 is turned off, and the power good signal PG at the terminal 104 is pulled up to a high level by the pull-up resistor Rup.
In summary, the power state detection circuit applied to a DC-DC converter provided by the embodiment of the invention includes a pull-up resistor, a comparator, a logic conversion module and an output module. The pull-up resistor is connected between an output terminal for outputting a power source good signal and a pull-up power source, the comparator is used for comparing a feedback signal of the output voltage of the DC-DC converter with a set reference voltage signal, the logic conversion module is used for carrying out logic conversion on the output signal of the comparator, the output module generates the power source good signal according to an enabling control signal and the output of the logic conversion module, and the output module is configured to output the power source good signal in a corresponding state according to the comparison result of the comparator only when the enabling control signal is valid. Compared with the traditional scheme, the power state detection circuit of the embodiment is not influenced by factors such as stability and rising speed of power voltage in the DC-DC converter, misjudgment can not occur under any power supply condition, and working stability and precision of the power state detection circuit are improved.
It should be noted that although the device is described herein as an N-channel or P-channel device, or an N-type or P-type doped region, it will be appreciated by those of ordinary skill in the art that complementary devices may be implemented in accordance with the present invention. It will be appreciated by those of ordinary skill in the art that conductivity type refers to a mechanism by which electrical conduction occurs, such as by hole or electron conduction, so conductivity type does not relate to doping concentration but rather to doping type, such as P-type or N-type. It will be appreciated by those of ordinary skill in the art that the terms "during", "when" and "when … …" as used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the start of a start-up action, but rather there may be some small but reasonable delay or delays between it and the reaction action (reaction) initiated by the start-up action, such as various transmission delays and the like. The word "about" or "substantially" is used herein to mean that an element value (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation such that the value or position is difficult to strictly assume the stated value. It has been well established in the art that deviations of at least ten percent (10%) (at least twenty percent (10%)) for semiconductor doping concentrations are reasonable deviations from the exact ideal targets described. When used in connection with a signal state, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.
Furthermore, it should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A power state detection circuit for use in a DC-DC converter, comprising:
a pull-up resistor connected between an output terminal for outputting a power good signal and a pull-up power supply;
a comparator configured to compare a feedback signal related to an output voltage of the DC-DC converter with a reference voltage signal to generate a first signal;
a logic conversion module configured to logically convert the first signal to generate a second signal; and
an output module connected between the logic conversion module and the output terminal, configured to generate the power good signal according to an enable control signal and the second signal,
wherein the output module is configured to control a respective state of the power good signal in accordance with a level state of the second signal in response to the enable control signal being active.
2. The power state detection circuit of claim 1, wherein,
the power state detection circuit includes a power state detection circuit in a control circuit of the DC-DC converter,
the control circuit further includes an internal regulator that is enabled when the control circuit receives an enabling signal that is enabled, and the internal regulator generates a stable internal power supply voltage based on an input voltage of the DC-DC converter.
3. The power state detection circuit of claim 2, wherein the pull-up power supply is configured to be connected to an internal power supply voltage of the control circuit or a system external power supply voltage.
4. The power state detection circuit of claim 2, wherein the output terminal comprises a power good terminal or pin of a control circuit of a DC-DC converter formed on an integrated circuit chip.
5. The power state detection circuit of claim 2, wherein the output module comprises:
a first transistor, a first end of which is connected with the second signal, and a control end of which is connected with the enabling control signal;
a first resistor and a second transistor connected in series between the output terminal and the reference ground, a control terminal of the second transistor being connected to a second terminal of the first transistor; and
and a third transistor and a second resistor connected in series between the output terminal and the reference ground, a control terminal of the third transistor being connected to the enable control signal.
6. The power state detection circuit of claim 5, further comprising:
a bias module configured to provide a bias voltage to a control terminal of the second transistor according to the input voltage, the bias module comprising:
a third resistor and a fourth resistor connected in series between the input voltage and the control terminal of the second transistor; and
and the cathode of the diode is connected with a common node of the third resistor and the fourth resistor, and the anode of the diode is connected with the reference ground.
7. The power state detection circuit of claim 6, wherein the second signal and the first signal are mutually inverted signals, the logic conversion module comprising:
a fourth transistor and a fifth transistor connected in series between the internal power supply voltage and a reference ground,
the control ends of the fourth transistor and the fifth transistor are connected with the first signal, and the second end of the fourth transistor and the first end of the fifth transistor are used for outputting the second signal.
8. The power state detection circuit according to claim 7, wherein a resistance value of the fourth resistor is larger than on-resistances of the first transistor and the fifth transistor.
9. The power state detection circuit of claim 7, wherein the first transistor, the second transistor, and the fifth transistor are NMOS transistors, and the third transistor and the fourth transistor are PMOS transistors.
10. A DC-DC converter, comprising:
a control circuit, comprising:
a power input terminal for connecting an input voltage;
an internal regulator connected to the power input terminal and configured to generate an internal power supply voltage from the input voltage when activated;
an enable input terminal for connecting an enable signal;
a schmitt trigger connected to the enable input terminal and configured to activate the internal regulator when the enable signal is active;
a feedback terminal for connecting a feedback signal of the output voltage;
a power good terminal for outputting a power good signal; and
the power state detection circuit of any one of claims 1-9, connected to the feedback terminal and the power good terminal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310664366.8A CN116896271A (en) | 2023-06-06 | 2023-06-06 | Power state detection circuit applied to DC-DC converter and DC-DC converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310664366.8A CN116896271A (en) | 2023-06-06 | 2023-06-06 | Power state detection circuit applied to DC-DC converter and DC-DC converter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117277825A (en) * | 2023-11-22 | 2023-12-22 | 长城电源技术有限公司 | Power failure control circuit, control method and power converter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117277825A (en) * | 2023-11-22 | 2023-12-22 | 长城电源技术有限公司 | Power failure control circuit, control method and power converter |
| CN117277825B (en) * | 2023-11-22 | 2024-01-30 | 长城电源技术有限公司 | Power failure control circuit, control method and power converter |
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