CN118073487A - Epitaxial layer, growth method thereof and light-emitting chip - Google Patents

Abstract

The application relates to an epitaxial layer, a growth method thereof and a light-emitting chip, wherein when at least one of an N-type semiconductor layer and a P-type semiconductor layer is grown, a doping source is pulsed in, an intrinsic sub-layer is grown in a stage where the doping source is not pulsed in one pulse period, and a doping sub-layer is grown in a stage where the doping source is pulsed in, so that doping source atoms can effectively replace basic source atoms, and defect density is reduced while doping concentration is ensured. Meanwhile, the concentration of electrons and holes at the interface is changed due to the structure of the pulse layers, and the current can be effectively expanded through different doped interfaces in the movement process of the electrons and the holes under the action of the current, so that the uniform distribution of the current is greatly improved through multiple current expansion before the electrons and the holes are injected into the active layer. In addition, the periodically grown doping structure can block dislocation and defects of the epitaxial layer, particularly threading dislocation is greatly reduced, a micro-leakage channel is reduced, and the internal quantum efficiency of the epitaxial layer is further improved.

Description

Epitaxial layer, growth method thereof and light-emitting chip

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to an epitaxial layer, a growth method thereof, and a light emitting chip.

Background

An LED (LIGHT EMITTING Diode) is a semiconductor solid light emitting device, which uses a semiconductor PN junction as a light emitting material, and can directly convert electricity into light, and has the advantages of small volume, high brightness, low power consumption, long service life, and the like, and has been widely used in industries of display, illumination, medical treatment, and the like. At present, researches on epitaxial materials are never interrupted, so that excellent epitaxial materials such as GaN (gallium nitride) and the like are discovered, the quality of an epitaxial layer determines the quality of an LED chip, the internal quantum efficiency of the epitaxial layer can be directly influenced by the defect density in the epitaxial layer, and therefore, how to reduce the epitaxial defects in the epitaxial layer, improve the internal quantum efficiency of the epitaxial layer and enhance the quality of the LED chip is a problem to be solved urgently.

Disclosure of Invention

In view of the above-mentioned shortcomings of the related art, an object of the present application is to provide an epitaxial layer, a growth method thereof, and a light emitting chip, which are aimed at reducing epitaxial defects in the epitaxial layer and improving internal quantum efficiency thereof.

The application first provides an epitaxial layer comprising:

an N-type semiconductor layer;

a P-type semiconductor layer; and

An active layer between the N-type semiconductor layer and the P-type semiconductor layer;

At least one of the N-type semiconductor layer and the P-type semiconductor layer is provided with a plurality of pulse layers, and each pulse layer is composed of an unintentionally doped intrinsic sub-layer and a doped sub-layer which is arranged on the same intrinsic sub-layer.

In the epitaxial layer, at least one of the N-type semiconductor layer and the P-type semiconductor layer is provided with a plurality of stacked pulse layers, each pulse layer is composed of an unintentionally doped intrinsic sub-layer and a doped sub-layer stacked with the intrinsic sub-layer, so that when at least one of the N-type semiconductor layer and the P-type semiconductor layer is grown, a doping source is pulsed in, the intrinsic sub-layer is grown in a stage where the doping source is not in a pulse period, and the doping sub-layer is grown in a stage where the doping source is in, thereby being beneficial to effectively replacing basic source atoms by doping source atoms, and reducing defect density while ensuring doping concentration. Meanwhile, the concentration of electrons and holes at the interface is changed due to the structure of the multiple pulse layers, and the current can be effectively expanded through different doped interfaces in the process of moving the electrons and the holes under the action of the current, and then the current is redistributed and expanded after passing through the next doped interface. The current spreading is performed for a plurality of times before the electrons and the holes are injected into the active layer, so that the uniform distribution of the current can be greatly improved. In addition, the periodically grown doping structure can block dislocation and defects of the epitaxial layer, particularly threading dislocation is greatly reduced, a micro-leakage channel is reduced, and the internal quantum efficiency of the epitaxial layer is further improved.

Optionally, a pulse layer has a thickness of 7-30 nm, wherein the doped sub-layer has a thickness of 5-20 nm and the intrinsic sub-layer has a thickness of 2-10 nm.

Optionally, the thickness of the N-type semiconductor layer is 1-5 um, and the thickness of the P-type semiconductor layer is 100-300 nm.

Optionally, a direction from the N-type semiconductor layer to the P-type semiconductor layer is a growth direction of the epitaxial layer; along the growth direction, the doping concentration of the P-type semiconductor layer gradually increases.

In the epitaxial layer, the doping concentration of the P-type semiconductor layer is gradually increased along the growth direction, so that the doping concentration of one side of the P-type semiconductor layer, which is close to the active layer, is lower, the lattice mismatch between the P-type semiconductor layer and the active layer is reduced, and the quality of the epitaxial layer is enhanced. At the same time, the doping concentration of the P-type semiconductor layer gradually increases along the growth direction, which increases the doping concentration of the P-type semiconductor layer.

Optionally, the P-type semiconductor layer includes a plurality of third step ladder layers, the P-type doping concentration of each third step ladder layer increases in a gradient manner along the growth direction, a third step ladder layer includes a plurality of pulse layers, and the P-type doping concentration of each doping sub-layer in the same third step ladder layer is the same.

In the epitaxial layer, the P-type semiconductor layer comprises a plurality of third-order ladder layers, the P-type doping concentration of each third-order ladder layer is increased in a gradient mode, and the current expansion effect is enhanced by different doping interfaces, so that the recombination probability of electrons and holes of the epitaxial layer is improved, and the light emitting uniformity of the epitaxial layer is also improved.

Optionally, a direction from the N-type semiconductor layer to the P-type semiconductor layer is a growth direction of the epitaxial layer, and along the growth direction, the N-type semiconductor layer sequentially includes:

A lower layer of gradually increasing N-type doping concentration; and

And an upper layer with gradually reduced N-type doping concentration, wherein the maximum value of the N-type doping concentration in the upper layer is smaller than or equal to the maximum value of the N-type doping concentration in the lower layer.

In the epitaxial layer, the N-type semiconductor layer comprises a lower layer with gradually increased N-type doping concentration and an upper layer with gradually reduced N-type doping concentration, so that when the N-type semiconductor layer is grown, the doping concentration is gradually increased and then gradually reduced, the high doping of the N-type semiconductor layer can be ensured, the lattice mismatch between the N-type semiconductor layer and the active layer can be reduced, and the epitaxial defect can be reduced.

Optionally, the N-type doping concentration of at least one of the lower layer and the upper layer is graded.

Optionally, the lower layer includes a plurality of first step ladder layers, the N-type doping concentration of each first step ladder layer increases in a gradient manner along the growth direction, a first step ladder layer includes a plurality of pulse layers, and the N-type doping concentration of each doping sub-layer in the same first step ladder layer is the same;

The upper layer comprises a plurality of second step-down layers, the N-type doping concentration of each second step-down layer is reduced in a gradient manner along the growth direction, one second step-down layer comprises a plurality of pulse layers, and the N-type doping concentration of each doping sub-layer in the same second step-down layer is the same.

In the epitaxial layer, the lower part layer comprises a plurality of first step ladder layers, and the N-type doping concentration of each first step ladder layer is increased in a gradient manner; the upper part layer comprises a plurality of second step ladder layers, the N-type doping concentration gradient of each second step ladder layer is reduced, and the current expansion effect is enhanced by different doping interfaces, so that the recombination probability of electrons and holes of the epitaxial layer is improved, and the light emitting uniformity of the epitaxial layer is also improved.

Based on the same inventive concept, the present application also provides a light emitting chip including:

an epitaxial layer of any of the preceding claims;

An N electrode electrically connected with the N-type semiconductor layer in the epitaxial layer; and

And a P electrode electrically connected with the P-type semiconductor layer in the epitaxial layer.

In the epitaxial layer of the light emitting chip, at least one of the N-type semiconductor layer and the P-type semiconductor layer is provided with a plurality of stacked pulse layers, each pulse layer is composed of an unintentionally doped intrinsic sub-layer and a doped sub-layer arranged on the same layer as the intrinsic sub-layer, so that when at least one of the N-type semiconductor layer and the P-type semiconductor layer is grown, the intrinsic sub-layer is grown in a pulse period in which the doping source is not introduced, and the doped sub-layer is grown in a doping source introduction stage, thereby being beneficial to effectively replacing basic source atoms by doping source atoms, and reducing defect density while ensuring doping concentration. Meanwhile, the concentration of electrons and holes at the interface is changed due to the structure of the multiple pulse layers, and the current can be effectively expanded through different doped interfaces in the process of moving the electrons and the holes under the action of the current, and then the current is redistributed and expanded after passing through the next doped interface. The current spreading is performed for a plurality of times before the electrons and the holes are injected into the active layer, so that the uniform distribution of the current can be greatly improved. In addition, the periodically grown doping structure can block dislocation and defects of the epitaxial layer, particularly threading dislocation is greatly reduced, a micro-leakage channel is reduced, and the internal quantum efficiency of the light-emitting chip is further improved.

Based on the same inventive concept, the present application also provides an epitaxial layer growth method applied to the growth of an epitaxial layer as in any one of the preceding claims, the epitaxial layer growth method comprising:

Growing an N-type semiconductor layer;

Growing an active layer;

Growing a P-type semiconductor layer;

At least one of the N-type semiconductor layer and the P-type semiconductor layer grows for a plurality of periods in a pulse growth mode, wherein the pulse growth mode comprises the following steps:

growing an unintentionally doped intrinsic sub-layer;

A doped sub-layer is produced over the intrinsic sub-layer.

In the epitaxial layer growth method, when at least one of the N-type semiconductor layer and the P-type semiconductor layer is grown, the doping source is pulsed in, the intrinsic sub-layer is grown in a stage where the doping source is not pulsed in one pulse period, and the doping sub-layer is grown in a stage where the doping source is pulsed in, so that the doping source atoms can effectively replace basic source atoms, and the defect density is reduced while the doping concentration is ensured. Meanwhile, the concentration of electrons and holes at the interface is changed due to the structure of the multiple pulse layers, and the current can be effectively expanded through different doped interfaces in the process of moving the electrons and the holes under the action of the current, and then the current is redistributed and expanded after passing through the next doped interface. The current spreading is performed for a plurality of times before the electrons and the holes are injected into the active layer, so that the uniform distribution of the current can be greatly improved. In addition, the periodically grown doping structure can block dislocation and defects of the epitaxial layer, particularly threading dislocation is greatly reduced, a micro-leakage channel is reduced, and the internal quantum efficiency of the epitaxial layer is further improved.

Drawings

FIG. 1 is a schematic diagram of an epitaxial layer provided in an alternative embodiment of the present application;

FIG. 2 is a schematic flow chart of an epitaxial layer growth method according to an alternative embodiment of the present application;

FIG. 3 is a schematic diagram of an N-type semiconductor layer or a P-type semiconductor layer according to an alternative embodiment of the present application;

FIG. 4 is a schematic diagram of a pulsed feed dopant source provided in an alternative embodiment of the application;

FIG. 5 is a timing diagram illustrating the introduction of an N-type dopant source into a reaction chamber according to an alternative embodiment of the present application;

FIG. 6 is a timing diagram illustrating the introduction of a P-type dopant source into a reaction chamber according to an alternative embodiment of the present application;

FIG. 7 is a schematic diagram of a light emitting chip according to an alternative embodiment of the present application;

Fig. 8 is a schematic view of an epitaxial layer provided in another alternative embodiment of the present application;

FIG. 9 is a schematic flow chart of an epitaxial layer growth method according to another alternative embodiment of the present application;

FIG. 10 is a timing diagram of the introduction of Si dopant sources into a reaction chamber according to an alternative embodiment of the present application;

FIG. 11 is a timing diagram illustrating the introduction of a Mg dopant source into a reaction chamber in accordance with an alternative embodiment of the present application.

Reference numerals illustrate:

10-an epitaxial layer; 100-pulse layer; 101-an intrinsic sub-layer; 102-doping the sub-layer; an 11-N type semiconductor layer; 111-first order ladder layer; 112-second ladder level; 12-an active layer; a 13-P type semiconductor layer; 131-third order ladder layers; 70-a light emitting chip; 71-N electrode; a 72-P electrode; 80-an epitaxial layer; 81-a buffer layer; 82-an unintentionally doped layer; 83-N type GaN layer; 84-a stress release layer; 85-an active layer; 86-electron blocking layer; 87-P type GaN layer; 88-P type contact layer.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the application. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

In recent years, the LED display industry is undergoing one-time technical innovation, the distance between LED display screens is smaller and smaller, the Micro-distance era is gradually entered, and the Mini-LED (sub-millimeter light emitting diode) and Micro-LED (Micro-scale light emitting diode) display markets enter the burst period. Applications of Micro-LEDs have been extended from flat panel displays to AR (Augmented Reality )/VR (Virtual Reality)/MR (Mixed Reality), spatial displays, flexible transparent displays. It is well known that the light-emitting brightness of an epitaxial layer is determined by photons emitted by holes and electrons after recombination in an active layer, and the light efficiency of an LED chip under a small current density is directly restricted by defects in an epitaxial structure.

Based on this, the present application is intended to provide a solution to the above technical problem, the details of which will be described in the following examples.

An alternative embodiment of the application:

The present application first provides an epitaxial layer 10, please refer to a schematic structural diagram of the epitaxial layer 10 shown in fig. 1:

The epitaxial layer 10 includes an N-type semiconductor layer 11, an active layer 12 and a P-type semiconductor layer 13, which are sequentially stacked, wherein the N-type semiconductor layer 11 is an N-type doped semiconductor layer, and the P-type semiconductor layer 13 is a P-type doped semiconductor layer. The N-type semiconductor layer 11 and the P-type semiconductor layer 13 are configured to inject electrons and holes into the active layer 12, respectively, under excitation of a current, and the electrons and holes recombine in the active layer 12 and radiate photons. It will be appreciated by those skilled in the art that the above three layer structures are merely basic layer structures of the epitaxial layer 10, and in fact, one or several other layer structures may be further included in the epitaxial layer 10, for example, a buffer layer may be further included in the epitaxial layer 10, which is disposed on a side of the N-type semiconductor layer 11 remote from the active layer 12; for example, an electron blocking layer may be included in the epitaxial layer 10, which is disposed between the active layer 12 and the P-type semiconductor layer 13; for another example, one or more transition layers may be included in epitaxial layer 10 to achieve a transition in growth temperature, a transition in growth pressure, a transition in lattice, or the like.

N-type doping is typically achieved by Si (silicon) doping, such as SiH ₄ (monosilane), or Si ₂H₆ (disilane), any of a B (boron) source and a Ge (germanium) source in addition to the Si source may also be achieved. The P-type dopant source includes at least one of a Mg (magnesium) source, a Zn (zinc) source, such as Cp ₂ Mg (magnesium-dicyclopentadiene), and the like. GaN-based LEDs are the leading edge and hot spot of the current optoelectronic field and industry, and GaN-based Lan Luguang LEDs have advantages of small volume, long lifetime, low power consumption, high brightness, easy integration, etc., so in some examples of this embodiment, the epitaxial layer 10 is a GaN-based material, and the N-type semiconductor layer 11 and the P-type semiconductor layer 13 are an N-type GaN layer and a P-type GaN layer, respectively. In other examples of this embodiment, the epitaxial layer 10 may also be a GaAs-based material or an AlGaInP (aluminum gallium indium phosphorus) -based material.

In some examples of the present embodiment, the thickness of the N-type semiconductor layer 11 is 1 to 5um, for example, may be 1um, 1.3um, 2um, 3.4um, 4um, 4.5um, 5um, or the like. The thickness of the P-type semiconductor layer 13 is 100-300 nm, for example, in one example, the thickness of the P-type semiconductor layer 13 is 100nm, in another example, the thickness of the P-type semiconductor layer 13 is 300nm, in yet another example, the thickness of the P-type semiconductor layer 13 may be 200nm, and in addition, in other examples, the thickness of the P-type semiconductor layer 13 may take other values in the epitaxial layer 10 provided in other examples, including, but not limited to, 123nm, 150nm, 189nm, 240nm, 277nm, and the like.

The embodiment also provides an epitaxial layer growth method, please refer to a flow chart of the epitaxial layer growth method shown in fig. 2:

S202: and growing an N-type semiconductor layer.

The epitaxial layer 10 generally includes a growth substrate on which the N-type semiconductor layer 11 may be grown, and the growth substrate of the epitaxial layer 10 may include, for example, a GaN-based epitaxial layer, but is not limited to, any one of a sapphire substrate, a Si substrate, a GaN substrate, and the like. If epitaxial layer 10 is predominantly GaAs (gallium arsenide) material, the growth substrate may include, but is not limited to, a GaAs substrate. In addition, since the lattice constants between the N-type semiconductor layer 11 and the growth substrate are greatly different, the direct growth of the N-type semiconductor layer 11 on the growth substrate may result in a high defect density in the epitaxial layer 10, so in some examples of this embodiment, a buffer layer or other layer structure may be grown on the growth substrate before the growth of the N-type semiconductor layer 11, so as to achieve transition of the lattice constants, and then an N-type doping source is introduced into the reaction chamber, so as to achieve growth of the N-type semiconductor layer 11, thereby ensuring crystal quality of the N-type semiconductor layer 11, and thus, in some examples of this embodiment, the N-type semiconductor layer 11 may be grown on the buffer layer.

S204: an active layer is grown.

After the growth of the N-type semiconductor layer 11 is completed, the active layer 12 may be grown directly on the N-type semiconductor layer 11; in other examples of the present embodiment, other layer structures may be grown on the N-type semiconductor layer 11 first, and then the active layer 12 may be grown. If the epitaxial layer 10 is made of GaN, the active layer 12 may be an InGaN (indium gallium nitride)/GaN quantum well layer.

S206: and growing a P-type semiconductor layer.

After the growth of the active layer 12 is completed, a P-type doping source may be introduced into the reaction chamber to grow a P-type semiconductor layer 13, and in some examples of this embodiment, the P-type semiconductor layer 13 may be directly grown on the active layer 12; in other examples, other layer structures, such as an electron blocking layer, etc., may also be grown between the active layer 12 and the P-type semiconductor layer 13.

In this embodiment, at least one of the N-type semiconductor layer 11 and the P-type semiconductor layer 13 has a plurality of pulse layers 100 stacked and arranged therein, please refer to fig. 3: each pulse layer 100 is composed of an intrinsic sub-layer 101 and a doped sub-layer 102. It is clear that the doped sub-layer 102 is a sub-layer containing dopant source atoms, whereas the intrinsic sub-layer 101 is an unintentional doped layer, in which case the intrinsic sub-layer 101 does not contain dopant source atoms. During the epitaxial growth of the epitaxial layer 10 by the process such as MOCVD (Metal-organic Chemical Vapor Deposition, metal organic chemical vapor deposition), a doping source is introduced into the reaction chamber when the doped sub-layer 102 is grown, for example, if the N-type semiconductor layer 11 includes a plurality of pulse layers 100, a Si source is introduced into the reaction chamber when the doped sub-layer 102 of the N-type semiconductor layer 11 is grown; if the P-type semiconductor layer 13 includes a plurality of pulse layers 100, a Mg source is introduced into the reaction chamber when the doped sub-layer 102 of the P-type semiconductor layer 13 is grown. Correspondingly, when the intrinsic sub-layer 101 is grown, no corresponding dopant is introduced into the reaction chamber. Since the plurality of pulse layers 100 are stacked, the doped sub-layers 102 and the intrinsic sub-layers 101 are alternately stacked, and when the plurality of pulse layers 100 are grown, a basic source (for example, a GaN-based epitaxial layer, the basic source includes Ga (gallium) and N (nitrogen) sources) is always introduced, but the doped source is introduced in a pulse manner: during one pulse period, the dopant source is not turned on for a period of time to grow the intrinsic sub-layer 101, and the dopant source is turned on for the remaining period of time to grow the doped sub-layer 102, as shown in fig. 4.

In some examples of this embodiment, the N-type semiconductor layer 11 is grown by pulsing the dopant source so that the intrinsic sub-layer 101 and the N-type doped sub-layer 102 in the N-type semiconductor layer 11 are alternately stacked for multiple cycles. In other examples of this embodiment, the P-type semiconductor layer 13 is grown by pulsing the dopant source so that the intrinsic sub-layer 101 and the P-type doped sub-layer 102 of the P-type semiconductor layer 13 are alternately stacked for multiple cycles. In still other examples, both the N-type semiconductor layer 11 and the P-type semiconductor layer 13 are grown by pulsing the dopant sources.

In some examples of this embodiment, the thickness of the doped sub-layer 102 is 5-20 nm, for example, in examples, the thickness of the doped sub-layer 102 is 5nm, in one example, the thickness of the doped sub-layer 102 is 7nm, in one example, the thickness of the doped sub-layer 102 is 10nm, and in still other examples, the thickness of the doped sub-layer 102 may be 11nm, 14nm, 17nm, 19nm, or 20nm. In some examples of this embodiment, the thickness of the intrinsic sub-layer 101 is 2-10 nm, for example, in examples, the thickness of the intrinsic sub-layer 101 is 2nm, in one example, the thickness of the intrinsic sub-layer 101 is 4nm, in one example, the thickness of the intrinsic sub-layer 101 is 5nm, and in still other examples, the thickness of the intrinsic sub-layer 101 may be 6nm, 8nm, 9.5nm, 10nm. The thickness of the pulse layer 100 is the sum of the thicknesses of the intrinsic sub-layer 101 and the doped sub-layer 102, so the thickness of the pulse layer 100 is 7 to 30nm, for example, 7nm, 10nm, 17nm, 23nm, 30nm, or the like.

In some examples of the present embodiment, the doping concentrations of the doped sublayers 102 of the N-type semiconductor layer 11 or the P-type semiconductor layer 13 are uniform, that is, if the N-type semiconductor layer 11 is grown by pulse-feeding the doping source, the doping concentrations of the doped sublayers 102 in the pulse layers 100 in the N-type semiconductor layer 11 are the same; if the P-type semiconductor layer 13 is grown by pulse-feeding a dopant source, the dopant concentration of the dopant sub-layer 102 in each pulse layer 100 in the P-type semiconductor layer 13 is also the same.

In other examples, in the case where the N-type semiconductor layer 11 is grown by pulse-type doping source, the N-type doping concentrations of the doping sub-layers 102 in each pulse layer 100 are different, for example, in some examples, the N-type semiconductor layer 11 has twelve pulse layers 100, and thus twelve doping sub-layers 102, where the doping concentrations of the doping sub-layers 102 may be completely different, or may be partially the same, for example, the doping concentrations of the first four doping sub-layers 102 are the same along the growth direction, and are all the first N-type doping concentrations; the doping concentrations of the middle four doping sublayers 102 are the same and are all the second N-type doping concentrations; the last four doped sublayers 102 have the same doping concentration and are of a third N-type doping concentration.

In some examples of the present embodiment, the N-type semiconductor layer 11 includes a lower layer and an upper layer, which are stacked along the growth direction, and it is understood that the "lower layer" and the "upper layer" are merely divisions according to the spatial positions of the portions in the N-type semiconductor layer 11, wherein the lower layer is farther from the active layer 12 than the upper layer. In this embodiment, along the growth direction, the N-type doping concentration of the lower layer gradually increases, while the N-type doping concentration of the upper layer gradually decreases, and the maximum value of the N-type doping concentration in the upper layer is equal to or less than the maximum value of the N-type doping concentration in the lower layer. Therefore, when the N-type semiconductor layer 11 is grown, the doping source is introduced into the reaction chamber gradually increases and then gradually decreases, and it is understood by those skilled in the art that the control of the doping source introduction can be achieved by adjusting at least one of the concentration and the flow rate of the doping source. It should be appreciated that, when the N-type semiconductor layer 11 is grown, the increasing and decreasing of the doping concentration is beneficial to reducing the lattice mismatch between the N-type semiconductor layer 11 and the layer structures (including the active layer 12) on both sides of the N-type semiconductor layer 11 and the inside of the N-type semiconductor layer 11 while realizing high doping of the N-type semiconductor layer 11, and reducing the defect density in the epitaxial layer 10, thereby improving the internal quantum efficiency of the epitaxial layer 10.

In some examples of this embodiment, the N-type doping concentration of at least one of the lower layer and the upper layer is varied in a gradient, e.g., in one example, the N-type doping concentration of the lower layer is increased in an arithmetic progression and the N-type doping concentration of the upper layer is decreased in an arithmetic progression. In still other examples, the N-type doping concentration of the lower layer or the upper layer does not change in an arithmetic progression, e.g., in the lower layer, the N-type doping concentration has no law other than a gradual increase; for example, in the lower layer, the N-type doping concentration does not have any change rule except for gradually increasing. In some examples of the present embodiment, the growth of the N-type semiconductor layer 11 not only follows the principle of increasing the N-type doping concentration and then decreasing, but also grows by pulse-feeding the doping source: in some examples of this embodiment, the lower layer of the N-type semiconductor layer 11 includes a plurality of first step ladder layers 111, and the doping concentration of each first step ladder layer 111 increases in a gradient manner along the growth direction of the epitaxial layer 10, as shown in fig. 5, one first step ladder layer 111 includes a plurality of pulse layers 100, and the N-type doping concentration of the doping sub-layer 102 in each pulse layer 100 belonging to the same first step ladder layer 111 is the same. For example, under the condition that the doping source inlet concentration (c) is unchanged, when growing the lower layer, an N-type doping source can be firstly introduced into the reaction chamber in a pulse mode according to the doping source inlet flow f ₁₁ so as to grow a plurality of pulse layers 100 to form a first step ladder layer 111; then, an N-type doping source is pulsed into the reaction chamber according to the flow f ₁₂ to grow a plurality of pulse layers 100, and finally, an N-type doping source is pulsed into the reaction chamber according to the flow f _1n to grow a plurality of pulse layers 100, wherein f ₁₁＜f₁₂＜…＜f_1n is the nth first step ladder layer 111, so that the N-type doping concentration corresponding to the N first step ladder layers 111 in the lower layer is increased stepwise.

In other examples of this embodiment, the upper layer of the N-type semiconductor layer 11 includes a plurality of second step ladder layers 112, and the doping concentration of each second step ladder layer 112 is reduced in a gradient manner along the growth direction of the epitaxial layer 10, and referring to fig. 5, one second step ladder layer 112 includes a plurality of pulse layers 100, and the N-type doping concentration of the doping sub-layer 102 in each pulse layer 100 belonging to the same second step ladder layer 112 is the same. Continuing to assume that the doping source inlet concentration (c) is unchanged, when growing the upper part of the layer, firstly, introducing an N-type doping source into the reaction chamber in a pulse mode according to the doping source inlet flow f ₂₁ so as to grow a plurality of pulse layers 100 to form a second step ladder layer 112; then, an N-type doping source is pulsed into the reaction chamber according to the flow f ₂₂ to grow a plurality of pulse layers 100, and finally, an N-type doping source is pulsed into the reaction chamber according to the flow f _2m to grow a plurality of pulse layers 100, wherein f ₂₁＞f₂₂＞…＞f_2m is the mth second step ladder layer 112, so that the N-type doping concentration corresponding to the m second step ladder layers 112 in the upper layer is reduced stepwise.

It will be understood by those skilled in the art that, in the example corresponding to fig. 5, the upper portion layer and the lower portion layer of the N-type semiconductor layer 11 are both grown by pulse-type doping sources, and the N-type doping concentration is changed stepwise, but in other examples of this embodiment, only one of the upper portion layer and the lower portion layer may be grown in this manner, and the other may not be grown in this manner, for example, one of the lower portion layer and the upper portion layer is grown by pulse-type doping sources, and the other is grown by continuous doping sources; the N-type doping concentration of one of the lower layer and the upper layer is stepwise varied, and the N-type doping concentration of the other is linearly varied. In the above example, the N-type semiconductor layer 11 is grown while keeping the N-type doping source concentration (c) constant, and the flow rate (f) of the N-type doping source is adjusted in a gradient manner, thereby realizing a gradient change in the N-type doping concentration; in other examples, the N-type doping source inlet flow rate may be kept unchanged, and the N-type doping source concentration may be adjusted in a gradient manner, so as to realize the gradient change of the N-type doping concentration. In still other examples, the N-type dopant source may be varied in a gradient manner in both the flow rate and the dopant source concentration.

In some examples of this embodiment, the P-type semiconductor layer 13 is grown by pulse-type doping source, where the P-type doping concentrations of the doping sub-layers 102 in each pulse layer 100 are different, for example, in some examples, the P-type semiconductor layer 13 has nine pulse layers 100, so that there are nine doping sub-layers 102, where the doping concentrations of the doping sub-layers 102 may be completely different, or may be partially different, and partially the same, for example, the doping concentrations of the first three doping sub-layers 102 are the same along the growth direction, and are all the first P-type doping concentrations; the doping concentrations of the middle three doping sublayers 102 are the same and are all the second P-type doping concentrations; the last three doped sublayers 102 have the same doping concentration and are of a third P-type doping concentration.

In some examples of the present embodiment, the P-type doping concentration of the P-type semiconductor layer 13 gradually increases along the growth direction, so that the doping concentration of the P-type semiconductor layer 13 on the side close to the active layer 12 is relatively low, and the P-type doping concentration on the side far from the active layer 12 is relatively high, which can not only increase the doping concentration of the P-type semiconductor layer 13, but also reduce crystal defects caused by lattice mismatch in a manner of gradual doping concentration change.

In some examples of the present embodiment, the P-type doping concentration of the P-type semiconductor layer 13 varies linearly, and in other examples, the P-type doping concentration of the P-type semiconductor layer 13 varies in a gradient manner. For example, referring to fig. 6, in some examples of the present embodiment, the P-type semiconductor layer 13 includes a plurality of third step ladder layers 131, the P-type doping concentration of each third step ladder layer 131 increases in a gradient manner along the growth direction of the epitaxial layer 10, a third step ladder layer 131 includes a plurality of pulse layers 100, and the P-type doping concentrations of the doping sub-layers 102 in each pulse layer 100 belonging to the same third step ladder layer 131 are the same. Assuming that the doping source inlet flow (f) is unchanged, when growing the upper part layer, a P-type doping source can be firstly introduced into the reaction chamber in a pulse mode according to the doping source concentration c ₃₁ so as to grow a plurality of pulse layers 100 to form a third-order ladder layer 131; then, a P-type doping source is pulsed into the reaction chamber according to the doping source concentration c ₃₂ to grow a plurality of pulse layers 100, and finally, a P-type doping source is pulsed into the reaction chamber according to the doping source concentration c _3k to grow a plurality of pulse layers 100, wherein c ₃₁＜c₂＜…＜c_3k is the kth third step ladder layer 131, so that the P-type doping concentration corresponding to the k third step ladder layers 131 in the P-type semiconductor layer 13 increases stepwise.

In the above example, the P-type semiconductor layer 13 is grown while keeping the dopant flux, such as the flow rate (f), unchanged, and the P-type dopant concentration (c) is adjusted in a gradient manner, thereby realizing a gradient change in the P-type dopant concentration; in other examples, the P-type doping source concentration may be adjusted in a gradient manner while the P-type doping source concentration inlet flow is kept unchanged, so as to realize the gradient change of the P-type doping concentration. In still other examples, the P-type dopant source may be varied in a gradient manner in both the flow rate and the dopant source concentration.

It is understood that the change of the N-type doping concentration in the N-type semiconductor layer 11 or the change of the P-type doping concentration in the P-type semiconductor layer 13 may also be a linear change, for example, in the epitaxial layer 10 provided in an example, the N-type semiconductor layer 11 is grown by pulse-type doping source, and the N-type doping concentration of the N-type semiconductor layer 11 is gradually increased along the growth direction, and then gradually decreased. Meanwhile, in the epitaxial layer 10, when the P-type semiconductor layer 13 is grown, the P-type doping source is always introduced, and the introduced amount of the P-type doping source gradually increases with the progress of the growth.

In some examples of this embodiment, the N-type doping concentration of the doped sub-layer 102 in the N-type semiconductor layer 11 is greater than 5E18cm ^-3. The P-type doping concentration of the doped sub-layer 102 in the P-type semiconductor layer 13 is greater than 1E19cm ^-3.

The present embodiment further provides a light emitting chip 70, please refer to a schematic structural diagram of the light emitting chip 70 shown in fig. 7: the light emitting chip 70 includes the epitaxial layer 10 provided in any one of the foregoing examples, and further includes a chip electrode including an N electrode 71 electrically connected to the N-type semiconductor layer 11 in the epitaxial layer 10, and a P electrode 72 electrically connected to the P-type semiconductor layer 13 in the epitaxial layer 10. It should be understood by those skilled in the art that the N-electrode 71 and the P-electrode 72 are not necessarily directly connected to the N-type semiconductor layer 11 and the P-type semiconductor layer 13, and in some examples of the present embodiment, the N-electrode 71 may be disposed on a buffer layer and electrically connected to the N-type semiconductor layer 11 through the buffer layer; in some examples, the P electrode 72 may be disposed on the current spreading layer by being electrically connected with the P-type semiconductor layer 13. In the present embodiment, the structure, color and size of the light emitting chip 70 are not particularly limited, for example, the light emitting chip 70 may be a flip-chip structure, a front-mounted structure or a vertical structure; the light emitting chip 70 may be a blue light chip or a green light chip or a red light chip; the light emitting chip 70 may be a Micro-LED chip, a Mini-LED chip, or even a general LED chip having a size larger than the Mini-LED chip.

According to the epitaxial layer and the light-emitting chip provided by the embodiment, at least one of the N-type semiconductor layer and the P-type semiconductor layer is grown in a pulse doping source introduction mode, and the pulse doping source pulse doping is used for forming a pulse layer composed of the intrinsic sub-layer and the doped sub-layer, so that doping source atoms can orderly replace basic source atoms, and defect density in an epitaxial crystal is reduced. Meanwhile, the N-type semiconductor layer or the P-type semiconductor layer formed by pulse-type doping sources is of a structure that an intrinsic sub-layer and a doped sub-layer are alternately laminated for a plurality of periods, and a plurality of interfaces are formed in the N-type semiconductor layer or the P-type semiconductor layer due to different doping concentrations, so that the interfaces can be subjected to current expansion continuously, uniform distribution of carriers is realized, and further the recombination probability of the carriers in the epitaxial layer and the uniformity of light emission of the epitaxial layer are improved. Moreover, the periodic doping structure can block dislocation and defects of the epitaxial layer, so that threading dislocation is greatly reduced, and micro-leakage channels are also reduced.

Another alternative embodiment of the application:

In order to make the structure and advantages of the epitaxial layer provided in the foregoing embodiments more apparent to those skilled in the art, the present embodiment will be further described with reference to the examples:

In this embodiment, the epitaxial layer 80 is a GaN-based epitaxial layer, and please refer to the schematic structure of the epitaxial layer shown in fig. 8:

The epitaxial layer 80 includes a buffer layer 81, an unintentionally doped layer 82, an N-type GaN layer 83, a Stress Relief Layer (SRL) 84, an active layer 85, an electron blocking layer 86, a P-type GaN layer 87, and a P-type contact layer 88 in this order along the growth direction thereof.

The growth preparation process of the epitaxial layer 80 is further described below with reference to the growth flow diagram of the epitaxial layer 80 shown in fig. 9:

s902: a buffer layer is grown on the growth substrate.

In the present embodiment, the growth substrate is selected from a sapphire substrate, but in other embodiments, a Si substrate or a GaN substrate may be used instead of the sapphire substrate.

The buffer layer 81 may be a low temperature GaN/AlN (aluminum nitride) layer including a GaN layer and an AlN layer stacked in the low temperature GaN/AlN (aluminum nitride) layer. When growing the GaN layer, introducing a Ga source and an N source into the reaction chamber through carrier gas, wherein the Ga source can be at least one of TMGa (trimethylgallium) and TEGa (triethylgallium); the N source is NH ₃ (ammonia). When growing the AlN layer, an Al source and an N source may be introduced into the reaction chamber by a carrier gas, wherein the Al source may include, but is not limited to, at least one of TMAL (trimethylaluminum) and TEAL (triethylaluminum). The carrier gas may be H ₂ (hydrogen) or N ₂ (nitrogen).

S904: an unintentionally doped layer is grown on the buffer layer.

After the buffer layer 81 is grown, the Ga source and the N source may be introduced into the reaction chamber to grow the undoped layer 82, and the undoped layer 82 is ideally an undoped GaN layer. The growth temperature of the unintentionally doped layer 82 is relatively high, exceeding the growth temperature of the buffer layer 81.

S906: and growing an N-type GaN layer on the unintentionally doped layer.

After the unintentionally doped layer 82 is grown, an N-type doped GaN layer, i.e., an N-type GaN layer 83, may be grown at a high temperature. In this embodiment, the doping source of the N-type doping is Si, and for example, at least one of monosilane and disilane may be used as the Si source.

In this embodiment, when the N-type GaN layer 83 is grown, the Si source may be introduced into the reaction chamber according to the Si source introduction timing chart shown in fig. 10, and the basic source (including the Ga source and the N source) may be continuously and uniformly introduced. From the timing diagram of fig. 10, the Si source is pulsed, and the pulse height is first increased in a gradient manner, and then decreased in a gradient manner: in the first growth stage of the N-type GaN layer 83, the Si doping source which is pulsed and gradient-raised is beneficial to replacing Ga atomic sites of doping atoms Si in the material in order and slowly changing, so that the doping concentration is effectively improved and the defect density is reduced. In the second growth stage of the N-type GaN layer 83, the doping concentration of the Si doping source is reduced in a gradient manner along the direction away from the active layer 85, and the Si doping source is introduced in a pulse manner, so that the crystallization quality of the active layer 85 is improved, and the electron-hole recombination probability is improved.

S908: and growing a stress release layer on the N-type GaN layer.

S910: an active layer is grown on the stress relief layer.

In this embodiment, the active layer 85 is an InGaN/GaN multiple quantum well layer, in which the GaN layer is a barrier layer and the InGaN layer is a potential well layer, and the barrier layer and the potential well layer are alternately stacked for a plurality of periods to form a multiple quantum well.

S912: an electron blocking layer is grown on the active layer.

S914: and growing a P-type GaN layer on the electron blocking layer.

In this embodiment, mg source introduction may be performed into the reaction chamber according to the Mg source introduction timing chart shown in fig. 11 when the P-type GaN layer 87 is grown, and the basic source (including Ga source and N source) may be continuously and uniformly introduced. As can be seen from the timing chart of fig. 11, the Mg source was pulsed, and the pulse height gradient increased as the growth proceeded.

S916: and growing a P-type contact layer on the P-type GaN layer.

S918: and (5) annealing treatment is carried out in a nitrogen atmosphere.

It will be appreciated by those skilled in the art that the pulsed graded doping structure is capable of varying the concentration of electrons and holes at the interface, and that electrons and holes can be laterally expanded by moving through different doping interfaces under the influence of current, and then redistributed to expand as they pass through the next doping interface. The uniformity of current distribution can be greatly improved through multiple current spreading before electrons and holes are injected into the active layer 85.

Meanwhile, the periodically grown doping structure enables dislocation and defects to be blocked in the growth process of epitaxy, particularly threading dislocation is greatly reduced, and micro-leakage channels are reduced. And the doping concentration is lower at the position close to the active layer 85, so that the defect density in the epitaxial crystal is greatly reduced, the growth quality of the epitaxial layer 80 is improved, the generation of a non-radiative recombination center is reduced, and the luminous efficiency under the low current density is improved.

It is to be understood that the application is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.

Claims (10)

1. An epitaxial layer, comprising:

an N-type semiconductor layer;

a P-type semiconductor layer; and

An active layer located between the N-type semiconductor layer and the P-type semiconductor layer;

at least one of the N-type semiconductor layer and the P-type semiconductor layer is provided with a plurality of laminated pulse layers, and each pulse layer is composed of an unintentionally doped intrinsic sub-layer and a doped sub-layer which is arranged on the intrinsic sub-layer.

2. The epitaxial layer of claim 1, wherein a thickness of one of the pulse layers is 7-30 nm, wherein a thickness of the doped sub-layer is 5-20 nm and a thickness of the intrinsic sub-layer is 2-10 nm.

3. The epitaxial layer of claim 1, wherein the N-type semiconductor layer has a thickness of 1 to 5um and the P-type semiconductor layer has a thickness of 100 to 300nm.

4. The epitaxial layer of claim 1, wherein a direction from the N-type semiconductor layer toward the P-type semiconductor layer is a growth direction of the epitaxial layer; along the growth direction, the doping concentration of the P-type semiconductor layer is gradually increased.

5. The epitaxial layer of claim 4 wherein said P-type semiconductor layer comprises a plurality of third step ladder layers, each of said third step ladder layers having a graded increase in P-type doping concentration along said growth direction, one of said third step ladder layers comprising a plurality of said pulse layers, and each of said doped sublayers in the same said third step ladder layer having the same P-type doping concentration.

6. The epitaxial layer of any one of claims 1 to 5, wherein a direction from the N-type semiconductor layer toward the P-type semiconductor layer is a growth direction of the epitaxial layer, and along the growth direction, the N-type semiconductor layer sequentially includes:

A lower layer of gradually increasing N-type doping concentration; and

And the upper layer with the N-type doping concentration gradually reduced is provided, and the maximum value of the N-type doping concentration in the upper layer is smaller than or equal to the maximum value of the N-type doping concentration in the lower layer.

7. The epitaxial layer of claim 6, wherein an N-type doping concentration gradient of at least one of the lower layer and the upper layer varies.

8. The epitaxial layer of claim 7 wherein said lower layer comprises a plurality of first step ladder layers, each of said first step ladder layers having a graded increase in N-type doping concentration along said growth direction, one of said first step ladder layers comprising a plurality of said pulse layers and each of said doped sublayers in the same first step ladder layer having the same N-type doping concentration;

the upper layer comprises a plurality of second step-down ladder layers, the N-type doping concentration of each second step-down ladder layer is reduced in a gradient mode along the growth direction, one second step-down ladder layer comprises a plurality of pulse layers, and the N-type doping concentration of each doping sub-layer in the same second step-down ladder layer is the same.

9. A light emitting chip, comprising:

epitaxial layer according to any of claims 1 to 8;

An N electrode electrically connected to the N-type semiconductor layer in the epitaxial layer; and

And a P electrode electrically connected with the P-type semiconductor layer in the epitaxial layer.

10. An epitaxial layer growth method, characterized by being applied to the growth of the epitaxial layer according to any one of claims 1 to 8, comprising:

Growing an N-type semiconductor layer;

Growing an active layer;

Growing a P-type semiconductor layer;

At least one of the N-type semiconductor layer and the P-type semiconductor layer grows for a plurality of periods in a pulse growth mode, wherein the pulse growth mode comprises the following steps:

growing an unintentionally doped intrinsic sub-layer;

a doped sub-layer is produced over the intrinsic sub-layer.