CN118073409A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same, the semiconductor structure comprising: a substrate having a first well region with first type doping ions and a second well region with second type doping ions, the first well region and the second well region being arranged adjacent to each other, the first type doping ions and the second type doping ions having different conductivity types; the plurality of heavily doped regions are arranged at intervals and comprise a first heavily doped region, a second heavily doped region and a suspension heavily doped region; the first heavily doped region is positioned in the first well region and provided with second type doped ions; the floating heavy doping region is positioned in the second well region and provided with first type doping ions, the floating heavy doping region is arranged adjacent to the first heavy doping region, and the side wall of the floating heavy doping region is contacted with the side wall of the first well region; the second heavily doped region is positioned in the second well region, the second heavily doped region is arranged adjacent to the suspension heavily doped region, and the second heavily doped region is provided with first type doped ions. The invention increases the working window of the semiconductor device, thereby improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

Integrated circuits are susceptible to electrostatic damage, and protection circuits are generally designed at the input/output terminals of the circuits or in the power protection devices to prevent the internal circuits from being damaged by the static electricity. In existing integrated circuit designs, silicon-controlled rectifier (SCR) devices are often used as electrostatic protection (Electrostatic Discharge, ESD) devices to reduce electrostatic damage.

However, with the rapid growth of the semiconductor integrated circuit (INTEGRATED CIRCUIT, IC) industry, semiconductor technology continues to advance toward smaller process nodes driven by moore's law, resulting in the development of integrated circuits with smaller volumes, higher circuit precision, and higher circuit complexity.

Therefore, the performance of the electrostatic protection structure in the prior art needs to be improved.

Disclosure of Invention

The embodiment of the invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of an electrostatic protection structure.

To solve the above problems, the present invention provides a semiconductor structure, including: the substrate is provided with a first well region with first type doping ions and a second well region with second type doping ions, the first well region and the second well region are adjacently arranged, and the conductivity types of the first type doping ions and the second type doping ions are different; the plurality of heavily doped regions are arranged at intervals and are respectively positioned in the first well region and the second well region, and each heavily doped region comprises a first heavily doped region, a second heavily doped region and a suspension heavily doped region; the first heavily doped region is positioned in the first well region and is provided with second type doped ions; the floating heavy doping region is positioned in the second well region and provided with first type doping ions, the floating heavy doping region is arranged adjacent to the first heavy doping region, and the side wall of the floating heavy doping region is contacted with the side wall of the first well region; the second heavily doped region is positioned in the second well region, the second heavily doped region is arranged adjacent to the suspension heavily doped region, and the second heavily doped region is provided with first type doped ions.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein a first well region with first type doping ions and a second well region with second type doping ions are formed in the substrate, the first well region and the second well region are adjacently arranged, and the conductivity types of the first type doping ions and the second type doping ions are different; forming a plurality of heavily doped regions in the first well region and the second well region at intervals, the forming the heavily doped regions comprising: forming a first heavily doped region in the first well region, wherein the first heavily doped region is provided with second type doping ions; forming a suspension heavy doping region in the second well region, wherein the suspension heavy doping region is provided with first type doping ions, the suspension heavy doping region is arranged adjacent to the first heavy doping region, and the side wall of the suspension heavy doping region is contacted with the side wall of the first well region; and forming a second heavily doped region in the second well region, wherein the second heavily doped region is provided with first type doped ions, and the second heavily doped region is adjacent to the suspended heavily doped region and is provided with a space.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

The semiconductor structure provided by the embodiment of the invention comprises a floating heavy doping region in the second well region, wherein the side wall of the floating heavy doping region is contacted with the side wall of the first well region, and the floating heavy doping region is provided with first type doping ions. When the semiconductor device works, in a charge transmission path from an Anode (Anode) to a Cathode (Cathode), after charges flow from the first heavily doped region to the first well region, the charges can flow to the floating heavily doped region through the first well region and then flow to the second well region through the floating heavily doped region, so that the floating heavily doped region increases the resistance between the Anode and the Cathode, thereby improving the working voltage (holding voltage, vh) of the semiconductor device, correspondingly reducing the difference between the starting voltage and the working voltage, correspondingly increasing the working window of the semiconductor device, further improving the performance of the semiconductor structure, and correspondingly expanding the application range of the semiconductor structure in the field of electrostatic protection (electrostatic discharge, ESD), and obtaining the high-performance electrostatic protection device.

In the method for forming a semiconductor structure provided by the embodiment of the invention, a floating heavy doping region is formed in a second well region, the side wall of the floating heavy doping region is contacted with the side wall of a first well region, and the floating heavy doping region is provided with first type doping ions. When the semiconductor device works, in a charge transmission path from an Anode (Anode) to a Cathode (Cathode), after charges flow from the first heavily doped region to the first well region, the charges can flow to the floating heavily doped region through the first well region and then flow to the second well region through the floating heavily doped region, so that the floating heavily doped region increases the resistance between the Anode and the Cathode, thereby improving the working voltage (holding voltage, vh) of the semiconductor device, correspondingly reducing the difference between the starting voltage and the working voltage, correspondingly increasing the working window of the semiconductor device, further improving the performance of the semiconductor structure, and correspondingly expanding the application range of the semiconductor structure in the field of electrostatic protection (electrostatic discharge, ESD), and obtaining the high-performance electrostatic protection device.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another embodiment of a semiconductor structure of the present invention;

fig. 3 to 6 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;

fig. 7 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention.

Detailed Description

At present, when a silicon controlled device is often used as an electrostatic protection device, the silicon controlled device has lower working voltage, but the starting voltage is relatively higher, and a latch up phenomenon is easy to occur after the silicon controlled device is started, so that the silicon controlled device is limited in application in the field of low-voltage electrostatic protection, and therefore, how to improve the working voltage of a semiconductor device, particularly the working voltage of the silicon controlled device, and reduce the starting voltage of the silicon controlled device becomes a problem to be solved urgently.

In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: the substrate is provided with a first well region with first type doping ions and a second well region with second type doping ions, the first well region and the second well region are adjacently arranged, and the conductivity types of the first type doping ions and the second type doping ions are different; the plurality of heavily doped regions are arranged at intervals and are respectively positioned in the first well region and the second well region, and each heavily doped region comprises a first heavily doped region, a second heavily doped region and a suspension heavily doped region; the first heavily doped region is positioned in the first well region and is provided with second type doped ions; the floating heavy doping region is positioned in the second well region and provided with first type doping ions, the floating heavy doping region is arranged adjacent to the first heavy doping region, and the side wall of the floating heavy doping region is contacted with the side wall of the first well region; the second heavily doped region is positioned in the second well region, the second heavily doped region is arranged adjacent to the suspension heavily doped region, and the second heavily doped region is provided with first type doped ions.

The embodiment of the invention comprises a suspension heavy doping region positioned in the second well region, wherein the side wall of the suspension heavy doping region is contacted with the side wall of the first well region, and the suspension heavy doping region is provided with first type doping ions. When the semiconductor device works, in a charge transmission path from the anode to the cathode, charges can flow to the floating heavy doping region through the first well region after flowing to the first well region, and then flow to the second well region through the floating heavy doping region, so that the floating heavy doping region increases the resistance between the anode and the cathode, the working voltage of the semiconductor device is improved, the difference between the starting voltage and the working voltage is correspondingly reduced, the working window of the semiconductor device is correspondingly increased, the performance of the semiconductor structure is further improved, the application range of the semiconductor structure in the field of electrostatic protection is correspondingly enlarged, and the high-performance electrostatic protection device is obtained.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 1 is a schematic structure diagram of an embodiment of a semiconductor structure according to the present invention.

Referring to fig. 1, a semiconductor structure includes: a substrate 100, in which a first well region 11 having first type doping ions and a second well region 12 having second type doping ions are formed, the first well region 11 and the second well region 12 being adjacently arranged, the first type doping ions and the second type doping ions being different in conductivity type; the heavily doped regions 130 are arranged at intervals and are respectively positioned in the first well region 11 and the second well region 12, and the heavily doped regions 130 comprise a first heavily doped region 131, a second heavily doped region 132 and a floating heavily doped region 133; the first heavily doped region 131 is located in the first well region 11 and has second type doped ions; the floating heavily doped region 133 is located in the second well region 12 and has first type doped ions, the floating heavily doped region 133 is disposed adjacent to the first heavily doped region 131, and a sidewall of the floating heavily doped region 133 contacts a sidewall of the first well region 11; the second heavily doped region 132 is located in the second well region 12, the second heavily doped region 132 is disposed adjacent to the floating heavily doped region 133, and the second heavily doped region 132 has the first type doped ions.

The substrate 100 is used to provide a process platform for subsequent processing.

The base 100 includes a substrate (not shown) that may be of other materials such as silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, or may be of other types such as silicon on insulator or germanium on insulator.

In this embodiment, the substrate 100 includes, in order from bottom to top: a bottom semiconductor layer (not shown), an insulating material layer 101, and a top semiconductor layer 102; the tops of the first well region 11 and the second well region 12 are flush with the top of the top semiconductor layer 102, respectively, and the bottoms of the first well region 11 and the second well region 12 are in contact with the top of the insulating material layer 101, or the bottoms of the first well region 11 and the second well region 12 are in the insulating material layer 101.

Specifically, the insulating material layer 101 is a Buried Oxide (BOX), the material of the buried oxide layer may be Silicon dioxide, the material of the bottom semiconductor layer may be Silicon, germanium or a mixture of Germanium and Silicon, the material of the top semiconductor layer 102 may be undoped Silicon, doped Silicon, undoped Germanium or doped Germanium, when the material of the top semiconductor layer 102 is undoped Silicon or doped Silicon, the substrate On the Insulator is a Silicon-On-Insulator (SOI) structure, and when the material of the top semiconductor layer is undoped Germanium or doped Germanium, the substrate On the Insulator is a Germanium-On-Insulator (GOI) structure. In this embodiment, the substrate on the insulator is silicon on insulator.

High voltage devices are typically fabricated on bulk substrates (e.g., bulk silicon substrates), whereas SOI substrates are used as an example where the operating voltage of the devices fabricated on the SOI substrate is relatively low, and thus increasing the operating voltage of the thyristor device is important for implementing the thyristor device on a substrate 100 of this type for a base 100 consisting of a bottom semiconductor layer (not shown), an insulating material layer 101 and a top semiconductor layer 102.

It should be noted that, the first well region 11 and the second well region 12 are formed in the top semiconductor layer 102, and the bottoms of the first well region 11 and the second well region 12 are respectively contacted with the top of the insulating material layer 101, or the bottoms of the first well region 11 and the second well region 12 are in the insulating material layer 101, so that the subsequently formed semiconductor device has low parasitic noise and current leakage, and the application range is wide, and the method can be used in the field of radio frequency devices.

Through the first well region 11 and the second well region 12 which are adjacently arranged, the first type doping ions of the first well region 11 and the second type doping ions of the second well region 12 have different conductive types, so that the junction of the first well region 11 and the second well region 12 is formed with a bias voltage, thereby forming the silicon controlled device.

When the number of the second well regions 12 is plural and the first well regions 11 and the second well regions 12 are alternately arranged, it is possible to form a triac semiconductor device. In this embodiment, the number of the second well regions 12 is plural, and the first well regions 11 and the second well regions 12 are alternately arranged. As an example, the number of the second well regions 12 is two.

Specifically, in this embodiment, the first type doped ion is an N type ion, and the second type doped ion is a P type ion. The N-type ions include B, ga or In and the P-type ions include P, as or Sb. Thus, a PN junction is formed at the junction of the first well region 11 and the second well region 12.

In this embodiment, the semiconductor structure further includes: the shallow trench isolation structures (Shallow Trench Isolation, STI) 110 are located in the substrate 100, and the regions between adjacent shallow trench isolation structures 110 are active regions (not shown), and the first well region 11 and the second well region 12 are located in the same active region of the substrate 100.

In the process of manufacturing semiconductor devices, a shallow trench isolation structure 110 is generally formed on a substrate, where the shallow trench isolation structure 110 is used to isolate each semiconductor device, so as to prevent leakage current between the devices.

Specifically, the bottom of the shallow trench isolation structure 110 contacts with the top of the insulating material layer 101, or the bottom of the shallow trench isolation structure 110 is located in the insulating material layer 101, so as to improve the isolation performance of the shallow trench isolation structure 110.

The material of the shallow trench isolation structure 110 is an insulating material, and in this embodiment, the material of the shallow trench isolation structure 110 is silicon oxide.

In this embodiment, the semiconductor structure further includes: the gate structures 120 are located on the substrate 100 between the adjacent heavily doped regions 130, and the gate structures 120 are all floating gate structures; or the gate structure 120 between the second heavily doped region 132 and the floating heavily doped region 133 is used for loading a voltage signal, and the rest of the gate structures 120 are all floating gate structures.

It should be noted that the gate structure 120 is a floating gate structure, each doped region 130 is formed on two sides of the gate structure 120, and the gate structure 120 is used to define a position of each heavily doped region 130. Or the gate structure 120 between the second heavily doped region 132 and the floating heavily doped region 133 is used for loading a Voltage signal, so as to reduce the turn-on Voltage (Vt) of the semiconductor device and define the positions of the second heavily doped region 132 and the floating heavily doped region 133, and the remaining gate structure 120 is used for defining the positions of the remaining heavily doped regions 130.

Increasing the width W1 of the gate structure 120 between the second heavily doped region 132 and the floating heavily doped region 133 increases the base resistance, thereby increasing the resistance of the semiconductor device and thus the operating voltage of the semiconductor device.

The width W1 of the gate structure 120 between the second heavily doped region 132 and the floating heavily doped region 133 is not too large or too small, and if the width W1 of the gate structure 120 between the second heavily doped region 132 and the floating heavily doped region 133 is too small, the effect of increasing the base resistance is not good, and the effect of increasing the operating voltage of the semiconductor device is not good; if the width W1 of the gate structure 120 between the second heavily doped region 132 and the floating heavily doped region 133 is too large, the area of the semiconductor structure is easily too large, which is disadvantageous for further shrinking of the process node. Therefore, in the present embodiment, the width W1 of the gate structure 120 between the second heavily doped region 132 and the floating heavily doped region 133 ranges from 0.2 μm to 2 μm. In the present embodiment, the width W1 of the gate structure 120 is set within the above range, so that the turn-on voltage of the semiconductor device can be reduced by 5V to 7V.

The heavily doped regions 130 are respectively located in the first well region 11 and the second well region 12 and are arranged at intervals to form a silicon controlled device.

Specifically, the first heavily doped region 131 is electrically connected to the anode, the second heavily doped region 132 is electrically connected to the cathode, the second heavily doped region 132 is located at a side of the floating heavily doped region 133 away from the first heavily doped region 131, in a charge transmission path from the anode to the cathode, after charges flow from the first heavily doped region 131 to the first well region 11, the charges can flow to the floating heavily doped region 133 through the first well region 11 and then flow to the second well region 12 through the floating heavily doped region 133, so that the floating heavily doped region 133 increases the resistance between the anode and the cathode, thereby increasing the working voltage of the semiconductor device, correspondingly reducing the difference between the starting voltage and the working voltage, correspondingly increasing the working window of the semiconductor device, further improving the performance of the semiconductor structure, correspondingly expanding the application range of the semiconductor in the field of electrostatic protection, and obtaining the high-performance electrostatic protection device.

In this embodiment, the doping concentration of the floating heavily doped region 133 is greater than that of the first well region 11, so that the charges flow from the first well region 11 to the floating heavily doped region 133 easily, and the effect of increasing the charge transmission path is better, and thus the effect of increasing the resistance between the anode and the cathode is correspondingly better.

In one particular embodiment, the sidewalls of the floating heavily doped region 133 are flush with the sidewalls of the first well region 11. In other embodiments, the sidewalls of the suspended heavily doped region are slightly extended into the first well region.

It should be noted that, along the arrangement direction of the first well region 11 and the second well region 12, the width W2 of the floating heavily doped region 133 is increased, and accordingly, the resistance of the floating heavily doped region 133 may be increased, so as to increase the resistance between the anode and the cathode, thereby further increasing the operating voltage of the semiconductor device.

The width W2 of the suspended heavily doped region 133 is preferably not too large nor too small. If the width W2 of the floating heavily doped region 133 is too small, an effect of increasing the resistance between the anode and the cathode is liable to be poor; if the width W2 of the floating heavily doped region 133 is too large, the area of the semiconductor structure is easily too large, which is disadvantageous for further shrinking of the process node. In this embodiment, the width W2 of the suspended heavily doped region 133 along the arrangement direction of the first well region 11 and the second well region 12 is in the range of 1 μm to 4 μm. In this embodiment, the operating voltage is increased by 2V when the width W2 of the floating heavily doped region 133 is increased from 1 micron to 4 microns.

In this embodiment, the heavily doped region 130 further includes: a first body contact region 134 located in the first well region 11 and between the first heavily doped region 131 and the second well region 12, the first body contact region 134 having first type dopant ions; the second body contact region 135 is located in the second well region 12 and on a side of the second heavily doped region 132 remote from the first well region 12, the second body contact region 135 having second type dopant ions.

The first body contact region 134 serves as an external terminal of the first well region 11, and the second body contact region 135 serves as an external terminal of the second well region 12.

In this embodiment, the first well region 11 is electrically connected to the anode via a first body contact region 134, and the second well region 12 is electrically connected to the cathode via a second body contact region 135.

In this embodiment, the semiconductor structure further includes: a metal silicide layer 140 covers the top of the remaining heavily doped region 130 except the floating heavily doped region 133.

In particular, the metal silicide layer 140 may reduce the contact resistance of the heavily doped region 130 with the external electrical connection structure.

Referring to fig. 2, fig. 2 is a schematic structure diagram of another embodiment of the semiconductor structure of the present invention.

The present embodiment is the same as the previous embodiment, and will not be described again here. The present embodiment is different from the foregoing embodiment in that the semiconductor structure further includes: a floating well region 25 located in the second well region 22 at the bottom of the floating heavily doped region 233, wherein the top of the floating well region 25 contacts the bottom of the floating heavily doped region 233, the sidewall of the floating well region 25 is spaced from the opposite sidewall of the first well region 21, and the floating well region 25 has first type doped ions.

Specifically, the floating well region 25 located in the second well region 22 may increase a charge transmission path, so that, in the charge transmission path from the anode to the cathode when the semiconductor device is in operation, a path from the floating heavily doped region 233 to the floating well region 25 and then to the second well region 22 via the floating well region 25 is increased, so that the floating well region 25 further increases the resistance between the anode and the cathode, reduces the switching-on voltage and the operating voltage difference of the semiconductor device, further increases the operating window of the semiconductor device, and correspondingly improves the structural performance of the semiconductor.

The top of the floating well region 25 contacts with the bottom of the floating heavily doped region 233, so that charges can flow from the floating heavily doped region 233 to the floating well region 25, the probability of charges flowing from other paths to the cathode is reduced, the effect of increasing the length of the charge transmission path between the anode and the cathode is better, and the working voltage of the semiconductor device is further improved.

The sidewall of the floating well region 25 is spaced from the opposite sidewall of the first well region 21, so that charges need to flow from the first well region 21 to the floating heavily doped region 233 before flowing from the floating heavily doped region 233 to the floating well region 25, but not directly flowing from the first well region 21 to the floating well region 25, so that the effect of increasing the charge transfer path between the anode and the cathode is better.

It should be noted that, adjusting the width W3 of the floating well region 25 along the arrangement direction of the first well region 21 and the second well region 22 increases the charge transfer path between the anode and the cathode, i.e., increases the resistance between the anode and the cathode, so that the operating voltage of the semiconductor device can be increased.

The width W3 of the suspended well region 25 should not be too large or too small, and if the width W3 of the suspended well region 25 is too small, the effect of easily increasing the resistance between the anode and the cathode is not remarkable; if the width W3 of the floating well region 25 is too large, the interval between the floating well region 25 and the second heavily doped region 232 is liable to be too small, or even not, and thus it is difficult to increase the charge transfer path between the anode and the cathode, which tends to cause poor effect of increasing the resistance between the anode and the cathode. In this embodiment, the width W3 of the floating well region 25 along the arrangement direction of the first well region 21 and the second well region 22 is in the range of 1 μm to 3 μm. For example: the operating voltage is increased by 4V as the width W3 of the suspended well region 25 increases from 2 microns to 3 microns.

When the bottom of the floating well region 25 coincides with the bottom of the second well region 22, the resistance between the anode and the cathode can be maximized with a certain width W3 of the floating well region 25. In this embodiment, the bottom of the floating well 25 coincides with the bottom of the second well 22.

In this embodiment, the floating heavily doped region 233 has a first sidewall 241 facing away from the first well region 21, the floating well region 25 has a second sidewall 242 facing away from the first well region 21, and the second sidewall 242 is close to the first well region 21 with respect to the first sidewall 241.

Specifically, the second sidewall 242 is close to the first well region 21 relative to the first sidewall 241, so that the separation distance between the floating well region 25 and the second heavily doped region 232 is easy to control, and the effect of increasing the charge transfer path between the anode and the cathode is ensured, so that the effect of increasing the resistance between the anode and the cathode is ideal, and the effect of increasing the operating voltage is better.

Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 3 to 7 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 3, a substrate 500 is provided, in which a first well region 51 having first type doping ions and a second well region 52 having second type doping ions are formed in the substrate 500, the first well region 51 and the second well region 52 being adjacently arranged, and the first type doping ions and the second type doping ions being different in conductivity type.

The substrate 500 is used to provide a process platform for subsequent processing.

The base 500 includes a substrate (not shown) which may be silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, or may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

In this embodiment, the substrate 500 includes, in order from bottom to top: a bottom semiconductor layer (not shown), an insulating material layer 501, and a top semiconductor layer 502; the tops of the first well region 51 and the second well region 52 are flush with the top of the top semiconductor layer 502, respectively, and the bottoms of the first well region 51 and the second well region 52 are in contact with the top of the insulating material layer 501, or the bottoms of the first well region 51 and the second well region 52 are in the insulating material layer 501.

Specifically, the insulating material layer 501 is a buried oxide layer, the material of the buried oxide layer may be silicon dioxide, the material of the bottom semiconductor layer may be silicon, germanium or a mixture of germanium and silicon, the material of the top semiconductor layer 502 may be undoped silicon, doped silicon, undoped germanium or doped germanium, when the material of the top semiconductor layer 502 is undoped silicon or doped silicon, the substrate on the insulator is a silicon-on-insulator structure, and when the material of the top semiconductor layer is undoped germanium or doped germanium, the substrate on the insulator is a germanium-on-insulator structure. In this embodiment, the substrate on the insulator is silicon on insulator.

High voltage devices are typically fabricated on bulk substrates (e.g., bulk silicon substrates), whereas SOI substrates are used as an example where the operating voltage of the devices fabricated on the SOI substrate is relatively low, and thus increasing the operating voltage of the thyristor device for a substrate consisting of a bottom semiconductor layer (not shown), an insulating material layer 501 and a top semiconductor layer 502 is of great significance for achieving an application of the thyristor device to a substrate 500 of this type.

It should be noted that, the first well region 51 and the second well region 52 are formed in the top semiconductor layer 502, and the bottoms of the first well region 51 and the second well region 52 are respectively contacted with the top of the insulating material layer 501, or the bottoms of the first well region 51 and the second well region 52 are in the insulating material layer 501, so that the subsequently formed semiconductor device has low parasitic noise and current leakage, and the application range is wide, and the method can be used in the field of radio frequency devices.

By the first well region 51 and the second well region 52 being adjacently arranged, the first type doping ions of the first well region 51 and the second type doping ions of the second well region have different conductive types, so that a bias voltage is formed at the junction of the first well region 51 and the second well region 52, thereby forming a silicon controlled device.

With continued reference to fig. 3, when the number of the second well regions 52 is plural and the first well regions 51 and the second well regions 52 are alternately arranged, it is possible to form a triac semiconductor device. In this embodiment, the number of the second well regions 52 is plural, and the first well regions 51 and the second well regions 52 are alternately arranged. As an example, the number of the second well regions 52 is two.

Specifically, in this embodiment, the first type doped ion is an N type ion, and the second type doped ion is a P type ion. The N-type ions include B, ga or In and the P-type ions include P, as or Sb. Thus, a PN junction is formed at the interface of the first well region 51 and the second well region 52.

In a specific embodiment, the substrate is doped by ion implantation to form the first well region 51 and the second well region 52, where the energy of ion implantation is 50KeV when the first well region 51 is formed, and the energy of ion implantation is 20KeV when the second well region 52 is formed, so that the bottoms of the first well region 51 and the second well region 52 contact with the top of the insulating material layer 501, or the bottoms of the first well region 51 and the second well region 52 are in the insulating material layer 501, which is easy to improve the performance of the semiconductor device formed on the substrate 500 of the first well region 51 and the second well region 55.

With continued reference to fig. 3, in the step of providing the substrate 500, shallow trench isolation structures (Shallow Trench Isolation, STI) 510 are further formed in the substrate 500, and regions between adjacent shallow trench isolation structures 510 are active regions (not labeled), where the first well region 51 and the second well region 52 are located in the same active region of the substrate 500.

In the process of manufacturing semiconductor devices, shallow trench isolation structures 510 are typically formed on a substrate, and the shallow trench isolation structures 510 are used to isolate each semiconductor device, so as to prevent leakage current between the devices.

Specifically, the bottom of the shallow trench isolation structure 510 contacts with the top of the insulating material layer 501, or the bottom of the shallow trench isolation structure 510 is located in the insulating material layer 501, so as to improve the isolation performance of the shallow trench isolation structure 510.

The material of the shallow trench isolation structure 510 is an insulating material, and in this embodiment, the material of the shallow trench isolation structure 510 is silicon oxide.

Referring to fig. 4, in this embodiment, before forming the heavily doped region 530, the method further includes: a plurality of discrete gate structures 520 are formed on the substrate 500 where the first well region 51 and the second well region 52 are located.

It should be noted that, the gate structure 520 is a floating gate structure, each heavily doped region formed later is located at two sides of the gate structure 520, and the gate structure 520 is used to define the position of each heavily doped region formed later. Or the gate structure 520 between the subsequently formed second heavily doped region and the floating heavily doped region is used for loading a Voltage signal, so that the turn-on Voltage (Vt) of the semiconductor device can be reduced, and the positions of the subsequently formed second heavily doped region and the floating heavily doped region are defined, and the remaining gate structure 520 is used for defining the positions of the remaining heavily doped regions.

Increasing the width w1 of the gate structure 520 between the subsequently formed second heavily doped region and the floating heavily doped region increases the base resistance, thereby increasing the resistance of the semiconductor device and thus the operating voltage of the semiconductor device.

The width w1 of the gate structure 520 between the subsequently formed second heavily doped region and the suspended heavily doped region should not be too large or too small, and if the width w1 of the gate structure 520 between the subsequently formed second heavily doped region and the suspended heavily doped region is too small, the effect of increasing the base resistance is poor, and the effect of increasing the operating voltage of the semiconductor device is also poor; if the width w1 of the gate structure 520 between the subsequently formed second heavily doped region and the floating heavily doped region is too large, the area of the semiconductor structure is easily too large, which is disadvantageous for further shrinking of the process node. In this embodiment, the width w1 of the gate structure 520 between the subsequently formed second heavily doped region and the floating heavily doped region is in the range of 0.2 μm to 2 μm. In the present embodiment, the width w1 of the gate structure 520 is set within the above range, so that the turn-on voltage of the semiconductor device can be reduced by 5V to 7V.

In this embodiment, the sidewall of the gate structure 520 formed on the first well region 51 and closest to the second well region 52 is flush with the sidewall of the first well region 51, so that the sidewall of the subsequently formed floating heavily doped region can contact the sidewall of the first well region 51.

Referring to fig. 5, a plurality of heavily doped regions 530 are formed in the first well 51 and the second well region 52 at intervals.

The heavily doped regions 530 are respectively located in the first well region 51 and the second well region 52 and are arranged at intervals for forming a silicon controlled device subsequently.

Referring to fig. 5 and 6 in combination, forming heavily doped region 530 includes: forming a first heavily doped region 531 in the first well region 51, the first heavily doped region 531 having doping ions of the second type; a floating heavily doped region 533 is formed in the second well region 52, the floating heavily doped region 533 has first type doped ions, the floating heavily doped region 533 is disposed adjacent to the first heavily doped region 531, and a sidewall of the floating heavily doped region 533 contacts a sidewall of the first well region 51; a second heavily doped region 532 is formed in the second well region 52, the second heavily doped region 532 having the first type of dopant ions, the second heavily doped region 532 being disposed adjacent to and spaced apart from the floating heavily doped region 533.

Specifically, the first heavily doped region 531 is electrically connected to the anode, the second heavily doped region 532 is electrically connected to the cathode, and in the charge transmission path from the anode to the cathode, after the charges flow from the first heavily doped region 531 to the first well region 51, the charges can flow to the floating heavily doped region 533 through the first well region 51 and then flow to the second well region 52 through the floating heavily doped region 533, so that the resistance between the anode and the cathode is increased by the floating heavily doped region 533, the working voltage of the semiconductor device is increased, the difference between the starting voltage and the working voltage is also reduced, the working window of the semiconductor device is correspondingly increased, the performance of the semiconductor structure is further improved, the application range of the semiconductor in the field of electrostatic protection is correspondingly enlarged, and the high-performance electrostatic protection device is obtained.

In this embodiment, the first well region 51 and the second well region 52 are doped by ion implantation to form a plurality of heavily doped regions 530.

In this embodiment, the doping concentration of the floating heavily doped region 533 is greater than that of the first well region 51, so that charges flow from the first well region 51 to the floating heavily doped region 533 more easily, and the effect of increasing the charge transfer path is better, and thus the effect of increasing the resistance between the anode and the cathode is correspondingly better.

In a specific embodiment, the sidewalls of the floating heavily doped region 533 are flush with the sidewalls of the first well region 51. In other embodiments, the sidewalls of the suspended heavily doped region are slightly extended into the first well region.

It should be noted that, along the arrangement direction of the first well region 51 and the second well region 52, the width w2 of the floating heavily doped region 533 is increased, and accordingly, the resistance of the floating heavily doped region 533 may be increased, so that the resistance between the anode and the cathode is increased, thereby further increasing the operating voltage of the semiconductor device.

The width w2 of the suspended heavily doped region 533 should not be too large or too small, and if the width w2 of the suspended heavily doped region 533 is too small, the effect of increasing the resistance between the anode and the cathode is easily poor; if the width w2 of the floating heavily doped region 533 is too large, the area of the semiconductor structure is easily too large, which is disadvantageous for further shrinking of the process node. In this embodiment, the width w2 of the suspended heavily doped region 533 along the arrangement direction of the first well region 51 and the second well region 52 is in the range of 1 μm to 4 μm. In this embodiment, the operating voltage is increased by 2V when the width w2 of the floating heavily doped region 133 is increased from 1 micron to 4 microns.

With continued reference to fig. 5, in the step of forming a plurality of heavily doped regions 530 in the first well region 51 and the second well region 52, the adjacent heavily doped regions 530 are located at two sides of the gate structure 520. The gate structure 520 is used to define the position of each heavily doped region 530, which is beneficial to improving the position accuracy of each heavily doped region 530.

With continued reference to fig. 5, in this embodiment, forming the heavily doped region 530 further includes: forming a first body contact region 534 in the first well region 51, the first body contact region 534 being located between the first heavily doped region 531 and the second well region 52, and the first body contact region 534 having first type dopant ions; a second body contact region 535 is formed in the second well region 52, the second body contact region 535 being located on a side of the second heavily doped region 52 remote from the first well region 51, and the second body contact region 535 having second type dopant ions.

The first body contact region 534 serves as an external terminal to the first well region 51, and the second body contact region 535 serves as an external terminal to the second well region 52.

Specifically, the first well region 51 is electrically connected to the anode through a first body contact region 534, and the second well region 52 is electrically connected to the cathode through a second body contact region 535.

In this embodiment, the first well region 51 and the second well region 52 are doped by ion implantation to form a first body contact region 534 and a second body contact region 535, respectively.

In one embodiment, the energy of ion implantation when forming the first body contact region 534 is 10KeV and the energy of ion implantation when forming the second body contact region 535 is 5KeV. Thus, the first body contact region 534 may be formed in the same step as the suspended heavily doped region 533 and the second heavily doped region 532, and the second body contact region 535 may be formed in the same step as the first heavily doped region 531, reducing process steps and reducing process costs.

Referring to fig. 6, in this embodiment, the forming method further includes: a metal silicide layer 540 is formed, the metal silicide layer 540 covering the top of the remaining heavily doped region 530 except for the floating heavily doped region 533.

In particular, the metal silicide layer 540 may reduce the contact resistance of the heavily doped region 530 with external electrical connection structures.

Referring to fig. 7, fig. 7 is a schematic structural diagram corresponding to each step in another embodiment of a method for forming a semiconductor structure according to the present invention.

The present embodiment is the same as the previous embodiment, and will not be described again here. This embodiment differs from the previous embodiments in that: before forming the floating heavily doped region 633 in the second well region 62, it further includes: forming a suspended well region 65 in the second well region 62, wherein the side wall of the suspended well region 65 is spaced from the side wall of the first well region 61, and the suspended well region 65 is provided with first type doped ions; in the step of forming the floating heavily doped region 633 in the second well region 62, the bottom of the floating heavily doped region 633 contacts the top of the floating well region 62.

Specifically, the floating well region 65 is formed in the second well region 62, so that a charge transmission path can be increased, and a path from the floating heavily doped region 633 to the floating well region 65 and then to the second well region 62 via the floating well region 65 is increased in the charge transmission path from the anode to the cathode when the semiconductor device works, so that the floating well region 65 further increases the resistance between the anode and the cathode, reduces the starting voltage and the working voltage difference of the semiconductor device, further increases the working window of the semiconductor device, and correspondingly improves the structural performance of the semiconductor.

The top of the floating well region 65 contacts with the bottom of the floating heavily doped region 633, so that charges can flow from the floating heavily doped region 633 to the floating well region 65, the probability that charges flow from other paths to the cathode is reduced, the effect of increasing the length of the charge transmission path between the anode and the cathode is better, and the working voltage of the semiconductor device is further improved.

The sidewall of the floating well region 65 is spaced from the opposite sidewall of the first well region 61, so that charges need to flow from the first well region 61 to the floating heavily doped region 633 before flowing from the floating heavily doped region 633 to the floating well region 65, but not directly flowing from the first well region 61 to the floating well region 65, thereby improving the effect of increasing the charge transfer path between the anode and the cathode.

In the present embodiment, the floating well region 65 is formed simultaneously with the formation of the first well region 61; the step of forming the floating heavily doped region 633 in the second well region 62 includes: a floating heavily doped region 633 is formed in the floating well region 65 and the second well region 62, and the floating well region 65 of the remaining thickness of the bottom of the floating heavily doped region 633 is left.

Specifically, while forming the first well region 61, the floating well region 65 is formed, which is favorable for reducing corresponding process steps, forming the floating heavy doped region 633 in the floating well region 65 and the second well region 62, and retaining the floating well region 65 with the residual thickness at the bottom of the floating heavy doped region 633, which is favorable for controlling the dimensional accuracy, the morphology accuracy and the doping concentration of the floating heavy doped region 633, and meanwhile, avoiding the problem that the ions of the floating well region 65 pass through the floating heavy doped region 633, and is favorable for precisely controlling the dimensional accuracy, the morphology accuracy and the doping concentration of the floating well region 65 correspondingly. In one embodiment, the floating well region 65 is doped by ion implantation, and the energy of ion implantation to form the floating well region 65 is 50KeV.

It should be noted that, adjusting the width w3 of the floating well region 65 along the arrangement direction of the first well region 61 and the second well region 62 increases the charge transfer path between the anode and the cathode, i.e., increases the resistance between the anode and the cathode, so that the operating voltage of the semiconductor device can be increased.

The width w3 of the suspended well region 65 should not be too large or too small, and if the width w3 of the suspended well region 65 is too small, the effect of easily increasing the resistance between the anode and the cathode is not obvious; if the width w3 of the floating well region 65 is too large, the interval between the floating well region 65 and the second heavily doped region 632 is liable to be too small, or even not, and thus it is difficult to increase the charge transfer path between the anode and the cathode, which tends to cause poor effect of increasing the resistance between the anode and the cathode. In this embodiment, the width w3 of the floating well 65 is in the range of 1 μm to 3 μm along the arrangement direction of the first well 61 and the second well 62. For example: the operating voltage is increased by 4V as the width w3 of the suspended well region 65 increases from 2 microns to 3 microns.

In the present embodiment, in the step of forming the floating well region 65 in the second well region 62, the bottom of the floating well region 65 coincides with the bottom of the second well region 62. The bottom of the floating well region 65 coincides with the bottom of the second well region 62, so that the resistance between the anode and the cathode can be increased to the greatest extent with a certain width w3 of the floating well region 65.

In the present embodiment, in the step of forming the floating well region 65 in the second well region 62, the floating well region 65 has the second sidewall 642 facing away from the first well region 61; in the step of forming the floating heavily doped region 633 in the second well region 62, the floating heavily doped region 633 has a first sidewall 641 facing away from the first well region 61, and the second sidewall 642 is close to the first well region 61 with respect to the first sidewall 641.

Specifically, the second sidewall 642 is close to the first well region 61 relative to the first sidewall 641, so that the separation distance between the floating well region 65 and the second heavily doped region 632 is easy to control, and the effect of increasing the charge transfer path between the anode and the cathode is ensured, so that the effect of increasing the resistance between the anode and the cathode is ideal, and the effect of increasing the operating voltage is better.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (19)

1. A semiconductor structure, comprising:

The semiconductor device comprises a substrate, wherein a first well region with first type doped ions and a second well region with second type doped ions are formed in the substrate, the first well region and the second well region are adjacently arranged, and the conductivity types of the first type doped ions and the second type doped ions are different;

The heavily doped regions are arranged at intervals and are respectively positioned in the first well region and the second well region, and each heavily doped region comprises a first heavily doped region, a second heavily doped region and a suspension heavily doped region; wherein the first heavily doped region is located in the first well region and has the second type of doping ions;

The suspended heavy doping region is positioned in the second well region and provided with the first type doping ions, the suspended heavy doping region is arranged adjacent to the first heavy doping region, and the side wall of the suspended heavy doping region is contacted with the side wall of the first well region;

The second heavily doped region is positioned in the second well region, the second heavily doped region is arranged adjacent to the suspension heavily doped region, and the second heavily doped region is provided with the first type doped ions.

2. The semiconductor structure of claim 1, wherein a width of the floating heavily doped region along an arrangement direction of the first well region and the second well region is in a range of 1 micron to 4 microns.

3. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: the grid electrode structures are positioned on the substrate between the adjacent heavily doped regions and are all suspended grid electrode structures; or the grid structure between the second heavily doped region and the suspension heavily doped region is used for loading voltage signals, and the rest of the grid structures are suspension grid structures.

4. The semiconductor structure of claim 3, wherein a width of the gate structure between the second heavily doped region and the floating heavily doped region ranges from 0.2 microns to 2 microns.

5. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: the floating well region is positioned in the second well region at the bottom of the floating heavy doping region, the top of the floating well region is contacted with the bottom of the floating heavy doping region, the side wall of the floating well region is spaced from the opposite side wall of the first well region, and the floating well region is provided with the first type doping ions.

6. The semiconductor structure of claim 5, wherein the floating heavily doped region has a first sidewall facing away from the first well region, the floating well region has a second sidewall facing away from the first well region, the second sidewall being adjacent to the first well region relative to the first sidewall.

7. The semiconductor structure of claim 5, wherein a bottom of the floating well region coincides with a bottom of the second well region.

8. The semiconductor structure of claim 5, wherein a width of the floating well region along an arrangement direction of the first well region and the second well region is in a range of 1 micron to 3 microns.

9. The semiconductor structure of claim 1, wherein the heavily doped region further comprises:

A first body contact region in the first well region and between the first heavily doped region and the second well region, the first body contact region having the first type dopant ions;

and a second body contact region in the second well region and on a side of the second heavily doped region away from the first well region, the second body contact region having the second type dopant ions.

10. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: and a metal silicide layer covering the top of the rest of the heavily doped region except the suspended heavily doped region.

11. The semiconductor structure of claim 1, wherein the first type of dopant ions are N-type ions and the second type of dopant ions are P-type ions.

12. The semiconductor structure of claim 1, wherein the substrate comprises, in order from bottom to top: a bottom semiconductor layer, an insulating material layer, and a top semiconductor layer;

the tops of the first well region and the second well region are respectively flush with the top of the top semiconductor layer, and the bottoms of the first well region and the second well region are respectively contacted with the top of the insulating material layer, or the bottoms of the first well region and the second well region are in the insulating material layer.

13. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a first well region with first type doping ions and a second well region with second type doping ions are formed in the substrate, the first well region and the second well region are adjacently arranged, and the conductivity types of the first type doping ions and the second type doping ions are different;

forming a plurality of heavily doped regions in the first well region and the second well region at intervals, wherein forming the heavily doped regions comprises:

forming a first heavily doped region in the first well region, the first heavily doped region having the second type of dopant ions;

forming a suspension heavy doping region in the second well region, wherein the suspension heavy doping region is provided with the first type doping ions, the suspension heavy doping region is arranged adjacent to the first heavy doping region, and the side wall of the suspension heavy doping region is contacted with the side wall of the first well region;

And forming a second heavily doped region in the second well region, wherein the second heavily doped region is provided with the first type doped ions, and the second heavily doped region is adjacent to the suspension heavily doped region and has a space.

14. The method of forming a semiconductor structure of claim 13, further comprising, prior to forming the heavily doped region: forming a plurality of discrete gate structures on a substrate where the first well region and the second well region are located;

in the step of forming a plurality of heavily doped regions arranged at intervals in the first well region and the second well region, the adjacent heavily doped regions are positioned at two sides of the gate structure.

15. The method of forming a semiconductor structure of claim 13, further comprising, prior to forming a floating heavily doped region in the second well region: forming a suspended well region in the second well region, wherein the side wall of the suspended well region is spaced from the side wall of the first well region, and the suspended well region is provided with first type doped ions;

in the step of forming the floating heavy doping region in the second well region, the bottom of the floating heavy doping region is contacted with the top of the floating well region.

16. The method of forming a semiconductor structure of claim 15, wherein the floating well region is formed at the same time as the first well region is formed;

The step of forming a floating heavily doped region in the second well region comprises: and forming a suspended heavy doping region in the suspended well region and the second well region, and reserving the suspended well region with the residual thickness at the bottom of the suspended heavy doping region.

17. The method of forming a semiconductor structure of claim 15, wherein in the step of forming a floating well region in the second well region, the floating well region has a second sidewall facing away from the first well region;

In the step of forming a floating heavily doped region in the second well region, the floating heavily doped region has a first sidewall facing away from the first well region, and the second sidewall is adjacent to the first well region relative to the first sidewall.

18. The method of forming a semiconductor structure of claim 15, wherein in the step of forming a floating well region in the second well region, a bottom of the floating well region coincides with a bottom of the second well region.

19. The method of forming a semiconductor structure of claim 13, further comprising: and forming a metal silicide layer, wherein the metal silicide layer covers the tops of the rest of the heavily doped regions except the suspended heavily doped regions.