CN118070717A - Storage unit coupling simulation method and device, storage medium and computing equipment - Google Patents
Storage unit coupling simulation method and device, storage medium and computing equipment Download PDFInfo
- Publication number
- CN118070717A CN118070717A CN202410465261.4A CN202410465261A CN118070717A CN 118070717 A CN118070717 A CN 118070717A CN 202410465261 A CN202410465261 A CN 202410465261A CN 118070717 A CN118070717 A CN 118070717A
- Authority
- CN
- China
- Prior art keywords
- simulation
- voltage
- memory cell
- control gate
- charge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004088 simulation Methods 0.000 title claims abstract description 291
- 238000000034 method Methods 0.000 title claims abstract description 48
- 230000008878 coupling Effects 0.000 title claims abstract description 40
- 238000010168 coupling process Methods 0.000 title claims abstract description 40
- 238000005859 coupling reaction Methods 0.000 title claims abstract description 40
- 238000007667 floating Methods 0.000 claims description 28
- 238000004590 computer program Methods 0.000 claims description 18
- 238000004364 calculation method Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 description 11
- 238000012360 testing method Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 238000004891 communication Methods 0.000 description 4
- 108010001267 Protein Subunits Proteins 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
The application provides a storage unit coupling simulation method and device, a storage medium and a computing device, wherein the storage unit coupling simulation method comprises the following steps: erasing the simulation memory cell array until the control gate voltage of the central simulation memory cell reaches a first target starting voltage; writing in the center simulation memory unit until the control gate voltage of the center simulation memory unit reaches a second target starting voltage; writing the first simulation memory unit according to the first charge to obtain a first voltage of the control gate of the center simulation memory unit, and writing the second simulation memory unit according to the second charge to obtain a second voltage of the control gate of the center simulation memory unit; and calculating the interference of the first simulation memory unit and the second simulation memory unit to the central simulation memory unit according to the second target starting voltage, the first voltage and the second voltage. The application provides a technical scheme for improving coupling simulation efficiency of a storage unit.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a storage unit coupling simulation method and apparatus, a storage medium, and a computing device.
Background
Simulation of coupling between cells in a memory array requires that the written and erased cells be obtained by write and erase simulation, and then looking at the coupling between cells. The write and erase simulation is a process that simulates a voltage application process, causing current to flow into or out of the floating gate through the gate oxide.
The method of writing and erasing cells is obtained by writing and erasing the simulation in the simulation process, which is very time-consuming and is prone to the situation of simulation interruption, i.e. the situation that the simulation cannot be continued due to non-convergence of the simulation. Implementing a graphical user interface (Graphics User Interface, GUI) for a technician would require adding more than ten device simulation tools and parameter extraction tools to the interface, while adding more than one device simulation tool and parameter extraction tool to the GUI interface, resulting in a very complex simulation process operation.
Therefore, simplifying the simulation process is a technical problem commonly faced in the art.
Disclosure of Invention
The application provides a technical scheme for improving coupling simulation efficiency of a storage unit.
In order to achieve the above purpose, the present application provides the following technical solutions:
In a first aspect, a memory cell coupling simulation method is provided, where the memory cell coupling simulation method includes: erasing the simulation memory cell array until the control gate voltage of the central simulation memory cell reaches a first target starting voltage; writing the central simulation memory unit until the control gate voltage of the central simulation memory unit reaches a second target starting voltage; writing a first simulation memory cell according to a first charge to obtain a first voltage of a control gate of the center simulation memory cell, and writing a second simulation memory cell according to a second charge to obtain a second voltage of the control gate of the center simulation memory cell, wherein the first simulation memory cell and the second simulation memory cell are cells adjacent to the center simulation memory cell in row and column directions respectively; and calculating the interference of the first simulation memory unit and the second simulation memory unit to the central simulation memory unit according to the second target starting voltage, the first voltage and the second voltage.
Optionally, the first target turn-on voltage represents a turn-on voltage corresponding to a removed charge in the floating gate of the memory cell to be simulated, and the second target turn-on voltage represents a turn-on voltage corresponding to a placed charge in the floating gate of the memory cell to be simulated.
Optionally, the step of acquiring the first charge and the second charge includes: and calculating first charges and second charges which are required to be written when the control gate voltages of the first simulation memory cell and the second simulation memory cell reach the second target starting voltage.
Optionally, the calculating the first charge and the second charge to be written when the control gate voltages of the first dummy memory cell and the second dummy memory cell reach the second target turn-on voltage includes: adding charges to the floating gate of the first simulation memory cell until the control gate voltage of the first simulation memory cell reaches the second target starting voltage, and recording the required charges as the first charges; and adding charges to the floating gate of the second simulation memory cell until the control gate voltage of the second simulation memory cell reaches the second target starting voltage, and recording the required charges as the second charges.
Optionally, the first dummy memory cell includes at least one first dummy memory sub-cell adjacent to the central dummy memory cell in a row direction, and writing the first dummy memory cell according to the first charge includes: and writing the at least one first simulation storage subunit according to the first charges, and recording the first voltage of the control gate of the central simulation storage subunit after the writing is completed.
Optionally, the second simulation memory cell includes at least one second simulation memory subunit adjacent to the central simulation memory cell in a column direction, and a third simulation memory subunit adjacent to the at least one second simulation memory subunit in a row direction, respectively.
Optionally, before writing the second dummy memory cell according to the second charge, the method further includes: adding charges to the floating gate of the second simulation storage subunit until the control gate voltage of the second simulation storage subunit reaches the second target starting voltage, and recording the required charges as the second charges; and adding charges to the floating gate of the third simulation storage subunit until the control gate voltage of the third simulation storage subunit reaches the second target starting voltage, and recording the required charges as third charges.
Optionally, the writing the second dummy memory cell according to the second charge, and the obtaining the second voltage of the control gate of the center dummy memory cell includes: writing at least one second simulation storage subunit according to the second charge, and recording a second voltage of a control gate of the center simulation storage subunit after writing is completed; and writing part or all of the third simulation storage sub-units according to the third charges, and recording the third voltage of the control gate of the center simulation storage unit after the writing is completed.
Optionally, the calculating the interference of the first simulation memory cell and the second simulation memory cell to the central simulation memory cell according to the second target turn-on voltage, the first voltage and the second voltage includes: calculating a first difference value between the second voltage and the first voltage as interference of the second simulation storage subunit to the central simulation storage unit; and calculating a second difference value between the third voltage and the second voltage as interference of the third simulation storage subunit to the central simulation storage unit.
Optionally, the calculating the interference of the first simulation memory cell and the second simulation memory cell to the central simulation memory cell according to the second target turn-on voltage, the first voltage and the second voltage includes: and calculating a third difference value between the first voltage and the second target starting voltage as interference of the first simulation memory unit to the central simulation memory unit.
Optionally, before erasing the dummy memory cell array, the method further includes: initializing the simulated memory cell array to make charges in floating gates of each simulated memory cell in the simulated memory cell array zero.
In a second aspect, the present application also discloses a memory cell coupling simulation device, where the memory cell coupling simulation device includes: the erasing module is used for erasing the simulation memory cell array until the control gate voltage of the center simulation memory cell reaches a first target starting voltage; the first writing module is used for writing the central simulation memory unit until the control gate voltage of the central simulation memory unit reaches a second target starting voltage; the second writing module is used for writing the first simulation memory unit according to the first charge, obtaining the first voltage of the control gate of the center simulation memory unit, writing the second simulation memory unit according to the second charge, and obtaining the second voltage of the control gate of the center simulation memory unit, wherein the first simulation memory unit and the second simulation memory unit are units adjacent to the center simulation memory unit in the row direction and the column direction respectively; and the interference calculation module is used for calculating the interference of the first simulation memory unit and the second simulation memory unit to the central simulation memory unit according to the second target starting voltage, the first voltage and the second voltage.
In a third aspect, there is provided a computer readable storage medium having stored thereon a computer program for execution by a processor to perform the method provided by the first aspect.
In a fourth aspect, there is provided a memory cell coupled simulation apparatus comprising a memory and a processor, the memory having stored thereon a computer program executable on the processor, the processor running the computer program to perform a method as provided in the first aspect.
In a fifth aspect, there is provided a computer program product having a computer program stored thereon, the computer program being executable by a processor to perform the method provided by the first aspect.
In a sixth aspect, an embodiment of the present application further provides a chip (or data transmission device), where a computer program is stored on the chip, and when the computer program is executed by the chip, the steps of the method are implemented.
In a seventh aspect, an embodiment of the present application further provides a system chip, applied to a terminal, where the system chip includes at least one processor and an interface circuit, where the interface circuit and the at least one processor are interconnected by a line, and the at least one processor is configured to execute instructions to perform a method provided in the first aspect.
Compared with the prior art, the technical scheme of the application has the following beneficial effects:
In the technical scheme of the application, the simulation memory cell array is erased until the control gate voltage of the central simulation memory cell reaches a first target starting voltage; writing in the center simulation memory unit until the control gate voltage of the center simulation memory unit reaches a second target starting voltage; writing the first simulation memory cell according to the first charge to obtain a first voltage of a control gate of the center simulation memory cell, and writing the second simulation memory cell according to the second charge to obtain a second voltage of the control gate of the center simulation memory cell, wherein the first simulation memory cell is a cell adjacent to the center simulation memory cell in the row direction, and the second simulation memory cell is a cell adjacent to the center simulation memory cell in the column direction; and calculating the interference of the first simulation memory unit and the second simulation memory unit to the central simulation memory unit according to the second target starting voltage, the first voltage and the second voltage. According to the technical scheme, the charge is predetermined and written into the simulation memory unit, namely, the proper charge is directly put into the floating gate of the simulation memory unit through calculation, and the condition that the simulation current flows through the gate oxide is not needed, so that the simulation memory unit is easier to converge, the simulation time is saved, and the simulation efficiency is improved. In addition, because the simulation current does not need to flow through the grid oxide, the simulation flow is simplified, the scheme can complete coupling simulation in one device simulation tool, the simulation process is simplified, the GUI interface of the simulation tool is simpler, and the user experience is improved.
Drawings
FIG. 1 is a flow chart of a method for simulating coupling of memory cells according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a simulated memory cell array according to an embodiment of the present application;
Fig. 3 to 6 are schematic views illustrating respective states of a dummy memory cell array according to an embodiment of the present application;
FIG. 7 is a flowchart illustrating another embodiment of a method for simulating coupling between memory cells;
fig. 8 is a schematic structural diagram of a memory cell coupling simulation device according to an embodiment of the present application.
Detailed Description
As described in the background, simplifying the simulation process is a technical problem commonly faced in the art.
According to the technical scheme, the charge is predetermined and written into the simulation memory unit, namely, the proper charge is directly put into the floating gate of the simulation memory unit through calculation, and the condition that the simulation current flows through the gate oxide is not needed, so that the simulation memory unit is easier to converge, the simulation time is saved, and the simulation efficiency is improved. In addition, because the simulation current does not need to flow through the grid oxide, the simulation flow is simplified, the scheme can complete coupling simulation in one device simulation tool, the simulation process is simplified, the GUI interface of the simulation tool is simpler, and the user experience is improved.
In order that the above objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring to fig. 1, the method provided by the application specifically includes the following steps:
step 101: erasing the simulation memory cell array until the control gate voltage of the central simulation memory cell reaches a first target starting voltage;
step 102: writing in the center simulation memory unit until the control gate voltage of the center simulation memory unit reaches a second target starting voltage;
Step 103: writing the first simulation memory cell according to the first charge to obtain a first voltage of a control gate of the central simulation memory cell, and writing the second simulation memory cell according to the second charge to obtain a second voltage of the control gate of the central simulation memory cell, wherein the first simulation memory cell and the second simulation memory cell are cells adjacent to the central simulation memory cell in row and column directions respectively;
step 104: and calculating the interference of the first simulation memory unit and the second simulation memory unit to the central simulation memory unit according to the second target starting voltage, the first voltage and the second voltage.
It should be noted that the serial numbers of the steps in the present embodiment do not represent a limitation on the execution sequence of the steps.
It will be appreciated that in a specific implementation, the memory unit coupling simulation method may be implemented in a software program running in a processor integrated within a chip or a chip module. The method may also be implemented by combining software with hardware, and the application is not limited.
In this embodiment, the first target on voltage and the second target on voltage may be obtained by a pre-test. Specifically, the WAT is used to test the electrical parameters of the transistor, which is obtained through wafer receiving test (WAFER ACCEPTANCE TEST, WAT). The test data of WAT includes a first target turn-on voltage VtERS and a second target turn-on voltage VtPGM.
In particular embodiments, the first target turn-on voltage VtERS represents a turn-on voltage corresponding to a floating gate of a memory cell to be emulated after a charge is removed, and the second target turn-on voltage VtPGM represents a turn-on voltage corresponding to a floating gate of a memory cell to be emulated after a charge is placed in the floating gate. Specifically, when the wafer receives the test, the memory cell is erased and written (for example, the memory cell is erased and written with a specific voltage and time), then a transfer characteristic curve (IDVG curve) is obtained through the test, and then a first target turn-on voltage VtERS and a second target turn-on voltage VtPGM are obtained through a IDVG curve.
Referring also to fig. 2, fig. 2 shows an array of dummy memory cells. The dummy memory cell array includes 9 dummy memory cells. The central simulation memory unit is positioned at the center of the simulation memory unit array, namely adjacent simulation memory units exist in all directions around the central simulation memory unit.
Specifically, the center dummy memory cell is adjacent to the memory cell A1 and the memory cell A2 in the row direction. The center dummy memory cell is adjacent to the memory cell B1 and the memory cell B2 in the column direction, the memory cell C1 and the memory cell C2 are adjacent to the memory cell B1 in the row direction, and the memory cell C3 and the memory cell C4 are adjacent to the memory cell B2 in the row direction. The embodiment of the application can determine the interference of at least one part of the storage units A1, A2, B1, B2 and C1-C4 to the central simulation storage unit when determining the interference of the adjacent storage units to the central simulation storage unit.
In one non-limiting embodiment, prior to step 101, the array of dummy memory cells may also be initialized such that the charge in the floating gates of each dummy memory cell in the array of dummy memory cells is zero.
In the implementation of step 101, all the memory cells in the array of dummy memory cells are erased until the control gate voltage of the center dummy memory cell reaches the first target turn-on voltage. Further, the charge QERS required for the control gate voltage of the center dummy memory cell to reach the first target turn-on voltage can also be obtained by scanning the charge.
In the implementation of step 102, the center dummy memory cell is written until the control gate voltage of the center dummy memory cell reaches the second target turn-on voltage. Further, the charge fg_charge_center required for the control gate voltage of the center dummy memory cell to reach the second target on voltage can also be obtained by scanning the charge.
The state of each of the dummy memory cells in the dummy memory cell array at this time is shown in fig. 3. Where P represents write and E represents erase. That is, the center dummy memory cell is in the written state and the other dummy memory cells are in the erased state, via step 102.
In an implementation of step 103, the first dummy memory cell is written with a first charge. The first dummy memory cell is a dummy memory cell adjacent to the center dummy memory cell in the row direction (i.e., dummy memory cell A1 and dummy memory cell A2 in fig. 2). The first charge represents the charge required when the control gate voltage of the first simulation memory cell reaches the second target starting voltage.
The state of each of the dummy memory cells in the dummy memory cell array at this time is shown in fig. 4. Where P represents write and E represents erase. That is, the center dummy memory cell and the first dummy memory cell are in a written state and the other dummy memory cells are in an erased state, via step 103. In this case, a first voltage of the control gate of the center dummy memory cell is obtained. Because other simulation memory cells are in an erased state, the interference of the first simulation memory cell to the central simulation memory cell can be reflected by the first voltage and the second target starting voltage.
Similarly, in the implementation of step 103, the second dummy memory cell is written with the second charge. The second dummy memory cell includes dummy memory cells adjacent to the center dummy memory cell in the column direction (i.e., dummy memory cells B1, B2, C1-C4 in fig. 2). The second charge represents the charge required when the control gate voltage of the second simulation memory cell reaches the second target turn-on voltage.
Specifically, after writing to the dummy memory cells B1 and B2, the states of the respective dummy memory cells in the dummy memory cell array are as shown in fig. 5. Where P represents write and E represents erase. That is, through step 103, the center dummy memory cell, the first dummy memory cell, and the second dummy memory cell are all in a written state, and the other dummy memory cells are in an erased state. In this case, a second voltage of the control gate of the center dummy memory cell is obtained. Because other simulation memory cells are in an erased state, the interference of the second simulation memory cell to the central simulation memory cell can be reflected by the first voltage and the second voltage.
In a particular embodiment, the second dummy memory cell is adjacent to at least one second dummy memory cell (i.e., dummy memory cells B1 and B2 in fig. 2) of the center dummy memory cell in the column direction, and the third dummy memory cell (i.e., dummy memory cells C1-C4 in fig. 2) is adjacent to at least one second dummy memory cell, respectively, in the row direction.
The embodiment of the application can respectively calculate the interference of the second simulation storage subunit and the third simulation storage subunit to the central simulation storage unit.
In this embodiment, at least one second dummy memory sub-cell is written according to the second charge, and the second voltage of the control gate of the center dummy memory cell after the writing is completed is recorded. And writing part or all of the third simulation memory sub-units according to the third charges, and recording the third voltage of the control gate of the central simulation memory unit after the writing is completed. Wherein the third charge represents a charge required by the control gate voltage of the third emulated memory subunit to reach the second target turn-on voltage.
Further, a first difference between the second voltage and the first voltage is calculated as an interference of the second emulated memory subunit to the central emulated memory unit.
Further, a second difference between the third voltage and the second voltage is calculated as an interference of the third emulated memory subunit to the central emulated memory unit.
Specifically, as described above, the number of the second dummy memory sub-units is two, and when at least one second dummy memory sub-unit is written according to the second electric charge, one second dummy memory sub-unit may be written, or two second dummy memory sub-units may be written.
Accordingly, the number of the third simulation storage subunits is four, and when at least one third simulation storage subunit is written according to the third charge, two second simulation storage subunits can be written, and four second simulation storage subunits can also be written.
Similarly, the number of the first emulation memory subunits is two, and when at least one first emulation memory subunit is written according to the first charge, one first emulation memory subunit can be written, and two first emulation memory subunits can also be written.
In one specific example, the second target turn-on voltage is VtPGM. Only two first dummy memory subcells are written to according to the first charge, recording the first voltage as vt_ centerA. Only one second emulated memory subunit is written with a second charge, recording the second voltage as vt_ centerB. Only the two second dummy memory subcells are written to according to the third charge, recording the second voltage to vt_ centerC.
The state of each of the dummy memory cells in the dummy memory cell array at this time is shown in fig. 6. The central simulation storage unit, the two first simulation storage subunits, the second simulation storage subunit positioned above the central simulation storage unit and the two third simulation storage subunits adjacent to the second simulation storage subunit are all in a writing state, and the other simulation storage units are in an erasing state.
The interference INTERFERENCEA of the two first emulated storage subunits on the central emulated storage unit may be represented as the following equation (1).
InterferenceA=Vt_centerA-VtPGM （1）。
The disturbance InterferenceB of the single second emulated storage subunit to the central emulated storage unit may be represented as formula (2) below.
InterferenceB= Vt_centerB-Vt_centerA （2）。
The interference INTERFERENCEC of the two third emulated storage subunits on the central emulated storage unit may be represented as the following equation (3).
InterferenceC= Vt_centerC-Vt_centerB （3）。
The Total Interference total_interference of the center simulation memory cell can be expressed as the following formula (4).
Total_Interference=InterferenceA+InterferenceB×2+InterferenceC×2 （4）。
In the embodiment of the application, each charge written into the simulation memory cell is predetermined, namely, the proper charge is directly put into the floating gate of the simulation memory cell through calculation, and the condition that the simulation current flows through the gate oxide is not needed, so that the simulation memory cell is easier to converge, the simulation time is saved, and the simulation efficiency is improved.
In one non-limiting embodiment, fig. 7 illustrates the steps of acquiring a first charge and a second charge.
Specifically, in step 701, charge is added to the floating gate of the first dummy memory cell until the control gate voltage of the first dummy memory cell reaches the second target turn-on voltage, and the required charge is recorded as the first charge.
In step 702, charge is added to the floating gate of the second dummy memory cell until the control gate voltage of the second dummy memory cell reaches the second target turn-on voltage, and the required charge is recorded as the second charge.
Further, as previously described, the second emulated storage unit includes a second emulated storage subunit and a third emulated storage subunit. Then step 702 may further comprise the steps of: adding charges to the floating gate of the second simulation storage subunit until the control gate voltage of the second simulation storage subunit reaches a second target starting voltage VtPGM, and recording the required charges as second charges; and adding charges to the floating gate of the third simulation storage subunit until the control gate voltage of the third simulation storage subunit reaches the second target starting voltage VtPGM, and recording the required charges as third charges.
In a specific application scenario, the storage unit coupling simulation method may include the following steps.
Step 1, obtaining a first target turn-on voltage VtERS and a second target turn-on voltage VtPGM through a IDVG curve in the WAT data.
And step 2, initializing all simulation memory cells in the simulation memory cell array, and setting the charge of the floating gate FG to 0.
And step 3, erasing all the simulation memory cells in the simulation memory cell array until the control gate voltage of the center simulation memory cell reaches a first target starting voltage.
And step 4, writing charges into the central simulation memory cell to enable the control gate voltage to reach the second target starting voltage VtPGM.
And step 5, obtaining a first charge fg_charge_A required by the control gate voltage of the first simulation storage subunit to reach the second target starting voltage VtPGM.
And 6, writing the first charge fg_charge_A into the two first simulation memory sub-units, and reading the voltage Vt_ centerA of the control gate of the central simulation memory unit at the moment.
And 7, obtaining a second charge fg_charge_b required by the control gate voltage of the second simulation memory subunit to reach the second target starting voltage VtPGM.
And 8, writing the first charge fg_charge_A and the second charge fg_charge_B into two first simulation memory sub-units and one second simulation memory sub-unit, and reading the voltage Vt_ centerB of the control gate of the central simulation memory unit at the moment.
And 9, obtaining a third charge fg_charge_C required by the control gate voltage of the third simulation memory subunit to reach the second target starting voltage VtPGM.
And 10, substituting the first charge fg_charge_A, the second charge fg_charge_B and the third charge fg_charge_C into two first simulation storage subunits, one second simulation storage subunit and two third simulation storage subunits adjacent to the second simulation storage subunit respectively, and reading the voltage Vt_ centerC of the control gate of the central simulation storage unit at the moment.
And step 11, calculating the interference of the first simulation storage subunit, one of the second simulation storage subunits and two third simulation storage subunits adjacent to the second simulation storage subunit on the central simulation storage unit. The specific calculation of the interference can be found by referring to equations (1) - (4).
And traversing each storage unit array by taking each storage unit in the memory as a central simulation storage unit so as to obtain the interference of each storage unit.
For more specific implementation manners of the embodiments of the present application, please refer to the foregoing embodiments, and the details are not repeated here.
Referring to fig. 8, fig. 8 shows a memory cell coupling simulation apparatus 80, and the memory cell coupling simulation apparatus 80 may include:
An erasing module 801, configured to erase the array of dummy memory cells until the control gate voltage of the center dummy memory cell reaches a first target on voltage;
A first writing module 802, configured to write to the central emulation memory cell until the control gate voltage of the central emulation memory cell reaches a second target turn-on voltage;
A second writing module 803, configured to write the first dummy memory cell according to the first charge, obtain a first voltage of the control gate of the center dummy memory cell, and write the second dummy memory cell according to the second charge, obtain a second voltage of the control gate of the center dummy memory cell, where the first dummy memory cell is a cell adjacent to the center dummy memory cell in the row direction, and the second dummy memory cell is a cell adjacent to the center dummy memory cell in the column direction;
The interference calculation module 804 is configured to calculate the interference of the first dummy memory cell and the second dummy memory cell to the central dummy memory cell according to the second target on voltage, the first voltage, and the second voltage.
In a specific implementation, the memory cell coupling simulation device 80 may correspond to a Chip having a memory cell coupling simulation function in a terminal device, for example, a System-On-a-Chip (SOC), a baseband Chip, etc.; or the terminal equipment comprises a chip module with a memory unit coupling simulation function; or corresponds to a chip module having a chip with a data processing function or corresponds to a terminal device.
Other relevant descriptions regarding the memory cell coupling simulation 80 may refer to those in the foregoing embodiments, and are not repeated here.
With respect to each of the apparatuses and each of the modules/units included in the products described in the above embodiments, it may be a software module/unit, a hardware module/unit, or a software module/unit, and a hardware module/unit. For example, for each device or product applied to or integrated on a chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least some modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the remaining (if any) part of modules/units may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module/unit contained in the device and product can be realized in a hardware manner such as a circuit, different modules/units can be located in the same component (such as a chip, a circuit module and the like) or different components of the chip module, or at least part of the modules/units can be realized in a software program, the software program runs on a processor integrated in the chip module, and the rest (if any) of the modules/units can be realized in a hardware manner such as a circuit; for each device, product, or application to or integrated with the terminal device, each module/unit included in the device may be implemented in hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal device, or at least some modules/units may be implemented in a software program, where the software program runs on a processor integrated within the terminal device, and the remaining (if any) some modules/units may be implemented in hardware such as a circuit.
The embodiment of the application also discloses a storage medium which is a computer readable storage medium and is stored with a computer program, and the computer program can execute the steps of the method in the previous embodiment when running. The storage medium may include Read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic or optical disks, and the like. The storage medium may also include non-volatile memory (non-volatile) or non-transitory memory (non-transitory) or the like.
It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship.
The term "plurality" as used in the embodiments of the present application means two or more.
The first, second, etc. descriptions in the embodiments of the present application are only used for illustrating and distinguishing the description objects, and no order is used, nor is the number of the devices in the embodiments of the present application limited, and no limitation on the embodiments of the present application should be construed.
The "connection" in the embodiment of the present application refers to various connection manners such as direct connection or indirect connection, so as to implement communication between devices, which is not limited in the embodiment of the present application.
The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions described in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired or wireless means.
It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus and system may be implemented in other manners. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only one logic function division, and other division modes can be adopted in actual implementation; for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may be physically included separately, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform part of the steps of the method according to the embodiments of the present application.
Although the present application is disclosed above, the present application is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the application, and the scope of the application should be assessed accordingly to that of the appended claims.
Claims (14)
1. A memory cell coupling simulation method, comprising:
Erasing the simulation memory cell array until the control gate voltage of the central simulation memory cell reaches a first target starting voltage;
Writing the central simulation memory unit until the control gate voltage of the central simulation memory unit reaches a second target starting voltage;
Writing a first simulation memory cell according to a first charge to obtain a first voltage of a control gate of the center simulation memory cell, and writing a second simulation memory cell according to a second charge to obtain a second voltage of the control gate of the center simulation memory cell, wherein the first simulation memory cell and the second simulation memory cell are cells adjacent to the center simulation memory cell in row and column directions respectively;
And calculating the interference of the first simulation memory unit and the second simulation memory unit to the central simulation memory unit according to the second target starting voltage, the first voltage and the second voltage.
2. The method of claim 1, wherein the first target turn-on voltage represents a turn-on voltage corresponding to a floating gate of a memory cell to be simulated after a charge is removed, and the second target turn-on voltage represents a turn-on voltage corresponding to a floating gate of the memory cell to be simulated after a charge is placed in the floating gate.
3. The memory cell coupling simulation method according to claim 1 or 2, wherein the step of acquiring the first charge and the second charge includes:
and calculating first charges and second charges which are required to be written when the control gate voltages of the first simulation memory cell and the second simulation memory cell reach the second target starting voltage.
4. The memory cell coupling simulation method of claim 3 wherein the calculating the first charge and the second charge to be written when the control gate voltages of the first and second simulated memory cells reach the second target turn-on voltage comprises:
Adding charges to the floating gate of the first simulation memory cell until the control gate voltage of the first simulation memory cell reaches the second target starting voltage, and recording the required charges as the first charges;
and adding charges to the floating gate of the second simulation memory cell until the control gate voltage of the second simulation memory cell reaches the second target starting voltage, and recording the required charges as the second charges.
5. The memory cell coupling simulation method of any of claims 1-2 or 4, wherein the first simulated memory cell comprises at least one first simulated memory subunit adjacent to the central simulated memory cell in a row direction, the writing the first simulated memory cell in accordance with the first charge comprising:
And writing the at least one first simulation storage subunit according to the first charges, and recording the first voltage of the control gate of the central simulation storage subunit after the writing is completed.
6. The memory cell coupling simulation method of claim 5, wherein the second simulation memory cell comprises at least one second simulation memory subunit adjacent to the center simulation memory cell in a column direction, and a third simulation memory subunit adjacent to the at least one second simulation memory subunit in a row direction, respectively.
7. The method of claim 6, further comprising, prior to writing to the second dummy memory cell according to the second charge:
Adding charges to the floating gate of the second simulation storage subunit until the control gate voltage of the second simulation storage subunit reaches the second target starting voltage, and recording the required charges as the second charges;
and adding charges to the floating gate of the third simulation storage subunit until the control gate voltage of the third simulation storage subunit reaches the second target starting voltage, and recording the required charges as third charges.
8. The method of claim 7, wherein writing the second dummy memory cell according to the second charge, obtaining the second voltage of the control gate of the center dummy memory cell comprises:
Writing at least one second simulation storage subunit according to the second charge, and recording a second voltage of a control gate of the center simulation storage subunit after writing is completed;
And writing part or all of the third simulation storage sub-units according to the third charges, and recording the third voltage of the control gate of the center simulation storage unit after the writing is completed.
9. The memory cell coupling simulation method of claim 8, wherein the calculating the interference of the first and second simulated memory cells to the center simulated memory cell based on the second target turn-on voltage, the first voltage, and the second voltage comprises:
Calculating a first difference value between the second voltage and the first voltage as interference of the second simulation storage subunit to the central simulation storage unit;
And calculating a second difference value between the third voltage and the second voltage as interference of the third simulation storage subunit to the central simulation storage unit.
10. The memory cell coupling simulation method of any of claims 1-2, 4, 6-9, wherein the calculating the first simulated memory cell and the second simulated memory cell interference with the center simulated memory cell based on the second target turn-on voltage, the first voltage, and the second voltage comprises:
And calculating a third difference value between the first voltage and the second target starting voltage as interference of the first simulation memory unit to the central simulation memory unit.
11. The memory cell coupling simulation method according to claim 1, further comprising, before erasing the simulated memory cell array:
initializing the simulated memory cell array to make charges in floating gates of each simulated memory cell in the simulated memory cell array zero.
12. A memory cell coupling simulation apparatus, comprising:
the erasing module is used for erasing the simulation memory cell array until the control gate voltage of the center simulation memory cell reaches a first target starting voltage;
the first writing module is used for writing the central simulation memory unit until the control gate voltage of the central simulation memory unit reaches a second target starting voltage;
The second writing module is used for writing the first simulation memory unit according to the first charge, obtaining the first voltage of the control gate of the center simulation memory unit, writing the second simulation memory unit according to the second charge, and obtaining the second voltage of the control gate of the center simulation memory unit, wherein the first simulation memory unit and the second simulation memory unit are units adjacent to the center simulation memory unit in the row direction and the column direction respectively;
And the interference calculation module is used for calculating the interference of the first simulation memory unit and the second simulation memory unit to the central simulation memory unit according to the second target starting voltage, the first voltage and the second voltage.
13. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program when run by a processor performs the steps of the storage unit coupling simulation method of any of claims 1 to 11.
14. A computing device comprising a memory and a processor, the memory having stored thereon a computer program executable on the processor, wherein the processor, when executing the computer program, performs the steps of the storage unit coupling simulation method of any of claims 1 to 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410465261.4A CN118070717A (en) | 2024-04-17 | 2024-04-17 | Storage unit coupling simulation method and device, storage medium and computing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410465261.4A CN118070717A (en) | 2024-04-17 | 2024-04-17 | Storage unit coupling simulation method and device, storage medium and computing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118070717A true CN118070717A (en) | 2024-05-24 |
Family
ID=91107909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410465261.4A Pending CN118070717A (en) | 2024-04-17 | 2024-04-17 | Storage unit coupling simulation method and device, storage medium and computing equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118070717A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1750006A (en) * | 2004-09-13 | 2006-03-22 | 中国科学院微电子研究所 | A kind of quick simulator and method based on static RAM |
| US7925936B1 (en) * | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
| CN103811074A (en) * | 2012-11-15 | 2014-05-21 | 建兴电子科技股份有限公司 | Storage state decision method of flash memory and related system |
| CN104733045A (en) * | 2015-03-23 | 2015-06-24 | 上海华力微电子有限公司 | Double-bit flash memory, and programming, erasing and reading method thereof |
-
2024
- 2024-04-17 CN CN202410465261.4A patent/CN118070717A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1750006A (en) * | 2004-09-13 | 2006-03-22 | 中国科学院微电子研究所 | A kind of quick simulator and method based on static RAM |
| US7925936B1 (en) * | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
| CN103811074A (en) * | 2012-11-15 | 2014-05-21 | 建兴电子科技股份有限公司 | Storage state decision method of flash memory and related system |
| CN104733045A (en) * | 2015-03-23 | 2015-06-24 | 上海华力微电子有限公司 | Double-bit flash memory, and programming, erasing and reading method thereof |
Non-Patent Citations (2)
| Title |
|---|
| 张司琪;孔令军;张顺外;张南;: "MLC型NAND闪存中基于MI异构的Polar码优化", 应用科学学报, no. 03, 30 May 2020 (2020-05-30), pages 431 - 440 * |
| 张旋;慕建君;焦晓鹏;: "一种MLC闪存存储系统的比特翻转译码算法", 西安电子科技大学学报, vol. 44, no. 05, 13 April 2017 (2017-04-13), pages 75 - 80 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7784003B2 (en) | Estimation of process variation impact of slack in multi-corner path-based static timing analysis | |
| US10007492B2 (en) | System and method for automatically generating device drivers for run time environments | |
| CN113076227A (en) | MCU verification method, system and terminal equipment | |
| CN108133732A (en) | Performance test methods, device, equipment and the storage medium of flash chip | |
| EP3822840B1 (en) | Method, apparatus, computer storage medium and program for authenticating a chip design | |
| US8271252B2 (en) | Automatic verification of device models | |
| CN107239392A (en) | A kind of method of testing, device and terminal | |
| CN111708284B (en) | Simulation test method, device, equipment and storage medium for fuel cell system | |
| US20210151124A1 (en) | Genetic variation identification method, genetic variation identification apparatuses, and storage medium | |
| CN110197183A (en) | A kind of method, apparatus and computer equipment of Image Blind denoising | |
| CN109189621A (en) | A kind of test method and system of NVMe SSD hot plug | |
| KR20210014561A (en) | Method and apparatus for extracting image data in parallel from multiple convolution windows, device, and computer-readable storage medium | |
| CN114707453A (en) | Chip function verification method and device, electronic equipment and storage medium | |
| CN111723020A (en) | Method, device and equipment for testing electric energy meter testing software | |
| CN115048888A (en) | Integrated circuit verification method, integrated circuit verification device, simulation system, electronic device and medium | |
| CN110516334B (en) | Convolution calculation simulation test method and device based on hardware environment and related equipment | |
| CN114548027A (en) | Method for tracking signal in verification system, electronic device and storage medium | |
| CN118070717A (en) | Storage unit coupling simulation method and device, storage medium and computing equipment | |
| CN113484585A (en) | Method for measuring chip voltage drop and related product | |
| CN108021735A (en) | Analogy method, host computer, real-time simulation machine and the battery analog system of battery | |
| US8281263B2 (en) | Propagating design tolerances to shape tolerances for lithography | |
| US20090007034A1 (en) | Device, System, and Method for Correction of Integrated Circuit Design | |
| CN116343888A (en) | Verification method of memory chip, electronic equipment and memory medium | |
| CN115718692A (en) | Solid state disk evaluation method and device based on firmware simulation and readable storage medium | |
| CN116739094A (en) | Quantum circuit crosstalk optimization method and device, storage medium and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |