CN118053899A

CN118053899A - High electron mobility transistor structure and method of fabricating the same

Info

Publication number: CN118053899A
Application number: CN202211405901.XA
Authority: CN
Inventors: 林鑫成; 黄嘉庆
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2022-11-10
Filing date: 2022-11-10
Publication date: 2024-05-17

Abstract

The invention discloses a high electron mobility transistor structure and a manufacturing method thereof, comprising the following steps: a compound semiconductor channel layer disposed on the substrate; a compound semiconductor barrier layer disposed on the compound semiconductor channel layer; a compound semiconductor cover layer disposed on the compound semiconductor barrier layer, the compound semiconductor cover layer including a first block and a second block arranged along a first direction, and a first gap being provided between the first block and the second block; a gate electrode disposed on the compound semiconductor cap layer; and source and drain electrodes disposed on the compound semiconductor barrier layer, the source and drain electrodes being arranged along the second direction and being located on both sides of the compound semiconductor cap layer, respectively.

Description

High electron mobility transistor structure and method of fabricating the same

Technical Field

The present invention relates to semiconductor devices, and more particularly, to an integrated enhancement mode and depletion mode high electron mobility transistor structure and method of fabricating the same.

Background

In alternating current/direct current (AC/DC) power converter and driver applications, it is often necessary to use junction field-effect transistor (JFET) or depletion-mode field-effect transistor (D-mode FET) to provide start-up (start-up) functionality. However, the conventional junction field effect transistor requires a well region to clamp (pin off) voltage, and the well region has high sensitivity to process variation, which easily causes the clamp voltage to deviate. In addition, the conventional depletion type field effect transistor is, for example, a depletion type metal-insulator-semiconductor field effect transistor (D-mode MISFET), and the gate structure thereof requires a gate recess (GATE RECESS), however, the etching depth for forming the gate recess is not easy to precisely control, which results in unstable threshold voltage (Vt) of the depletion type MISFET. In addition, interface defects (INTERFACE TRAP) are liable to occur between the gate dielectric layer and the semiconductor layer of the depletion type MISFET, resulting in a reduction in reliability.

Disclosure of Invention

In view of the above, the present invention provides a high electron mobility transistor structure and a method for fabricating the same, so as to solve the above-mentioned problems of the prior art.

According to an embodiment of the present invention, there is provided a high electron mobility transistor structure including a compound semiconductor channel layer disposed on a substrate; a compound semiconductor barrier layer disposed on the compound semiconductor channel layer; a compound semiconductor cover layer arranged on the compound semiconductor barrier layer and comprising a first block and a second block which are arranged along a first direction, wherein a first gap is arranged between the first block and the second block; a gate electrode disposed on the compound semiconductor cap layer; and a source electrode and a drain electrode arranged on the compound semiconductor barrier layer and arranged along a second direction and respectively positioned at two sides of the compound semiconductor cover layer.

According to another embodiment of the present invention, there is provided a method of manufacturing a high electron mobility transistor structure, including: forming a compound semiconductor channel layer on a substrate; forming a compound semiconductor barrier layer on the compound semiconductor channel layer; forming a compound semiconductor cover layer on the compound semiconductor barrier layer, wherein the compound semiconductor cover layer comprises a first block and a second block which are arranged along a first direction, and a first gap is arranged between the first block and the second block; forming a gate electrode on the compound semiconductor cap layer; and forming a source electrode and a drain electrode on the compound semiconductor barrier layer, wherein the source electrode and the drain electrode are arranged along a second direction and are respectively positioned at two sides of the compound semiconductor cover layer.

The technical scheme of the invention has the beneficial effects that: the structure of the high electron mobility transistor can provide a start-up function, and the critical voltage (Vt) of the depletion type high electron mobility transistor can be accurately controlled by controlling the gap width between the blocks of the compound semiconductor cover layer, so that the structure of the high electron mobility transistor has stable and accurate electrical characteristics.

In order to make the features of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

For a better understanding of the present invention, reference should be made to the drawings and to the detailed description thereof when read in light of the accompanying drawings. Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein the present embodiments are illustrated in the accompanying drawings. Furthermore, for the sake of clarity, various features in the drawings may not be drawn to actual scale, and therefore the dimensions of some features in some of the drawings may be exaggerated or reduced in size.

Fig. 1 is a schematic top view of a high electron mobility transistor structure according to an embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of a high electron mobility transistor structure along the section line B-B' of fig. 1 according to an embodiment of the present invention.

FIG. 3 is a view along the line of FIG. 1 according to an embodiment of the present invention cross-sectional schematic of a high electron mobility transistor structure at section line A-A'.

Fig. 4 is a schematic cross-sectional view of a portion of a high electron mobility transistor structure along section line A-A' of fig. 1, according to another embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view of a portion of a high electron mobility transistor structure along section line A-A' of fig. 1, according to yet another embodiment of the present invention.

FIG. 6 is a graph of drain current versus gate voltage for a HEMT structure according to some embodiments of the invention, where the drain current for state 200B is exponentially represented for state 200A.

Fig. 7 and 8 are schematic cross-sectional views along the section line A-A' of fig. 1 of some stages of a method of fabricating a high electron mobility transistor structure according to an embodiment of the present invention.

Fig. 9 is a schematic cross-sectional view of an intermediate stage of a method of fabricating a high electron mobility transistor structure along the cross-sectional line A-A' of fig. 1 according to another embodiment of the present invention.

Reference numerals illustrate:

100 DEG high electron mobility transistor structure

100D··depletion region

100E. Enhanced regions

101. Substrate

102 Seed layer

103 Compound semiconductor channel layer

104. Buffer layer

105/Compound semiconductor Barrier layer

106 High resistance layer

107 Compound semiconductor cap layer

107-1. First block

107-2 Second block

107-3 Third block

107-C1. First linking moiety

108-1. First gap

108-2. Second gap

109 Gate electrode

109-1. First part

109-2. Second part

110 Compound semiconductor material layer

111 Source electrode

112-Patterned block of compound semiconductor material

113 Drain electrode

120 Patterning photoresist

120-1. Opening

121 First patterned photoresist

130 Second patterned photoresist

130-1. Opening

200A, 200B. Curves

S101, S103, S105, S201. Step

W1 & gtfirst block width

W2 & gtsecond block width

W3 & gtthird block width

S1. First gap width

S2. Second gap width

2DEG & two-dimensional electron gas region

C & ltS & gt wire-framed region

Thickness T1, T2

Detailed Description

The invention provides several different embodiments that can be used to implement different features of the invention. For simplicity of explanation, the invention also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of a first feature being formed on or over a second feature may refer to the first feature being in direct contact with the second feature, or may refer to other features being present between the first and second features, such that the first and second features are not in direct contact. Furthermore, various embodiments of the present invention may use repeated reference characters and/or textual notations. These repeated reference characters and marks are used to make the description more concise and clear, rather than to indicate a relationship between different embodiments and/or configurations.

In addition, for the spatially related narrative terms mentioned in the present invention, for example: when "under", "low", "lower", "upper", "top", "bottom" and the like, for ease of description, the description is used to describe one element or feature's relative relationship to another element(s) or feature(s) in the figures. In addition to the orientation shown in the drawings, these spatially dependent terms are also used to describe possible orientations of the semiconductor device in use and operation. With the semiconductor device oriented differently (rotated 90 degrees or other orientations), the spatially relative descriptors describing its orientation should be interpreted in a similar manner.

Although the invention has been described in the language of first, second, third, etc., to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, which does not itself imply any preceding ordinal number or order of manufacture by the element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the embodiments of the present invention.

The terms "about" or "substantially" as referred to herein generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are about amounts, i.e., without a specific recitation of "about" or "substantially," the meaning of "about" or "substantially" may still be implied.

The terms "coupled," "coupled," and "electrically connected," as used herein, are intended to encompass any direct or indirect means of electrical connection. For example, if a first element is coupled to a second element, that connection may be directly to the second element or indirectly to the second element through other means of attachment or connection.

In the present invention, the "compound semiconductor (compound semiconductor)" refers to a compound semiconductor including at least one group III element and at least one group V element. Among them, the group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb). Further, "compound semiconductor" may be a binary compound semiconductor, a ternary compound semiconductor, or a quaternary compound semiconductor, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (inaias), gallium indium arsenide (InGaAs), the like, or a combination of the above compounds, but are not limited thereto. In addition, dopants may be included in the compound semiconductor as required, and are compound semiconductors having a specific conductivity type, such as n-type or p-type compound semiconductors. Hereinafter, the compound semiconductor may also be referred to as a III-V semiconductor.

While the invention is described below with respect to specific embodiments, the inventive principles of this patent disclosure are applicable to other embodiments as well. Furthermore, specific details are omitted so as not to obscure the spirit of the present invention, and such omitted details are within the knowledge of those skilled in the art.

The present invention relates to a high electron mobility transistor (high electron mobility transistor, HEMT) structure integrating enhancement-mode and depletion-mode and a method for fabricating the same, wherein the high electron mobility transistor structure does not require additional process steps, and can achieve the effect of lateral depletion by using the layout structure of a compound semiconductor cap layer, so that the high electron mobility transistor structure of the present invention can provide a start-up function, and can precisely control the threshold voltage (Vt) of the depletion-type high electron mobility transistor by controlling the gap width between blocks of the compound semiconductor cap layer. Therefore, compared with the prior depletion type MISFET (D-mode MISFET), the high electron mobility transistor structure of the invention can stably and accurately control the critical voltage (Vt) of the depletion type MISFET, thereby accurately controlling the clamping voltage when providing the start-up function, and simultaneously overcoming the interface defect (INTERFACE TRAP) of the gate dielectric layer and the semiconductor layer of the prior depletion type MISFET, thereby improving the reliability.

Fig. 1 is a schematic top view of a hemt structure according to an embodiment of the present invention, wherein hemt structure 100 comprises a substrate 101, and the material of substrate 101 may comprise ceramic, silicon carbide (SiC), aluminum nitride (AlN), sapphire (sapphire), or silicon according to some embodiments. When the substrate 101 is made of a material with high hardness, high thermal conductivity, and low electrical conductivity, such as a ceramic substrate, the high electron mobility transistor structure 100 is more suitable for use in high voltage semiconductor devices. The high hardness, high thermal conductivity, and low electrical conductivity mentioned above are compared to single crystal silicon substrates, and the high voltage semiconductor device refers to a semiconductor device having an operating voltage higher than 50V. In some embodiments, the substrate 101 may be a semiconductor-on-insulator (semiconductor on insulator, SOI) substrate. In other embodiments, the substrate 101 may be provided by a composite substrate (also referred to as a QST substrate) formed by wrapping a core substrate with a composite material layer, wherein the core substrate comprises ceramic, silicon carbide, aluminum nitride, sapphire or silicon, the composite material layer comprises an insulating material layer and a semiconductor material layer, wherein the insulating material layer may be single-layer or multi-layer silicon oxide, silicon nitride or silicon oxynitride, the semiconductor material layer may be silicon or polysilicon, and the composite material layer on the back of the core substrate is removed through a thinning process, such as a polishing or etching process, so that the back of the core substrate is exposed.

With continued reference to fig. 1, from a top view, the hemt structure 100 comprises a compound semiconductor barrier layer 105 (hereinafter referred to simply as a barrier layer) disposed over the substrate 101, a compound semiconductor cap layer 107 (hereinafter referred to simply as a cap layer) disposed over the barrier layer 105, and the cap layer 107 comprises a plurality of blocks, such as a first block 107-1, a second block 107-2, a third block 107-3, etc., according to some embodiments of the present invention, although five blocks are illustrated in fig. 1, in fact more or fewer blocks may be disposed for the cap layer 107 depending on various requirements of the hemt structure 100. The blocks of the cap layer 107 are arranged along a first direction (e.g., the X-direction) and are separated from each other with gaps, such as a first gap 108-1 between the first block 107-1 and the second block 107-2, a second gap 108-2 between the second block 107-2 and the third block 107-3, and so on. In some embodiments, a portion of the surface of the barrier layer 105 may be exposed through the first gap 108-1, the second gap 108-2, and other gaps, and according to embodiments of the present invention, the widths of the first gap 108-1, the second gap 108-2, and other gaps in a first direction (e.g., X-direction), for example, the first gap width S1, the second gap width S2, and other gap widths may range from about 0.01 micrometers (μm) to about 1 μm, and the first gap width S1, the second gap width S2, and other gap widths may be set to be the same or different depending on electrical requirements, such that the gap widths may allow the high electron mobility transistor structure 100 to achieve a desired lateral depletion effect.

Furthermore, according to an embodiment of the present invention, the widths of the first, second, third and other blocks 107-1, 107-2, 107-3 in the first direction (e.g., X-direction), such as the first, second, third and other block widths W1, W2, W3, are determined according to the ranges of the first, second and other gap widths S1, S2. The ratio of the block width to the gap width may be smaller as the gap width is smaller, and the higher the effect of the high electron mobility transistor structure (HEMT) 100 to achieve the desired lateral depletion is, the device can be turned off as each gap width is smaller than 1 μm. In some embodiments, the gap width is, for example, 0.01 μm to 0.5 μm, and the ratio of the block width to the gap width is 5 to 200, so that the HEMT 100 can achieve the effect of lateral depletion to rapidly turn off the device. In one embodiment, the device is turned off when the gap width is 0.4 μm and the ratio of the block width to the gap width is 5, and the block width is 2.0 μm. In another embodiment, the element is turned off only when the gap width is 0.5 μm and the ratio of the block width to the gap width is 179, and the block width is 89.5 μm. In addition, when the width of each gap is smaller and the width of each block is larger, the ratio of the width of each block to the width of each gap is larger, so that the HEMT 100 can achieve the effect of lateral depletion more quickly, the device is turned off more quickly, the required threshold voltage (Vt) is smaller, and the size of the threshold voltage (Vt) can be adjusted according to the application requirement, so long as the device can be turned off.

In some embodiments, the first, second, third, and other block widths W1, W2, W3 may range from about 1 micrometer (μm) to about 500 μm, depending on the respective gap widths, e.g., the respective gap widths may range from about 0.01 micrometers (μm) to about 5 μm. In addition, the first block width W1, the second block width W2, the third block width W3 and other block widths may be set to be the same or different according to the electrical requirements, and the block widths adjusted according to the gap width may enable the high electron mobility transistor structure 100 to achieve the desired lateral depletion effect. In addition, the embodiment of the present invention can adjust the width of each block and the width of each gap according to various electrical requirements (such as clamping voltage, threshold voltage, drain current, etc.) of the high electron mobility transistor structure 100, so that the high electron mobility transistor structure 100 has higher product flexibility. In some embodiments, the first gap width S1 is 0.01 μm to 0.5 μm in the first direction (e.g., X direction), and the ratio of the first block width W1 to the first gap width S1 may be 5 to 200. In some embodiments, the second block width W2 may be less than or equal to the first block width W1, and the first gap width S1 and the second gap width S2 may each be 0.01 μm to 0.5 μm, and a ratio of the second block width W2 to the first gap width S1 or a ratio of the second block width W2 to the second gap width S2 may be 5 to 200. In addition, the ratio of the third block width W3 to the second gap width S2 may be 5 to 200.

Still referring to fig. 1, the hemt structure 100 further includes a gate electrode 109 disposed on the cap layer 107. In some embodiments, the gate electrode 109 may continuously overlie the first region 107-1, the first gap 108-1, the second region 107-2, the second gap 108-2, the third region 107-3, other regions, and other gaps of the cap layer 107. In other embodiments, the gate electrode 109 may include a plurality of portions separated from each other along a first direction (e.g., X-direction), and each of the portions is disposed directly above the first region 107-1, the second region 107-2, the third region 107-3, and other regions of the cap layer 107. In addition, the high electron mobility transistor structure 100 further includes a source electrode 111 and a drain electrode 113 disposed on the barrier layer 105, wherein the source electrode 111 and the drain electrode 113 are arranged along the second direction (e.g. Y direction) and are respectively located at two sides of the cap layer 107 and are respectively located at two sides of the gate electrode 109, and long axes of the source electrode 111 and the drain electrode 113 extend along the first direction (e.g. X direction) to form a continuous electrode pattern.

Fig. 2 is a schematic cross-sectional view of the hemt structure along the section line B-B' of fig. 1 according to an embodiment of the present invention, and as shown in fig. 2, the hemt structure 100 further includes a seed layer (nucleation layer) 102, a buffer layer 104, and a high-resistance layer (HIGH RESISTANCE LAYER) (or referred to as an electrical isolation layer) 106 sequentially stacked on the substrate 101 from bottom to top in some embodiments. The materials of the seed layer 102, the buffer layer 104, and the high resistance layer 106 comprise compound semiconductors, and in some embodiments, the seed layer 102 is, for example, an aluminum nitride (AlN) layer, the buffer layer 104 may be a superlattice (superlattice, SL) structure, for example, comprising a plurality of alternating layers of aluminum gallium nitride (AlGaN) layers and aluminum nitride (AlN) layers, and the high resistance layer 106 is, for example, a carbon doped gallium nitride (c-GaN) layer, but is not limited thereto. In addition, the high electron mobility transistor structure 100 further includes a compound semiconductor channel layer 103 (hereinafter, may be simply referred to as a channel layer) disposed between the high resistance layer 106 and the barrier layer 105. In some embodiments, the channel layer 103 is, for example, an undoped compound semiconductor layer (e.g., an undoped gallium nitride (u-GaN) layer), the barrier layer 105 is, for example, a compound semiconductor layer (e.g., an aluminum gallium nitride (AlGaN) layer) having a larger energy gap than the channel layer 103, and the cap layer 107 is, for example, a p-type compound semiconductor layer (e.g., a p-type gallium nitride (p-GaN) layer), but is not limited thereto. The composition and structural configuration of the above-described compound semiconductor layers of the high electron mobility transistor structure 100 may be dependent on the requirements of various semiconductor devices.

As shown in fig. 2, the gate electrode 109 is disposed on the cap layer 107, and the source electrode 111 and the drain electrode 113 are disposed on the barrier layer 105 and are respectively located at two sides of the gate electrode 109, wherein the distance between the drain electrode 113 and the gate electrode 109 may be greater than the distance between the source electrode 111 and the gate electrode 109. The channel layer 103 and the barrier layer 105 extend between the source electrode 111 and the drain electrode 113 along the second direction (e.g., Y direction), and electrons are collected at the heterojunction between the channel layer 103 and the barrier layer 105 due to the piezoelectric effect by stacking the channel layer 103 and the barrier layer 105 on each other due to the discontinuous energy gap between the channel layer 103 and the barrier layer 105, thereby generating a thin layer with high electron mobility, i.e., a two-dimensional electron gas region 2DEG. The materials of the gate electrode 109, the source electrode 111, and the drain electrode 113 may include conductive materials, such as metals, alloys, metal nitrides, or semiconductor materials. In some embodiments, the metal may comprise gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), among other suitable conductive materials, or combinations of the foregoing. In addition, the gate electrode 109 may make a Schottky contact with the cap layer 107, while the source electrode 111 and the drain electrode 113 may make an ohmic contact with the underlying semiconductor layers (e.g., the channel layer 103 and the barrier layer 105) (ohmic contact).

For an enhanced (E-mode) (or normally off) High Electron Mobility Transistor (HEMT), when no voltage is applied to the gate electrode 109, the region covered by the cap layer 107 does not form a two-dimensional electron gas (as shown in fig. 2), which can be regarded as a 2DEG cut region, and the source electrode 111 and the drain electrode 113 are not turned on. When a positive voltage is applied to the gate electrode 109, the region covered by the cap layer 107 forms a two-dimensional electron gas, so that a continuous two-dimensional electron gas region is generated between the source electrode 111 and the drain electrode 113, and conduction is achieved between the source electrode 111 and the drain electrode 113.

In addition, for a depletion mode (D-mode) (or referred to as normal on) High Electron Mobility Transistor (HEMT), when no voltage or only a weak positive voltage is applied to the gate electrode 109, a region not covered by the cap layer 107 forms a two-dimensional electron gas, so that a partial region between the source electrode 111 and the drain electrode 113 generates a continuous two-dimensional electron gas region, and the source electrode 111 and the drain electrode 113 are turned on. When a negative voltage is applied to the gate electrode 109, the two-dimensional electron gas in the region not covered by the cap layer 107 is blocked, which is regarded as a 2DEG blocking region, and the source electrode 111 and the drain electrode 113 are not conducted.

Fig. 3 is a schematic cross-sectional view of the hemt structure along the section line A-A' of fig. 1 according to an embodiment of the present invention, and as shown in fig. 3, the hemt structure 100 includes an enhanced (E-mode) region 100E corresponding to each region of the cap layer 107, for example, the first region 107-1 and the second region 107-2, and a depletion (D-mode) region 100D corresponding to a gap, for example, the first gap 108-1, between each region of the cap layer 107. According to the embodiment of the present invention, when no voltage is applied to the gate electrode 109, the heterojunction between the channel layer 103 and the barrier layer 105 of the depletion region 100D is generated by the two-dimensional electron gas region 2DEG, and the heterojunction between the channel layer 103 and the barrier layer 105 of the enhancement region 100E is not generated by the two-dimensional electron gas region 2 DEG. In addition, in the present embodiment, the gate electrode 109 includes a plurality of portions separated from each other, such as the first portion 109-1 and the second portion 109-2, respectively disposed directly above the first region 107-1 and the second region 107-2 of the cap layer 107, and the gate electrode 109 is not filled in the first gap 108-1.

Referring to fig. 1 and 3, in the operation of the hemt structure 100 according to the embodiment of the invention, when no voltage (or only a weak positive voltage) is applied to the gate electrode 109 and a positive voltage is applied to the drain electrode 113, a current can flow from the drain electrode 113 to the source electrode 111 through the two-dimensional electron gas region 2DEG under the first gap 108-1, and the hemt structure 100 is considered to be in a conductive state.

In contrast, when a negative voltage is applied to the gate electrode 109, an electric field is generated to the two-dimensional electron gas region 2DEG under the first gap 108-1, such that the two-dimensional electron gas region 2DEG under the first gap 108-1 is influenced by the electric field to disappear, and thus even if a positive voltage is applied to the drain electrode 113, a current cannot flow from the drain electrode 113 to the source electrode 111 through the lower portion of the first gap 108-1, and the high electron mobility transistor structure 100 is considered to be in an off state.

Therefore, according to the present embodiment of the present invention, the layout structure of the cap layer 107 in the enhancement region 100E and the depletion region 100D is utilized, so that the region of the channel layer 103 directly under the first region 107-1 and the second region 107-2 of the cap layer 107 forms the channel region of the enhancement HEMT, and the other region of the channel layer 103 directly under the first gap 108-1 of the cap layer 107 forms the channel region of the depletion HEMT or the Junction Field Effect Transistor (JFET), thereby the present invention achieves the effect of lateral depletion of the high electron mobility transistor structure 100, and further provides the start function in the application of an alternating current/direct current (AC/DC) power converter and a driver.

Fig. 4 is a schematic cross-sectional view of a portion of a hemt structure along the section line A-A' of fig. 1, which is another structure illustrating the frame line region C of fig. 3, according to another embodiment of the present invention. The structure of the frame line region C shown in fig. 3,4 and 5 may be regarded as a repeating unit of the high electron mobility transistor structure 100 according to an embodiment of the present invention, and the repeating unit may be repeatedly arranged along a first direction (for example, an X direction) on the substrate 101 to form the high electron mobility transistor structure. Referring to fig. 4, in this embodiment, the cap layer 107 may further include a first connection portion 107-C1 disposed between the first region 107-1 and the second region 107-2, and a thickness T2 of the first connection portion 107-C1 is smaller than a thickness T1 of each of the first region 107-1 and the second region 107-2. In some embodiments, the thickness T2 of the first connection portion 107-C1 is about 10 nanometers (nm) to about 100nm, and the thickness T1 of each of the first and second regions 107-1, 107-2 is about 50 nanometers (nm) to about 150nm. According to some embodiments of the present invention, since the thickness T2 of the first connection portion 107-C1 is 5% to 70% of the thickness T1 of the first area 107-1 or the second area 107-2, the first connection portion 107-C1 does not completely intercept the two-dimensional electron gas region 2DEG under the first gap 108-1. Since there is still a sufficient space between the first region 107-1 and the second region 107-2 for the first gap 108-1, and when a sufficient negative voltage is applied to the gate electrode 109, the two-dimensional electron gas region 2DEG under the first gap 108-1 and the first connection portion 107-C1 is still vanished by the electric field from the gate electrode 109, so that even if a positive voltage is applied to the drain electrode 113, current cannot flow from the drain electrode 113 to the source electrode 111 through the first gap 108-1 and the channel layer 103 under the first connection portion 107-C1, and the high electron mobility transistor structure 100 is still in an off state and has a similar activation function as provided by a depletion HEMT or Junction Field Effect Transistor (JFET). In addition, as shown in fig. 4, in this embodiment, the gate electrode 109 includes a plurality of separated portions, such as a first portion 109-1 and a second portion 109-2, respectively disposed directly above the first region 107-1 and the second region 107-2 of the cap layer 107, and the gate electrode 109 is not filled in the first gap 108-1, i.e. the gate electrode 109 does not cover the first connection portion 107-C1. In addition, referring to fig. 1 and 4, a second connection portion (not shown) may be disposed between the second region 107-2 and the third region 107-3 of the cap layer 107, and the thickness of the second connection portion is smaller than the respective thicknesses of the second region 107-2 and the third region 107-3. In some embodiments, the thicknesses of the first connection portion 107-C1 and the second connection portion may be set to be the same or different according to the electrical requirements of the hemt structure 100.

Fig. 5 is a schematic cross-sectional view of a portion of a hemt structure along the section line A-A' of fig. 1, which is another structure illustrating the frame line region C of fig. 3, according to another embodiment of the present invention. In this embodiment, a portion of the surface of the barrier layer 105 is exposed through the first gap 108-1, and the gate electrode 109 continuously covers the first region 107-1 of the cap layer 107, the portion of the surface of the barrier layer 105, and the second region 107-2 of the cap layer 107. In one embodiment, the gate electrode 109 may fill the first gap 108-1 and have a planar top surface. In another embodiment, the gate electrode 109 may be formed on the sidewall and bottom surfaces of the first gap 108-1 in a conformal manner (conformally) with a top surface having a concave-convex profile.

Fig. 6 is a graph of drain current versus gate voltage for a high electron mobility transistor structure according to some embodiments of the present invention, with drain current Id on the vertical axis in amperes (a) and gate voltage Vg on the horizontal axis in volts (V). The drain current of the curve 200A of the drain current of the curve 200B of fig. 6 (B) is shown in an exponential form, so that the trend of each curve in the curve 200B in the interval of the drain current Id of 0A to 0.2A is easier to observe. The curves of fig. 6 represent the characteristics of drain current versus gate voltage for some embodiments of the high electron mobility transistor structure having different sized gap widths S and block widths W of the cap layer 107, respectively, the gap widths S and block widths W of the cap layer 107 of these embodiments are in micrometers (μm), respectively: s=0.8, w=89.2; s=0.5, w=89.5; s=0.8, w=2; s=0.5, w=2; s=0.4, w=2. As can be seen from the curves 200A and 200B of fig. 6, the high-electron-mobility transistor structure with the cap layer having the larger block width W (e.g., w=89.2, w=89.5) can make the drain current cut off faster when the gate electrode is applied with less negative voltage, and the high-electron-mobility transistor structure with the cap layer having the smaller gap width S (e.g., s=0.4, s=0.5) can make the cut-off drain current drop lower when the gate electrode is applied with the same negative voltage. Therefore, according to the embodiment of the invention, the gap width and the block width of the cover layer can be adjusted to enable the high electron mobility transistor structure to have different electrical characteristics so as to improve the flexibility of the high electron mobility transistor structure applied to different electronic products.

Fig. 7 and 8 are schematic cross-sectional views along the section line A-A' of fig. 1 of some stages of a method of fabricating a high electron mobility transistor structure according to an embodiment of the present invention. As shown in fig. 7, first, a seed layer 102, a buffer layer 104, a high-resistance layer 106, a channel layer 103, a barrier layer 105 and a compound semiconductor material layer 110 are sequentially stacked on a substrate 101, wherein the compound semiconductor material layer 110 is used to form a cap layer 107 in a subsequent process, and the materials of the layers are compound semiconductors, the composition of which can be described with reference to fig. 2, and the layers can be sequentially formed on the substrate 101 from bottom to top by using different epitaxial growth processes, respectively. Next, a patterned photoresist 120 is formed on the compound semiconductor material layer 110, the patterned photoresist 120 having openings 120-1 corresponding to predetermined regions of the cap layer, e.g., the first gaps 108-1.

Referring still to fig. 7, in step S101, an etchant is removed through the opening 120-1 of the patterned photoresist 120 by using an etching process to remove the portion of the compound semiconductor material layer 110 not covered by the patterned photoresist 120, so as to form each region and each gap of the cap layer 107, for example, the first region 107-1, the second region 107-2 and the first gap 108-1.

Next, referring to fig. 8, in step S103, compound semiconductor material is epitaxially grown in the first gap 108-1 by using an epitaxial growth process to form each connection portion of the cap layer 107, for example, a first connection portion 107-C1, wherein the thickness of the first connection portion 107-C1 is smaller than the thickness of each of the first region 107-1 and the second region 107-2. Thereafter, in step S105, a gate electrode 109 is formed on the cap layer 107 using deposition, photolithography and etching processes, and in this embodiment, the gate electrode 109 continuously covers the first region 107-1, the first connection portion 107-C1 and the second region 107-2 of the cap layer 107 and fills the first gap 108-1 to have a flat top surface. Thereafter, referring to fig. 1, a source electrode 111 and a drain electrode 113 are formed on the barrier layer 105 to complete the high electron mobility transistor structure 100.

Fig. 9 is a schematic cross-sectional view of an intermediate stage of a method of fabricating a high electron mobility transistor structure along the cross-sectional line A-A' of fig. 1 according to another embodiment of the present invention. First, referring to fig. 7, a seed layer 102, a buffer layer 104, a high-resistance layer 106, a channel layer 103, a barrier layer 105 and a compound semiconductor material layer 110 are sequentially stacked on a substrate 101, wherein the compound semiconductor material layer 110 is used to form a cap layer 107 in a subsequent process, and the materials of the layers are compound semiconductors, the composition of which can be described with reference to fig. 2, and the layers can be sequentially formed on the substrate 101 from bottom to top by using different epitaxial growth processes, respectively. Next, referring to fig. 7 and 9, a first patterned photoresist 121 is formed on the compound semiconductor material layer 110, and portions of the compound semiconductor material layer 110 not covered by the first patterned photoresist 121 are removed using an etching process to form patterned compound semiconductor material blocks 112 having a pattern corresponding to a profile formed by connecting blocks of the cap layer 107 shown in fig. 1 to each other by means of connection portions.

Referring still to fig. 9, in step S201, the first patterned photoresist 121 is removed, and then a second patterned photoresist 130 is formed on the patterned block 112 of compound semiconductor material, where the second patterned photoresist 130 has an opening 130-1 corresponding to a predetermined area of the cap layer 107, such as the first gap 108-1. Then, an etching process is used to remove the upper portion of the patterned compound semiconductor material block 112 exposed by the opening 130-1 through the opening 130-1 of the second patterned photoresist 130 to form a connection portion of the cap layer 107, such as the first connection portion 107-C1. Thereafter, the second patterned photoresist 130 is removed, and a gate electrode 109 is formed on the cap layer 107 and a source electrode 111 and a drain electrode 113 are formed on the barrier layer 105, to complete the high electron mobility transistor structure 100, as shown in fig. 1 and 8.

The high electron mobility transistor structure of the embodiment of the invention integrates the enhancement type and depletion type high electron mobility transistors, utilizes the layout framework of the compound semiconductor cover layer, can complete the enhancement type and depletion type high electron mobility transistors without extra processing steps, and achieves the effect of transverse depletion, so that the high electron mobility transistor structure of the invention has the starting function provided by the junction field effect transistor or the depletion type field effect transistor. In addition, the structure of the high electron mobility transistor can stably and accurately control the threshold voltage (Vt) of the depletion type high electron mobility transistor by controlling the gap width between the blocks of the compound semiconductor cover layer. Compared with the prior depletion MISFET (D-mode MISFET), the high electron mobility transistor structure of the invention does not need to form a gate recess and a gate dielectric layer, thereby having the advantages of precisely controlling the threshold voltage (Vt) and avoiding the interface defect (INTERFACE TRAP) between the gate dielectric layer and the semiconductor layer, thereby improving the electrical performance and reliability of the semiconductor device. In addition, the process of the present invention can be performed with the existing high electron mobility transistor Cheng Jianrong, so that the cost of manufacturing can be saved and the high electron mobility transistor can be manufactured on the same wafer together with other high electron mobility transistors.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several equivalent substitutions and obvious modifications can be made without departing from the spirit of the invention, and the same should be considered to be within the scope of the invention.

Claims

1. A high electron mobility transistor structure comprising:

a compound semiconductor channel layer disposed on a substrate;

A compound semiconductor barrier layer disposed on the compound semiconductor channel layer;

A compound semiconductor cover layer arranged on the compound semiconductor barrier layer and comprising a first block and a second block which are arranged along a first direction, wherein a first gap is arranged between the first block and the second block;

A gate electrode disposed on the compound semiconductor cap layer; and

And a source electrode and a drain electrode arranged on the compound semiconductor barrier layer and arranged along a second direction and respectively positioned at two sides of the compound semiconductor cover layer.

2. The high electron mobility transistor structure of claim 1, wherein: one region of the compound semiconductor channel layer directly below the first block and the second block constitutes a channel region of an enhancement type high electron mobility transistor, and the other region of the compound semiconductor channel layer directly below the first gap constitutes a channel region of a depletion type high electron mobility transistor or a junction type field effect transistor.

3. The high electron mobility transistor structure of claim 1, wherein: the first gap has a width in the first direction of 0.01 micrometers to 5 micrometers.

4. The high electron mobility transistor structure of claim 1, wherein: in the first direction, the width of the first gap in the first direction is 0.01 to 0.5 micrometers, the ratio of the width of the first block to the width of the first gap is 5 to 200, the width of the second block is less than or equal to the width of the first block, and the ratio of the width of the second block to the width of the first gap is 5 to 200.

5. The high electron mobility transistor structure of claim 1, wherein: the gate electrode includes a first portion and a second portion separated from each other along the first direction, and the first portion and the second portion are each located directly above the first block and the second block of the compound semiconductor cap layer.

6. The high electron mobility transistor structure of claim 1, wherein: a portion of the surface of the compound semiconductor barrier layer is exposed through the first gap, and the gate electrode continuously covers the first region, the portion of the surface, and the second region.

7. The high electron mobility transistor structure of claim 6, wherein: the gate electrode fills the first gap and has a flat top surface.

8. The high electron mobility transistor structure of claim 1, wherein: the compound semiconductor cover layer further comprises a first connecting part arranged between the first block and the second block, and the thickness of the first connecting part is smaller than that of each of the first block and the second block.

9. The high electron mobility transistor structure of claim 8, wherein: the thickness of the first connection part is 5% to 70% of the thickness of the first block or the second block.

10. The high electron mobility transistor structure of claim 8, wherein: the gate electrode continuously covers the first block, the first connection portion and the second block.

11. The high electron mobility transistor structure of claim 1, wherein: the compound semiconductor cover layer further comprises a third block which is arranged on one side of the second block along the first direction, and a second gap is arranged between the third block and the second block; in the first direction, the width of the second gap is 0.01 to 0.5 microns, and the ratio of the width of the third block to the width of the second gap is 5 to 200.

12. The high electron mobility transistor structure of claim 11, wherein: the compound semiconductor cover layer further comprises a second connecting part arranged between the second block and the third block, and the thickness of the second connecting part is smaller than that of each of the second block and the third block.

13. The high electron mobility transistor structure of claim 11, wherein: the gate electrode continuously covers the first block, the first gap, the second block, the second gap, and the third block.

14. The high electron mobility transistor structure of claim 11, wherein: the gate electrode includes a first portion, a second portion, and a third portion separated from each other along the first direction, and the first portion, the second portion, and the third portion are each located directly above the first block, the second block, and the third block, respectively.

15. The high electron mobility transistor structure of claim 1, wherein: the compound semiconductor channel layer and the compound semiconductor barrier layer extend between the source electrode and the drain electrode along the second direction.

16. A method of fabricating a high electron mobility transistor structure, comprising:

Forming a compound semiconductor channel layer on a substrate;

Forming a compound semiconductor barrier layer on the compound semiconductor channel layer;

Forming a compound semiconductor cover layer on the compound semiconductor barrier layer, wherein the compound semiconductor cover layer comprises a first block and a second block which are arranged along a first direction, and a first gap is arranged between the first block and the second block;

forming a gate electrode on the compound semiconductor cap layer; and

Forming a source electrode and a drain electrode on the compound semiconductor barrier layer, wherein the source electrode and the drain electrode are arranged along a second direction and are respectively positioned at two sides of the compound semiconductor cover layer.

17. The method of manufacturing a high electron mobility transistor structure according to claim 16, wherein forming the compound semiconductor cap layer comprises:

epitaxially growing a compound semiconductor material layer on the compound semiconductor barrier layer;

Forming a patterned photoresist on the compound semiconductor material layer, wherein the patterned photoresist has an opening corresponding to a predetermined region of the first gap; and

Etching removes portions of the compound semiconductor material layer not covered by the patterned photoresist to form the first region, the second region, and the first gap.

18. The method of manufacturing a high electron mobility transistor structure according to claim 16, wherein forming the compound semiconductor cap layer further comprises: and forming a first connecting part which is positioned between the first block and the second block, wherein the thickness of the first connecting part is smaller than that of each of the first block and the second block.

19. The method of manufacturing a high electron mobility transistor structure according to claim 18, wherein forming the first connection portion comprises:

Forming a patterned photoresist on the compound semiconductor material layer, wherein the patterned photoresist has an opening corresponding to a predetermined region of the first gap;

Etching to remove the part of the compound semiconductor material layer not covered by the patterned photoresist to form the first block, the second block and the first gap; and

And epitaxially growing a compound semiconductor material in the first gap to form the first connection portion.

20. The method of manufacturing a high electron mobility transistor structure according to claim 18, wherein forming the first connection portion comprises:

Forming a first patterned photoresist on the compound semiconductor material layer;

Etching to remove the part of the compound semiconductor material layer not covered by the first patterned photoresist to form a patterned compound semiconductor material block;

forming a second patterned photoresist on the patterned block of compound semiconductor material, the second patterned photoresist having an opening corresponding to a predetermined region of the first gap; and

An upper portion of the patterned block of compound semiconductor material exposed by the opening is etched away to form the first connection.