CN118053475A - Write circuit of one-time programmable memory and memory device - Google Patents

Abstract

The invention relates to a write circuit of a one-time programmable memory and a memory device. In the write circuit, a selection module is used for selecting a set number of memory cells to program, enabling a second connection end of the selected memory cells to be grounded to form a current path, disconnecting the current path after the selected memory cells are burned, a voltage module is used for applying a set voltage to a control end of the selected memory cells, a current detection module is used for acquiring sampling current from the current path and outputting a burning-through signal when the sampling current exceeds a reference current, and the selection module enables the current path to be disconnected according to the burning-through signal. The large current flowing through the burn-through storage unit is turned off in time, so that current consumption can be reduced, the requirement on the current output capacity of the voltage module is reduced, the occupied area of the voltage module in the device is reduced, and the circuit power consumption is reduced. The memory device includes the write circuit.

Description

Write circuit of one-time programmable memory and memory device

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a write circuit and a memory device of a one-time programmable memory.

Background

One-time programmable memories (eFuses) have been employed in post-silicon verification, memory repair, in-line field testing, and secure information storage, for example, in DRAM (dynamic random Access memory) repair, defective addresses may be recorded in one-time programmable memories, and when the externally provided address is a defective address, the semiconductor circuit may effect repair by accessing redundant memory cells instead of defective cells. For another example, to solve security issues such as information disclosure, illegal access, or malware attacks that may occur in an internet of things device, a one-time programmable memory may be used to store information to prevent reprogramming. A common one-time programmable memory is programmed using an antifuse mechanism, which is not conductive in its unprogrammed state, but becomes conductive after being programmed, and the programming process is irreversible.

Typically, the one-time programmable memory in the chip includes a plurality of memory cells (cells), and the plurality of memory cells may be arranged in at least one memory array. When writing information in the otp memory, the memory array may be selected and a specific memory cell may be selected for programming based on the row address and the column address in the selected memory array. In programming, a high voltage needs to be applied to a selected memory cell, so that the memory cell is burned-in (burn-in means that an antifuse structure in the memory cell is broken down), and a large current path is formed. The high voltages required for programming are typically generated by a charge pump (pump) inside the device that includes the otp memory.

In order to improve the efficiency of writing information in the otp memory, the same writing operation often needs to program a plurality of memory cells, and due to the difference of the programming time of each memory cell, during the writing process, part of the memory cells are programmed to form a large current, and part of the memory cells are maintained at a high voltage, so that in order to ensure the voltage output capability and the current output capability, the voltage module often needs to use a larger number of charge pumps to provide the high voltage required by programming, which results in a larger area occupied by the voltage module in the device and increased circuit power consumption.

Disclosure of Invention

In order to reduce the requirement on the voltage module while programming a set number of memory cells in the same write operation, thereby being beneficial to reducing the occupied area of the voltage module in the device and reducing the circuit power consumption, the invention provides a write circuit of an one-time programmable memory, and a memory device comprising the write circuit.

In one aspect, the present invention provides a write circuit of a one-time programmable memory, the one-time programmable memory including at least one memory cell, the memory cell having a first connection terminal and a second connection terminal, the write circuit comprising:

The selecting module is used for selecting a set number of memory cells to program, enabling the second connection end of the selected memory cells to be grounded, forming a current path between the second connection end and the ground, and disconnecting the current path after the selected memory cells are burned;

the voltage module is used for applying a set voltage to the control end of the selected storage unit;

And the current detection module is used for acquiring the sampling current from the current path, judging whether the sampling current exceeds a reference current, and outputting a burn-through signal if the sampling current exceeds the reference current, wherein the selection module enables the current path to be disconnected according to the burn-through signal.

Optionally, the selection module includes a row selection transistor, a column selection transistor, and a ground transistor connected in series between the second connection terminal of the memory cell, wherein the second connection terminal of the selected memory cell is grounded through the row selection transistor, the column selection transistor, and the ground transistor by turning on the row selection transistor, the column selection transistor, and the ground transistor connected to the selected memory cell.

Optionally, the selecting module further includes a ground signal control unit, and an output end of the ground signal control unit is connected to a control end of the ground transistor, where when the current detecting module outputs the burn-in signal, the ground signal control unit controls the ground transistor to be turned off.

Optionally, the ground signal control unit includes a nor gate, and an output end of the nor gate is connected to a control end of the ground transistor; and one input end of the NOR gate is connected with a state signal, when the output signal of the current detection module is the burn-in signal, the state signal is subjected to level conversion, so that the output end signal of the NOR gate is subjected to level conversion, and the grounding transistor is turned off.

Optionally, the write circuit further includes:

A memory module for storing the programming state of the memory cell, and storing the programming state of the corresponding selected memory cell as a burn-through state unmodified when the current detection module outputs the burn-through signal;

The selection module cuts off the current path by reading the burn-in state stored by the storage module.

Optionally, the current detection module includes a first cascode current mirror and a second cascode current mirror that are sequentially connected between a power supply voltage and ground, a connection node of the first cascode current mirror and the second cascode current mirror is an output end of the current detection module, a current on an input side of the first cascode current mirror is the sampling current, and a current on an input side of the second cascode current mirror is the reference current.

Optionally, the first cascode current mirror includes a first P-channel transistor MP1, a second P-channel transistor MP2, a third P-channel transistor MP3, and a fourth P-channel transistor MP4, gates of the first P-channel transistor MP1 and the second P-channel transistor MP2 are connected with each other and sources thereof are connected with the power supply voltage, gates of the third P-channel transistor MP3 and the fourth P-channel transistor MP4 are connected with each other and sources thereof are connected with a drain of the first P-channel transistor MP1 and a drain of the second P-channel transistor MP2, gates and drains of the first P-channel transistor MP1 are connected with each other, gates and drains of the third P-channel transistor MP3 are connected with each other and with a first end of the ground transistor, and a second end of the ground transistor is grounded.

Optionally, the second cascode current mirror includes a first N-channel transistor MN1, a second N-channel transistor MN2, a third N-channel transistor MN3, and a fourth N-channel transistor MN4, where the gates of the first N-channel transistor MN1 and the second N-channel transistor MN2 are connected, the drain of the first N-channel transistor MN1 is connected to the reference current, the drain of the second N-channel transistor MN2 is connected to the drain of the fourth P-channel transistor MP4, the connection point is the output end of the current detection module, the drains of the third N-channel transistor MN3 and the fourth N-channel transistor MN4 are respectively connected to the sources of the first N-channel transistor MN1 and the second N-channel transistor MN2, the gates of the third N-channel transistor MN3 and the fourth N-channel transistor MN4 are both connected to ground, the gates of the first N-channel transistor MN1 are connected to the drain, and the drains of the third N-channel transistor MN3 and the drain are connected to each other.

Optionally, the voltage module includes at least one charge pump.

Alternatively, in the same write operation, the selection module selects eight of the memory cells to program.

In one aspect, the present invention provides a memory device including the write circuit described above.

The write circuit of the one-time programmable memory comprises a selection module, a voltage module and a current detection module, wherein the selection module is used for selecting a set number of memory units to program, enabling a second connection end of the selected memory units to be connected to the ground, forming a current path between the second connection end and the ground, disconnecting the current path after the selected memory units are burnt, the voltage module is used for applying a set voltage to a control end of the selected memory units, the current detection module is used for acquiring sampling current from the current path and judging whether the sampling current exceeds a reference current, and outputting a burning-on signal if the sampling current exceeds the reference current, wherein the selection module enables the current path to be disconnected according to the burning-on signal. By timely switching off the large current flowing through the burnt-on memory unit, current consumption can be reduced, the requirement on the current output capacity of the voltage module is reduced, and the occupied area of the voltage module in the device is reduced, and the circuit power consumption is reduced.

The memory device provided by the invention comprises the write circuit, wherein the write circuit can select at least one memory cell in the one-time programmable memory to perform write operation, can reduce current consumption, reduce the requirement on the current output capability of the voltage module, and is beneficial to reducing the area of the memory device and reducing the circuit power consumption of the memory device.

Drawings

FIG. 1 is a schematic diagram of a memory cell and a write circuit of an OTP memory according to an embodiment of the invention.

FIG. 2 is an equivalent circuit diagram of a memory cell and a write circuit when a memory cell of the OTP memory is burned-in accordance with an embodiment of the present invention.

Reference numerals illustrate:

10-a memory cell; a 20-selection module; 30-voltage module; 40-a current detection module; 21-row select transistors; 22-column select transistors; 23-a grounded transistor; 24-ground signal control unit.

Detailed Description

The write circuit and the memory device of the otp memory of the present invention will be described in further detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The embodiment of the invention relates to a write circuit of a one-time programmable memory. The one-time programmable memory may include at least one memory cell (cell). A plurality of the memory cells may form one or more memory cell arrays (fuse arrays), and a plurality of memory cell arrays may form one or more segments (segments) in a chip. The write circuit may program a set number (one or more) of the memory cells in the otp memory in the same write operation. During writing operation, the segment of the memory cell to be programmed is selected, and the memory cell to be programmed is selected according to the address of the memory cell array of the memory cell to be programmed, and the row address and the column address of the memory cell to be programmed in the corresponding memory cell array.

In order to reduce the requirement on the voltage module while programming the set number of memory cells in the same write operation, so as to be beneficial to reducing the occupied area of the voltage module in the device and reducing the circuit power consumption of the device. When the write circuit of the embodiment of the invention is used for programming only one memory cell in the same write operation, when the memory cell is burned, the large current path is turned off in time, so that the requirement on the current output capability of the voltage module is reduced, the occupied area of the voltage module in the device is reduced, and the circuit power consumption of the device is reduced. The write circuit of the otp memory according to the embodiment of the invention is specifically described below.

FIG. 1 is a schematic diagram of a memory cell and a write circuit of an OTP memory according to an embodiment of the invention. Referring to fig. 1, in an embodiment of the present invention, the otp memory includes at least one memory cell 10, and the memory cell 10 includes, for example, a MOS transistor, and a source and a drain of the MOS transistor are connected, and when a voltage applied between a gate and a source (or a drain) exceeds a certain value, a dielectric layer under the gate is broken down to form a large current. In other embodiments, the memory cell 10 may take other configurations. In this embodiment, two ends of the memory cell 10 that form a large current after breakdown are respectively referred to as a first connection end Ain and a second connection end Aout, where the first connection end Ain is, for example, a gate end of a MOS transistor, and the second connection end Aout is, for example, a drain end of the MOS transistor.

Referring to fig. 1, in an embodiment of the present invention, the write circuit includes a selection module 20, a voltage module 30, and a current detection module 40, which are described in detail below.

The selecting module 20 is configured to select a memory cell 10 in the otp memory for programming, connect a second connection terminal Aout of the selected memory cell 10 to ground (ground), form a current path between the second connection terminal Aout and ground, and disconnect the current path after the selected memory cell 10 is burned, that is, disconnect the second connection terminal Aout of the selected memory cell 10 from ground, so that a large current generated by the burning is turned off.

To improve the efficiency of writing information in the otp memory, a plurality of memory cells 10 in the otp memory may be programmed by the same write operation, for example, the selection module 20 may select eight of the memory cells 10 at the same time for programming. Specifically, the n memory cells 10 may be selected for programming by using a segment selection signal Vs, which is a selection signal of a segment in which the n memory cells 10 to be selected are located, an array selection signal Vz (Vz 1, vzn as shown in fig. 1), a row address selection signal Vx, and a column address selection signal Vy, which are selection signals of a memory array in which the n memory cells 10 are located, respectively, where n is an integer greater than or equal to 1, for example, n=8.

The selection module 20 may include a row selection transistor 21, a column selection transistor 22, and a ground transistor 23 connected in series between the second connection terminal Aout of each of the memory cells 10, and when selecting a memory cell 10 in the otp memory, the corresponding memory cell 10 may be selected by turning on the row selection transistor 21, the column selection transistor 22, and the ground transistor 23 connected to the memory cell 10 to be selected, and the second connection terminal Aout of the selected memory cell 10 may be grounded through the row selection transistor 21, the column selection transistor 22, and the ground transistor 23. In this embodiment, the row selection transistor 21 is turned on or off by the row address selection signal Vx, the column selection transistor 22 is turned on or off by the column address selection signal Vy, and the ground transistor 23 is turned on or off by the segment selection signal Vs, the array selection signal Vz (Vz 1, fig. 1, vzn) and a state signal Fs (Fs 1, fig. 1, fsn).

The selection module 20 may include a ground signal control unit 24, and an output terminal of the ground signal control unit 24 is connected to a control terminal of the ground transistor 23 to control the connected ground transistor 23 to be turned on or off. As shown in fig. 1, the ground signal control unit 24 includes, for example, a NOR gate NOR1 provided corresponding to the ground transistor 23, and an output terminal signal of the NOR gate NOR1 serves as a control terminal signal of the corresponding ground transistor 23. The three input terminals of the NOR gate NOR1 are respectively connected to a Segment selection signal Vs of the Segment (Segment) where the selected memory cell 10 is located, an array selection signal Vz of the memory array where the selected memory cell 10 is located, and a status signal Fs. As an example, when the memory cell 10 is selected for programming, the corresponding array selection signal Vz and the segment selection signal Vs of the memory cell 10 are both low, the state signal Fs is also low, so that the row selection transistor 21, the column selection transistor 22 and the ground transistor 23 are turned on to form the above-mentioned current path, and when the memory cell 10 is turned on, a large current flows through the current path connected to the memory cell 10, and the output terminal of the NOR gate NOR1 is level-hopped by level-shifting (e.g., hopping from low to high) the state signal Fs, so that the corresponding ground transistor 23 is turned off, the current path between the memory cell 10 and the ground is disconnected, and the large current is turned off.

The voltage module 30 is configured to apply a set voltage V1 to the first connection terminal Ain of the selected memory cell 10. The voltage module 30 may include at least one charge PUMP (PUMP), and when the voltage module 30 includes a plurality of charge PUMPs, the plurality of charge PUMPs cooperate with each other to output a set voltage V1 required for a programming operation, an output terminal of the voltage module 30 may be connected to the first connection terminal Ain of the memory cell 10, and when one or more memory cells 10 are selected to be programmed, the voltage module 30 may simultaneously apply the set voltage V1 to the first connection terminal Ain of the selected one or more memory cells 10. Since the second connection terminal Aout of the selected memory cell 10 is grounded, the voltage difference between the first connection terminal Ain and the second connection terminal Aout is substantially equal to the set voltage V1, and after the voltage difference is sustained for a certain period of time, a large current is formed by burning a portion of the selected memory cell 10 between the first connection terminal Ain and the second connection terminal Aout, and the large current flows through the current path connected to the corresponding memory cell 10. The specific value of the set voltage V1 may be set according to the breakdown voltage of the memory cell 10.

The current detection module 40 is configured to obtain a sampling current Iin from a current path between the second connection terminal Aout of the selected memory cell 10 and ground, and determine whether the sampling current Iin exceeds a reference current Iref, and if the sampling current Iin exceeds the reference current Iref, output a burn-through signal indicating that the selected memory cell 10 is burned through, so as to open the current path in time. The current detection module 40 is provided corresponding to the ground transistor 23, for example, to detect a current through a current path of the corresponding ground transistor 23, and thus detect whether or not the selected memory cell 10 connected to the current path is burned. In the embodiment of the present invention, the selection module 20 breaks the current path connected to the corresponding selected memory cell 10 according to the burn-in signal output by the current detection module 40, so that the large current generated between the selected memory cell 10 and the ground due to the burn-in is turned off.

Illustratively, the current detection module 40 has an output signal Vf (Vf <1>,. Vf < n > as shown in fig. 1), and taking the current detection module 40 with the output signal Vf <1> as an example, when the obtained sampling current Iin does not exceed the reference current Iref, the output signal Vf <1> indicates that the current path connected to the corresponding selected memory cell 10 does not form a large current, and is in an unfired state, and the output signal Vf <1> is, for example, at a low level (Vf <1> =0); when the sampling current Iin exceeds the reference current Iref, the output signal Vf <1> is, for example, high (Vf <1> =1), and the output signal is a burn-in signal, which indicates that the corresponding selected memory cell 10 is burned-in. The reference current Iref may be set according to circumstances.

In some embodiments, the selection module 20 may obtain the burn-in signal by obtaining the output signal Vf of the current detection module 40, and disconnect the current path connected to the corresponding selected memory cell 10. Specifically, the state signal Fs at the input end of the NOR gate NOR1 may be obtained from the output signal Vf of the current detection module 40, for example, when the output signal Vf <1> of the current detection module 40 is at a low level, the state signal Fs1 at the input end of the NOR gate NOR1 at the control end of the corresponding grounding transistor 23 is also at a low level, and the grounding transistor 23 is turned on; when the output signal Vf <1> of the current detection module 40 is at a high level, the state signal Fs1 at the input terminal of the NOR gate NOR1 at the control terminal of the corresponding ground transistor 23 is converted to a high level, so that the ground transistor 23 is turned off, and the detected current path is disconnected. Alternatively, since the selected memory cell 10 connected to the detected current path is already burned to complete programming (writing), after the detected current path is opened, the corresponding memory cell 10 may no longer be selected to be programmed by controlling the array selection signal Vz, and the ground transistor 23 remains in an opened state, thereby ending the programming operation for the memory cell 10.

Optionally, the write circuit may include a sampling module (not shown) for sampling the output signal Vf of the current detection module 40 and outputting a corresponding signal to the ground signal control unit 24 of the selection module 20. Specifically, when the memory cell 10 is selected to be programmed so as to connect the second connection terminal Aout of the memory cell 10 to ground and the first connection terminal Ain applies the set voltage V1, the sampling module starts to detect the output signal Vf of the current detection module 40 and outputs a corresponding signal to the ground signal control unit 24 of the selection module 20, for example, when the output signal Vf <1> of the current detection module 40 is an inactive signal (low level), the output signal of the sampling module makes the state signal Fs1 of the input terminal of the NOR gate 1 be low level and the ground transistor 23 be on, and when the output signal Vf <1> of the current detection module 40 becomes a burn signal (high level), the output signal of the sampling module changes to the ground signal control unit 24 of the selection module 20 so that the state signal Fs1 of the input terminal of the NOR gate 1 is high level and the ground transistor 23 is turned off, and at the same time, the sampling module stops sampling so that the state signal Fs of the input terminal of the NOR gate 1 keeps the state signal Fs of the input terminal of the corresponding NOR gate 1 is low level, and the state signal Fs of the input terminal of the selected cell is still unchanged even if the state signal V <1> is changed to the burn signal V is high level, and the state signal V is changed to the second connection terminal of the memory cell 10 is not changed, and the memory cell is not changed.

Optionally, the write circuit includes a switch tube (not shown) disposed between the selection module 20 and the current detection module 40, wherein a control end of the switch tube is connected to an output end of the current detection module 40, when the sampling current Iin does not exceed the reference current Iref, and thus the output signal of the current detection module 40 is a non-burn-through signal (e.g., vf <1> =0), the switch tube is in an off state, and does not affect the state of the ground signal control unit 24 in the selection module 20, and at this time, the state signal Fs at the input end of the NOR gate NOR1 is, for example, in a low level, the ground transistor 23 is turned on to form the current path, and when the sampling current Iin exceeds the reference current Iref so that the output signal of the current detection module 40 is a burn-through signal (e.g., vf <1> =1), the switch tube is turned on, so that the state signal Fs at the input end of the NOR gate NOR1 is in a high level, and the ground transistor 23 is turned off. When the grounding transistor 23 is turned off, the large current generated by the selected memory cell 10 being turned on is turned off, the sampling current Iin drops to a level not exceeding the reference current Iref, the output signal of the current detection module 40 is at a low level (e.g., vf <1> =0), the switching tube is turned off, the state of the grounding signal control unit 24 in the selection module 20 is not affected, the state signal Fs at the input terminal of the NOR gate NOR1 remains at a high level, and then the second connection terminal Aout of the memory cell 10 is still disconnected from the ground even if the selected state of the corresponding memory cell 10 is unchanged.

The write circuit may further include a memory module (not shown) for storing a programmed state of at least one memory cell 10 in the otp memory, the memory module being capable of acquiring the output signal Vf of the current detection module 40, and the memory module being capable of non-modifiable storing the programmed state of the corresponding selected memory cell 10 as a burn-through state when the current detection module 40 outputs the burn-through signal. The memory module may include registers or memory areas corresponding to each memory cell 10. By storing the programmed state of at least one memory cell 10 in the otp memory, the memory module can provide a state table that can be read by other modules as needed, for example, when reading the data written in the memory cell 10, the state table can be obtained directly from the programmed state stored in the memory module, without detecting whether the first connection Ain and the second connection Aout of the memory cell 10 are turned on.

In some embodiments, the selection module 20 may cause the current path to be disconnected by reading the burn-in state stored by the storage module. For example, when the on state of a selected memory cell 10 stored in the memory module is not on (or not programmed), the state signal Fs at the input end of the NOR gate NOR1 in the selection module 20 is at a low level, and the ground transistor 23 is turned on, and when the current detection module 40 outputs the on state, the programmed state of the memory cell 10 in the memory module is stored as the on state, the state signal Fs at the input end of the NOR gate NOR1 in the selection module 20 jumps to a high level, so that the ground transistor 23 is turned off. Since the on state of the memory cell 10 is one-time, the on state stored by the memory module is not modifiable, and the state signal Fs at the input terminal of the NOR gate NOR1 is always at a high level after level transition according to the on state stored by the memory module, and then the second connection terminal Aout of the memory cell 10 is disconnected from the ground even if the selected state of the corresponding memory cell 10 is unchanged.

FIG. 2 is an equivalent circuit diagram of a memory cell and a write circuit when a memory cell of the OTP memory is burned-in accordance with an embodiment of the present invention. Referring to fig. 2, there is shown a selected one of the memory cells 10 and the write circuit of fig. 1, and a current path (dc) is formed between the second connection terminal Aout of the memory cell 10 and ground. The memory cell 10, the row selection transistor 21, the column selection transistor 22, and the ground transistor 23 are equivalent to resistors R10, R21, R22, and R23, respectively.

The current detection module 40 samples the current path by connecting the node between the column select transistor 22 and the ground transistor 23, and when the current of the current path increases, the sampling current Iin increases.

Referring to fig. 2, in particular, the current detection module 40 may include a first cascode current mirror and a second cascode current mirror sequentially connected between a power supply voltage VDD and ground, and a connection node of the first cascode current mirror and the second cascode current mirror is an output terminal of the current detection module 40. The current at the input side of the first cascode current mirror is the sampling current Iin derived from the detected current path, and the current at the input side of the second cascode current mirror is the reference current Ivef.

Specifically, when the set voltage V1 is applied to the first connection terminal Ain of the selected memory cell 10 but not yet burned, the resistance R10 has a large resistance (e.g., up to the mΩ level), the current path from the second connection terminal Aout of the memory cell 10 to ground corresponds to an open circuit, the current flowing through the ground transistor 23 is close to 0, the sampling current Iin is smaller than the reference current Iref, the voltage signal at the connection point of the first cascode current mirror and the second cascode current mirror is pulled to a low level after the sampling current Iin is mirrored by the first cascode current mirror and the second cascode current mirror, the output signal Vf <1> of the current detection module 40 is at a low level, and the output of the ground signal control unit 24 (here, for example, the NOR gate 1) is not changed, so as to keep the state of turning on the ground transistor 23.

When the selected memory cell 10 is burned, the resistance R10 becomes smaller (for example, k Ω level), the current path from the second connection terminal Aout of the memory cell 10 to ground is no longer in the off state, the voltage VD at the sampling point for obtaining the sampling current Iin is equal to (r23/(r10+r21+r22+r23)) ×v1, where the grounding transistor 23 is, for example, an NMOS transistor, the voltage VD is equal to the drain voltage of the grounding transistor 23, and R10, R21, R22, R23 respectively represent the resistances of the memory cell 10, the row selection transistor 21, the column selection transistor 22, and the grounding transistor 23. It can be seen that when the selected memory cell 10 is turned on, the current flowing through the ground transistor 23 increases, the sampling current Iin also increases, and when the sampling current Iin increases to be greater than the reference current Iref, after mirroring the first cascode current mirror and the second cascode current mirror, the voltage signal at the junction of the first cascode current mirror and the second cascode current mirror is pulled to a high level, at this time, the output signal Vf <1> of the current detection module 40 is 1, and accordingly, the output of the NOR gate NOR1 is level-shifted, the ground transistor 23 is turned off, so that the corresponding current path is turned off, the large current from the first junction Ain of the selected memory cell 10 connected to the current path is turned off, and the voltage difference is not required to be maintained across the memory cell 10 after being turned on due to the irreversibility of the turning on, and the current consumption can be reduced by turning off the large current after the turning off.

Referring to fig. 2, the first cascode current mirror includes, for example, a first P-channel transistor MP1, a second P-channel transistor MP2, a third P-channel transistor MP3, and a fourth P-channel transistor MP4, wherein gates of the first P-channel transistor MP1 and the second P-channel transistor MP2 are connected to each other and sources thereof are connected to a power supply voltage VDD, gates of the third P-channel transistor MP3 and the fourth P-channel transistor MP4 are connected to gates thereof and sources thereof are connected to a drain of the first P-channel transistor MP1 and a drain of the second P-channel transistor MP2, respectively, gates and drains of the first P-channel transistor MP1 are connected to each other, gates and drains of the third P-channel transistor MP3 are connected to each other and are connected to a first end (for example, a drain of the ground transistor 23) of the ground transistor 23, and a second end (for example, a source of the ground transistor 23) of the ground transistor 23 is grounded.

The second cascode current mirror includes, for example, a first N-channel transistor MN1, a second N-channel transistor MN2, a third N-channel transistor MN3, and a fourth N-channel transistor MN4, where gates of the first N-channel transistor MN1 and the second N-channel transistor MN2 are connected, a drain of the first N-channel transistor MN1 is connected to the reference current Iref, a drain of the second N-channel transistor MN2 is connected to a drain of a fourth P-channel transistor MP4 in the first cascode current mirror, a connection point is an output end of the current detection module 40, drains of the third N-channel transistor MN3 and the fourth N-channel transistor MN4 are respectively connected to sources of the first N-channel transistor MN1 and the second N-channel transistor MN2, gates of the third N-channel transistor MN3 and the fourth N-channel transistor MN4 are connected to each other, and sources of the first N-channel transistor MN1 and the drain are connected to the drain of the third N-channel transistor MN 3.

In the write circuit of the embodiment of the present invention, the current detection module 40 obtains the sampling current Iin from the current path connected to the selected memory cell 10, and determines whether the sampling current Iin exceeds the reference current Iref, so as to detect whether the selected memory cell 10 is burned through, and the selection module 20 breaks the current path according to the burn-through signal, so that the large current generated by the burn-through is turned off, current consumption can be reduced, the requirement on the current output capability of the voltage module 40 can be reduced, for example, the write operation can be performed through a small number of charge pumps, which is helpful for reducing the area occupied by the voltage module 30 in the device and reducing the circuit power consumption.

The embodiment of the invention also relates to a memory device, which comprises the write circuit described in the embodiment. By way of example, the Memory device may include at least one of Static Random-Access Memory (SRAM), dynamic Random-Access Memory (DRAM), resistive Random-Access Memory (RRAM), phase-Change Random-Access Memory (PCRAM), and magnetoresistive Random-Access Memory (Magnetoresistive Random-Access Memory, MRAM), and the like, and may further include a one-time programmable Memory, which may include the Memory cell 10 described in at least one of the above embodiments. According to the description of the above embodiment, the write circuit can select at least one memory cell 10 in the otp memory for writing operation, and can reduce current consumption, reduce the requirement for the current output capability of the voltage module 30, for example, program a set number of memory cells 10 by a smaller number of charge pumps, which helps to reduce the area of the memory device and reduce the circuit power consumption of the memory device.

The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims (11)

1. A write circuit for a one-time programmable memory, the one-time programmable memory comprising at least one memory cell, the memory cell having a first connection and a second connection, the write circuit comprising:

The selecting module is used for selecting a set number of memory cells to program, enabling the second connection end of the selected memory cells to be grounded, forming a current path between the second connection end and the ground, and disconnecting the current path after the selected memory cells are burned;

the voltage module is used for applying a set voltage to the control end of the selected storage unit; and

And the current detection module is used for acquiring the sampling current from the current path, judging whether the sampling current exceeds a reference current, and outputting a burn-through signal if the sampling current exceeds the reference current, wherein the selection module enables the current path to be disconnected according to the burn-through signal.

2. The write circuit of claim 1, wherein the selection module includes a row selection transistor, a column selection transistor, and a ground transistor connected in series between a second connection terminal of the memory cell, wherein the second connection terminal of the selected memory cell is grounded through the row selection transistor, the column selection transistor, and the ground transistor by turning on the row selection transistor, the column selection transistor, and the ground transistor connected to the selected memory cell.

3. The write circuit of claim 2, wherein the selection module further comprises a ground signal control unit having an output terminal connected to a control terminal of the ground transistor, wherein the ground signal control unit controls the ground transistor to turn off when the current detection module outputs the burn-in signal.

4. The write circuit of claim 3 wherein the ground signal control unit comprises a nor gate, an output of the nor gate being connected to a control terminal of the ground transistor; and one input end of the NOR gate is connected with a state signal, when the output signal of the current detection module is the burn-in signal, the state signal is subjected to level conversion, so that the output end signal of the NOR gate is subjected to level conversion, and the grounding transistor is turned off.

5. The write circuit of claim 1, further comprising:

A memory module for storing the programming state of the memory cell, and storing the programming state of the corresponding selected memory cell as a burn-through state unmodified when the current detection module outputs the burn-through signal;

The selection module cuts off the current path by reading the burn-in state stored by the storage module.

6. The write circuit of claim 2, wherein the current detection module includes a first cascode current mirror and a second cascode current mirror connected in sequence between a supply voltage and ground, a connection node of the first cascode current mirror and the second cascode current mirror being an output of the current detection module, a current on an input side of the first cascode current mirror being the sampling current, a current on an input side of the second cascode current mirror being the reference current.

7. The write circuit of claim 6 wherein the first cascode current mirror comprises a first P-channel transistor MP1, a second P-channel transistor MP2, a third P-channel transistor MP3, and a fourth P-channel transistor MP4, the gates of the first P-channel transistor MP1 and the second P-channel transistor MP2 are both connected to the supply voltage, the gates of the third P-channel transistor MP3 and the fourth P-channel transistor MP4 are both connected to the supply voltage, the sources are respectively connected to the drain of the first P-channel transistor MP1 and the drain of the second P-channel transistor MP2, the gate and the drain of the first P-channel transistor MP1 are connected, the gate and the drain of the third P-channel transistor MP3 are both connected to the first end of the ground transistor, and the second end of the ground transistor is grounded.

8. The write circuit of claim 7 wherein the second cascode current mirror comprises a first N-channel transistor MN1, a second N-channel transistor MN2, a third N-channel transistor MN3, and a fourth N-channel transistor MN4, the first N-channel transistor MN1 and the second N-channel transistor MN2 have their gates connected, the first N-channel transistor MN1 has its drain connected to the reference current, the second N-channel transistor MN2 has its drain connected to the fourth P-channel transistor MP4 and its connection point is the output of the current detection module, the third N-channel transistor MN3 and the fourth N-channel transistor MN4 have their drains connected to the sources of the first N-channel transistor MN1 and the second N-channel transistor MN2, the third N-channel transistor MN3 and the fourth N-channel transistor MN4 have their gates connected and their sources connected to ground, the first N-channel transistor MN1 and the drain connected to the drain of the third N-channel transistor MN 3.

9. The write circuit of any one of claims 1 to 8, wherein the voltage module comprises at least one charge pump.

10. The write circuit of any one of claims 1 to 8, wherein the selection module selects eight of the memory cells to program in a same write operation.

11. A memory device comprising a write circuit as claimed in any one of claims 1 to 10.