CN118050613A - DIMM slot test system without JTAG serial test circuit board and method thereof - Google Patents

Abstract

A DIMM slot test system without JTAG serial test circuit board and its method, the DIMM plug interface of the test circuit board is plugged in the DIMM slot of the test circuit board, the CPU generates test data or test signal according to the test signal of JTAG signal format, the CPU transmits test data to appointed CPLD chip through differential pin or input/output pin, the appointed CPLD chip records the received data as test result, the CPU transmits test signal to appointed CPLD chip through control pin, appointed CPLD chip tests power pin or ground pin takes the value of reading and recording power pin or ground pin as test result, the CPU generates test result reading signal, transmits test result reading signal to appointed CPLD chip through control pin to obtain test result by data transmission pin and feeds back to the detecting device.

Description

DIMM slot test system without JTAG serial test circuit board and method thereof

Technical Field

The present invention relates to a socket test system and a method thereof, and more particularly, to a socket test system and a method thereof capable of independently testing a DIMM socket without using JTAG (joint test action group) to connect in series a test circuit board inserted in the DIMM socket.

Background

IN the prior art, a DIMM test circuit board needs to be inserted into the DIMM slot IN the boundary scan test of the DIMM slot, and two JTAG connection interfaces (namely a JTAG IN connection interface and a JTAG OUT connection interface) need to be arranged on the DIMM test circuit board according to the specification of the boundary scan test technology, so that JTAG signals can be transmitted into and OUT of the DIMM test circuit board to realize the boundary scan test of the DIMM slot.

When actually performing the boundary scan test of the DIMM socket, since each DIMM test circuit board needs to be connected IN series with each other through the JTAG IN connection interface and the JTAG OUT connection interface, the stability of the line connection is affected due to the overlong line of the series connection, and the driving capability and stability of the JTAG signal must meet certain requirements, the insufficient stability of the line connection will cause the boundary scan test of the DIMM socket to fail.

IN summary, it can be seen that there is a long-felt need IN the art for an improved technique for solving the problem of failure of the boundary scan test caused by insufficient stability of the line connection generated by the connection of the boundary scan test of the existing DIMM slot through the JTAG IN connection interface and the JTAG OUT connection interface.

Disclosure of Invention

IN view of the problem that the boundary scan test fails due to insufficient line connection stability caused by the fact that the existing DIMM slot boundary scan test is connected IN series through a JTAG IN connection interface and a JTAG OUT connection interface IN the prior art, the invention further discloses a DIMM slot test system and a method thereof without a JTAG serial test circuit board, wherein:

The invention discloses a DIMM slot test system of a JTAG-free serial test circuit board, which comprises: the test system comprises a circuit board to be tested, at least one test circuit board, a test access Port (TEST ACCESS Port, TAP) controller and a detection device.

The circuit board to be tested is provided with a joint test working group (Joint Test Action Group, JTAG) connection interface, a central processing unit (Central Processing Unit, CPU) and at least one Dual In-line Memory Module, DIMM (Dual In-DIMM) slot, each DIMM slot comprises a plurality of power pins, a plurality of grounding pins, a plurality of differential pins and a plurality of input/output pins, wherein a selected part of the input/output pins is used as a control pin, a selected part of the input/output pins is used as a data transmission pin, and the differential pins and the input/output pins are electrically connected with the CPU.

Each test circuit board has a DIMM socket interface plugged into one of the at least one DIMM socket and at least one complex programmable logic device (Complex Programmable Logic Device, CPLD) chip in electrical connection with the DIMM socket interface.

The TAP controller is electrically connected with the circuit board to be tested through the JTAG connection interface; and the detection device is electrically connected with the TAP controller.

The test device generates a test signal and provides the test signal to the TAP controller, the TAP controller converts the test signal into a test signal in a JTAG signal format and provides the test signal to the CPU, the CPU transmits the test data to a designated CPLD chip through a differential pin or an input/output pin according to the generated test data or the test signal, the designated CPLD chip records the received data as a test result, the CPU transmits the test signal to the designated CPLD chip through a control pin, the designated CPLD chip tests a power pin or a grounding pin to read and record the numerical value of the power pin or the grounding pin as the test result, and the CPU generates a test result reading signal and transmits the test result reading signal to the designated CPLD chip through the control pin to acquire the test result through the data transmission pin and feeds back the test result to the test device.

The invention discloses a DIMM slot test method of a JTAG-free serial test circuit board, which comprises the following steps:

Firstly, a circuit board to be tested is provided with a joint test working group connection interface, a CPU and at least one DIMM slot, wherein the JTAG connection interface is electrically connected with the CPU, each DIMM slot comprises a plurality of power supply pins, a plurality of grounding pins, a plurality of differential pins and a plurality of input/output pins, a part of pins selected from the input/output pins are used as control pins, a part of pins selected from the input/output pins are used as data transmission pins, and the differential pins and a part of input/output pins are electrically connected with the CPU; next, at least one test circuit board is respectively provided with a DIMM plug interface and at least one CPLD chip which is electrically connected with the DIMM plug interface, and the DIMM plug interface is plugged into one of at least one DIMM slot; then, the TAP controller is electrically connected with the circuit board to be tested through a JTAG connection interface; then, the detecting device is electrically connected with the TAP controller; next, the detection device generates a test signal and provides the test signal to the TAP controller; then, the TAP controller converts the test signal into a test signal in JTAG signal format and provides the test signal to the CPU; then, the CPU generates test data or test signals according to the test signals in the JTAG signal format; then, the CPU transmits test data to a designated CPLD chip through a differential pin or an input/output pin, and the designated CPLD chip records the received data as a test result; then, the CPU transmits a test signal to a designated CPLD chip through a control pin, and the designated CPLD chip tests a power pin or a grounding pin to read and record the numerical value of the power pin or the grounding pin as a test result; finally, the CPU generates a test result reading signal, and transmits the test result reading signal to the appointed CPLD chip through the control pin so as to obtain a test result through the data transmission pin and feed back the test result to the detection device.

The system and the method disclosed by the invention are different from the prior art in that the DIMM plug-in interface of the test circuit board is plugged in the DIMM slot of the circuit board to be tested, the CPU generates test data or test signals according to the test signals in JTAG signal format, the CPU transmits the test data to the appointed CPLD chip through differential pins or input/output pins, the appointed CPLD chip records the received data as test results, the CPU transmits the test signals to the appointed CPLD chip through control pins, the appointed CPLD chip tests the power pins or grounding pins to read and record the values of the power pins or grounding pins as test results, the CPU generates test result reading signals, and the control pins transmit the test result reading signals to the appointed CPLD chip to obtain the test results through the data transmission pins and feed back the test results to the detection device.

By the technical means, the invention can achieve the technical effect that the test circuit boards can independently test pins of the DIMM slot of the circuit board to be tested.

Drawings

FIG. 1 shows a system block diagram of a DIMM socket test system without a JTAG serial test circuit board of the present invention.

FIG. 2A is a block diagram illustrating a test circuit board and DIMM socket according to a first embodiment of the present invention.

FIG. 2B is a block diagram illustrating a test circuit board and DIMM socket according to a second embodiment of the present invention.

Fig. 3A shows a schematic block diagram of a test circuit board according to an embodiment variant of the embodiment of fig. 2A.

Fig. 3B shows a schematic block diagram of a test circuit board according to an embodiment variant of the embodiment of fig. 2B.

Fig. 4A and 4B are flow charts illustrating a method of testing a DIMM socket of a JTAG-free serial test circuit board according to the present invention.

Reference numerals illustrate:

10-to-be-tested circuit board

11JTAG connection interface

12CPU

13DIMM slot

131. Power supply pin

132. Grounding pin

133. Differential pin

134. Input/output pin

145. Control pin

146. Data transmission pin

20 Test circuit board

21DIMM plug-in interface

23A/D converter

22CPLD chip

30TAP controller

40 Detection device

Detailed Description

The embodiments of the present invention will be described in detail below with reference to the drawings and the embodiments, so that the implementation process of how the technical means are applied to solve the technical problems and achieve the technical effects of the present invention can be fully understood and implemented.

The present invention discloses a DIMM socket test system without a JTAG serial test circuit board, and please refer to fig. 1, fig. 1 shows a system block diagram of the DIMM socket test system without a JTAG serial test circuit board.

The invention discloses a DIMM slot test system of a JTAG-free serial test circuit board, which comprises: the test circuit board 10, at least one test circuit board 20, the TAP controller 30 and the detecting device 40.

The circuit board 10 to be tested has a JTAG connection interface 11, a CPU12 and at least one DIMM slot 13, wherein the JTAG connection interface 11 is electrically connected with the CPU12, each DIMM slot 13 (please refer to FIG. 2A) includes a plurality of power pins 131, a plurality of ground pins 132, a plurality of differential pins 133 and a plurality of input/output pins 134, a selected portion of the input/output pins 134 is used as a control pin 135, a selected portion of the input/output pins 134 is used as a data transmission pin 136, and the differential pins 133 and the input/output pins 134 are electrically connected with the CPU 12.

Each test circuit board 20 has a DIMM socket interface 21 and a CPLD chip 22, the number of test circuit boards 20 is the same as the number of DIMM sockets 13 of the circuit board 10 to be tested, and the DIMM socket interface 21 is plugged into one of the at least one DIMM socket 13.

Referring to fig. 2A, fig. 2A is a block schematic diagram illustrating a test circuit board and a DIMM socket according to a first embodiment of the present invention, in fig. 2A, only a single CPLD chip 22 is provided, so that the CPLD chip 22 is electrically connected to the DIMM socket 21, and the power pin 131, the ground pin 132, the differential pin 133, the input/output pin 134, the control pin 135 and the data transmission pin 136 of the DIMM socket 13 are electrically connected to the single CPLD chip 22, which is only illustrative and not intended to limit the application scope of the present invention.

Referring to fig. 2B, fig. 2B is a block schematic diagram illustrating a test circuit board and a DIMM socket according to a second embodiment of the present invention, in fig. 2B, two CPLD chips 22 are provided, each CPLD chip 22 is electrically connected to the DIMM socket 21, and it should be noted that the power pin 131, the ground pin 132, the control pin 135 and the data transmission pin 136 of the DIMM socket 13 are electrically connected to one CPLD chip 22, and the differential pin 133, the input/output pin 134, the control pin 135 and the data transmission pin 136 of the DIMM socket 13 are electrically connected to another CPLD chip 22, which is only illustrative herein and not limiting the application scope of the present invention.

The TAP controller 30 is electrically connected with the circuit board 10 to be tested through the JTAG connection interface 11, and the detecting device 40 is electrically connected with the TAP controller 30, so as to construct the overall test architecture of the DIMM socket test of the JTAG-free serial test circuit board.

The foregoing mentions that a pin of the selected portion of the input-output pins is used as a data transmission pin, which is used for data transmission between the CPU12 and the CPLD chip 22, and the input-output pins may be selected so that the data transmission pin needs to satisfy the following conditions: the input/output pins have not been selected as control pins, the input/output pins are electrically connected to the CPU12, and the input/output pins and the CPU12 perform functions of reading and writing to each other.

Specifically, up to 104 input/output pins in the DIMM slot 13 defined by the DDR5 DIMM specification may be selected as data transmission pins, i.e., up to 104 input/output pins in the DIMM slot 13 defined by the DDR5 DIMM specification are electrically connected to the CPU12, and the input/output pins are not yet selected as control pins, and the input/output pins and the CPU12 may have functions of reading and writing.

The input/output pins in the DIMM slot 13 defined by the DDR5 DIMM specification are not electrically connected to the CPU12, or the input/output pins in the DIMM slot 13 defined by the DDR5 DIMM specification are electrically connected to the CPU12, but the data transmission direction of the input/output pins is unidirectional (i.e., the input/output pins can only perform data reading or data writing), so that the input/output pins cannot be selected as data transmission pins, and the power pins and the ground pins in the DIMM slot 13 defined by the DDR5 DIMM specification are not electrically connected to the CPU12, so that the input/output pins cannot be selected as data transmission pins.

Although the differential pins in the DIMM socket 13 defined by the DDR5 DIMM specification are electrically connected to the CPU12, since the boundary scan cell (BoundaryScan Cell, BSC) in the CPU12 is in a fixed direction, it cannot have the functions of reading and writing, and thus cannot be selected as data transfer pins.

The foregoing references to a selected portion of the input/output pins as control pins and the following description will describe embodiments of control pin selection in the specification definition of DDR5 DIMM.

The fourth pin (i.e., pin 4 defined by the DDR5DIMM specification) in the DDR5DIMM slot is the Serial Clock (SCL) pin of the modified internal integrated Circuit (advanced INTER INTEGRATED Circuit, I3C) bus, the fifth pin (i.e., pin 5 defined by the DDR5DIMM specification) in the DDR5DIMM slot is the Serial Clock (SCL) pin serial data (SERIAL DATA, SDA) pin of the I3C bus, since the fourth pin and the fifth pin in the DDR5DIMM slot are typically connected together for 8 DIMM slots 13 to be reconnected to the CPU12 in the Circuit design of the Circuit board under test 10, in order to reduce the number of DIMM slots 13 when chip select (CHIP SELECT) control, the fourth pin in the DDR5DIMM slot can be selected as WE_n control pin (i.e., write enable) and the fifth pin in the DDR5DIMM slot can be selected as OE_n control pin (i.e., read enable).

The sixty-fourth pin in the DDR5 DIMM slot in the DDR5 DIMM specification definition (i.e., pin 64 of the DDR5 DIMM specification definition) is one of the chip select pins of DIMM slot 13, thus selecting the sixty-fourth pin in the DDR5 DIMM slot as the CE_n control pin (i.e., chip select enable).

Communication control between the CPU12 of the circuit board 10 to be tested and the CPLD chip 22 of the circuit board 20 to be tested can be accomplished by selecting the fourth pin, the fifth pin and the sixty-fourth pin in the DDR5 DIMM socket, which is only for illustration, and is not meant to limit the scope of application of the present invention.

In addition, in the specification definition of the DDR5 DIMM, the second hundred and nine pins in the DDR5 DIMM slot (i.e., pin 209 defined by the DDR5 DIMM specification) is one of the chip select pins of the DIMM slot 13, and the second hundred and nine pins in the DDR5 DIMM slot are further selected as the ptn_idx control pins (i.e., the test mode indication), and the ptn_idx control pins can be used as the indication of the test mode (TEST PATTERN), specifically, assuming that there are two sets of test modes in the test logic, when the ptn_idx control pin is 0, the first set of test modes is currently used for testing; when the ptn_idx control pin is 1, the second set of test modes is used for testing, which is only used for illustration, and the application scope of the present invention is not limited.

The detection device 40 is, for example: for example, the application range of the present invention is not limited, and a test signal is generated by a tester through the detecting device 40 and provided to the TAP controller 30, the TAP controller 30 converts the test signal into a test signal with a JTAG signal format and provides the test signal to the CPU12 through the JTAG connection interface 11, the CPU12 generates test data or the test signal according to the test signal with the JTAG signal format, the CPU12 transmits the test data to the designated CPLD chip 22 through the differential pin 133 or the input/output pin 134, the designated CPLD chip 22 records the received data as a test result, the CPU12 transmits the test signal to the designated CPLD chip 22 through the control pin 135, the designated CPLD chip 22 tests the power pin 131 or the ground pin 132 to read and record the numerical value of the power pin 131 or the ground pin 132 as a test result, and the CPU12 generates a test result reading signal, and transmits the test result reading signal to the designated CPLD chip 22 through the control pin 135 to obtain the test result through the data transmission pin 136 and feeds back to the detecting device 40.

It should be noted that, the CPU12 sends test data or test signals to all the DIMM slots 13 at the same time, so that all the test circuit boards 20 simultaneously test and record test results to the DIMM slots 13, in a general design, two DIMM slots 13 are in the same Channel (Channel), so when the CPU12 generates a test result reading signal, it is necessary to select one DIMM slot 13 in each Channel to obtain the test result of the first selected DIMM slot 13 in each Channel, and then select another DIMM slot 13 in each Channel to obtain the test result of the second selected DIMM slot 13 in each Channel, thereby obtaining the test result of all the DIMM slots 13.

It should be noted that, the CPU12 transmits the power test signal to the designated CPLD chip 22 through the control pin 135 according to the power test signal or the ground test signal generated by the test signal in the JTAG signal format, the designated CPLD chip 22 tests the power pin 131 to read and record the value of the power pin 131 as the power test result, or the CPU12 transmits the ground test signal to the designated CPLD chip 22 through the control pin 135, and the designated CPLD chip 22 tests the ground pin 132 to read and record the value of the ground pin 132 as the ground test result.

The CPLD chip 22 is electrically connected to the power pin through an Analog-to-digital converter (ADC) 23 or a single chip, the CPU12 generates a test signal according to the test signal in the JTAG signal format as a power test signal, the CPU12 transmits the power test signal to the designated CPLD chip 22 through the control pin 135, the designated CPLD chip 22 tests the power pin 131 of the DIMM slot 13 through the ADC23 or the single chip, so that the value of the power pin 131 of the DIMM slot 13 is read by the ADC23 or the single chip, the test circuit board 20 is shown with reference to fig. 3A and 3B, fig. 3A shows a schematic block diagram of the test circuit board according to the embodiment variant of the embodiment of fig. 2A, fig. 3B shows a schematic block diagram of the test circuit board according to the embodiment variant of the embodiment of fig. 2B, and fig. 3A and 3B only take the ADC23 as illustrations, which is not limiting the application scope of the invention.

The CPU12 generates test data as differential test data according to the test signal in the JTAG signal format, and the CPU12 transmits the differential test data to the designated CPLD chip 22 through the differential pin 133, and the designated CPLD chip 22 records the received data as a differential test result.

The CPU12 generates test data as input/output test data according to the test signal in the JTAG signal format, and the CPU12 transmits the input/output test data to the specified CPLD chip 22 through the input/output pin 134, and the specified CPLD chip 22 records the received data as an input/output test result.

Next, the operation system and method of the first embodiment of the present invention will be described with reference to fig. 4A and 4B, and fig. 4A and 4B show a method flowchart of the DIMM socket testing method of the JTAG tandem test circuit board of the present invention.

The invention discloses a DIMM slot test method of a JTAG-free serial test circuit board, which comprises the following steps:

Firstly, a circuit board to be tested is provided with a joint test working group connection interface, a CPU and at least one DIMM slot, wherein the JTAG connection interface is electrically connected with the CPU, each DIMM slot comprises a plurality of power supply pins, a plurality of grounding pins, a plurality of differential pins and a plurality of input/output pins, a part of pins selected from the input/output pins are used as data transmission pins, a part of pins selected from the input/output pins are used as control pins, and the differential pins and the input/output pins are electrically connected with the CPU (step 501); next, at least one test circuit board is provided with a DIMM socket interface and at least one CPLD chip electrically connected with the DIMM socket interface, wherein the DIMM socket interface is plugged into one of the at least one DIMM slot (step 502); next, the TAP controller forms an electrical connection with the circuit board to be tested through the JTAG connection interface (step 503); next, the detection device is electrically connected to the TAP controller (step 504); next, the detection device generates a test signal and provides the test signal to the TAP controller (step 505); next, the TAP controller converts the test signal into a test signal in JTAG signal format and provides it to the CPU (step 506); next, the CPU generates test data or test signals according to the test signals in the JTAG signal format (step 507); next, the CPU transmits the test data to the designated CPLD chip through the differential pin or the input/output pin, and the designated CPLD chip records the received data as a test result (step 508); next, the CPU transmits a test signal to the designated CPLD chip through the control pin, and the designated CPLD chip tests the power pin or the ground pin to read and record the numerical value of the power pin or the ground pin as a test result (step 509); finally, the CPU generates a test result reading signal, transmits the test result reading signal to the designated CPLD chip through the control pin to obtain the test result from the data transmission pin and feeds back the test result to the detection device (step 510).

In summary, the difference between the present invention and the prior art is that the DIMM socket of the test circuit board is plugged into the DIMM slot of the test circuit board, the CPU generates test data or test signals according to the test signals in the JTAG signal format, the CPU transmits the test data to the designated CPLD chip through the differential pins or the input/output pins, the designated CPLD chip records the received data as test results, the CPU transmits the test signals to the designated CPLD chip through the control pins, the designated CPLD chip tests the power pins or the ground pins to read and record the values of the power pins or the ground pins as test results, the CPU generates test result reading signals, and the control pins transmit the test result reading signals to the designated CPLD chip to obtain test results from the data transmission pins and feed back to the detection device.

The technical means can solve the problem that the boundary scan test fails due to insufficient line connection stability caused by the fact that the existing DIMM slot boundary scan test IN the prior art is formed by connecting a JTAG IN connection interface and a JTAG OUT connection interface IN series, and further achieves the technical effect that the test circuit boards independently test pins of the DIMM slot of the circuit board to be tested.

Although the invention is described above, the disclosure is not intended to limit the scope of the invention. Workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the disclosure. The scope of the invention is to be defined only by the appended claims.

Claims (10)

1. A DIMM socket test system for a JTAG-free serial test circuit board, comprising:

The circuit board to be tested is provided with a joint test working group (JTAG) connection interface, a Central Processing Unit (CPU) and at least one dual in-line memory module (DIMM) slot, wherein each DIMM slot comprises a plurality of power supply pins, a plurality of grounding pins, a plurality of differential pins and a plurality of input/output pins, wherein a part of pins selected from the input/output pins are used as data transmission pins, a part of pins selected from the input/output pins are used as control pins, and the differential pins and a part of the input/output pins are electrically connected with the CPU;

at least one test circuit board, the test circuit board further comprising:

the DIMM plug-in interface is plugged in one of the at least one DIMM slot; and

At least one Complex Programmable Logic Device (CPLD) chip electrically connected with the DIMM plug interface;

a Test Access Port (TAP) controller electrically connected to the circuit board to be tested through the JTAG connection interface; and

The detection device is electrically connected with the TAP controller;

the test device generates a test signal and provides the test signal to the TAP controller, the TAP controller converts the test signal into a test signal in a JTAG signal format and provides the test signal to the CPU, the CPU generates test data or the test signal according to the test signal in the JTAG signal format, the CPU transmits the test data to the appointed CPLD chip through the differential pin or the input/output pin, the appointed CPLD chip records the received data as a test result, the CPU transmits the test signal to the appointed CPLD chip through the control pin, the appointed CPLD chip tests the power pin or the grounding pin to read and record the numerical value of the power pin or the grounding pin as the test result, and the CPU generates a test result reading signal and transmits the test result reading signal to the appointed CPLD chip through the control pin to obtain the test result through the data transmission pin and feed back the test result to the test device.

2. The DIMM socket test system of the JTAG-free serial test circuit board of claim 1, wherein the test signal generated by the CPU according to the test signal in the JTAG signal format is a power test signal or a ground test signal, the CPU transmits the power test signal to the specified CPLD chip through the control pin, the specified CPLD chip tests the power pin to read and record the value of the power pin as a power test result, or the CPU transmits the ground test signal to the specified CPLD chip through the control pin, and the specified CPLD chip tests the ground pin to read and record the value of the ground pin as a ground test result.

3. The DIMM socket test system of JTAG-free serial test circuit board of claim 1, wherein said test circuit board further comprises an analog-to-digital converter (ADC), said ADC is electrically connected to said CPLD chip and said DIMM socket respectively, said CPU is configured to generate a test signal according to a test signal in a JTAG signal format as a power test signal, said CPU is configured to transmit said power test signal to said CPLD chip through said control pin, said CPLD chip is configured to test said power pin through said ADC, so that the value of said power pin is read by said ADC, and said CPLD chip is configured to read and record the value of said power pin from said ADC as said power test result.

4. The DIMM socket test system of JTAG-free serial test circuit boards of claim 1, wherein the CPU generates test data as differential test data according to test signals in JTAG signal format, and the CPU transmits the differential test data to the designated CPLD chip via the differential pins, and the designated CPLD chip records the received data as a differential test result.

5. The DIMM socket test system of JTAG-free serial test circuit board of claim 1, wherein the CPU generates test data as input/output test data according to test signals in JTAG signal format, and the CPU transmits the input/output test data to the designated CPLD chip via the input/output pins, and the designated CPLD chip records the received data as input/output test results.

6. A DIMM slot test method of a JTAG-free serial test circuit board comprises the following steps:

The circuit board to be tested is provided with a joint test working group (JTAG) connection interface, a Central Processing Unit (CPU) and at least one dual in-line memory module (DIMM) slot, wherein each DIMM slot comprises a plurality of power supply pins, a plurality of grounding pins, a plurality of differential pins and a plurality of input/output pins, a part of pins selected from the input/output pins are used as data transmission pins, a part of pins selected from the input/output pins are used as control pins, and the differential pins and a part of the input/output pins are electrically connected with the CPU;

the at least one test circuit board is respectively provided with a DIMM plug interface and at least one Complex Programmable Logic Device (CPLD) chip which is electrically connected with the DIMM plug interface, and the DIMM plug interface is plugged in one of the at least one DIMM slot;

a Test Access Port (TAP) controller is electrically connected with the circuit board to be tested through the JTAG connection interface;

The detection device is electrically connected with the TAP controller;

The detection device generates a test signal and provides the test signal to the TAP controller;

the TAP controller converts the test signal into a test signal in a JTAG signal format and provides the test signal to the CPU;

the CPU generates test data or test signals according to the test signals in the JTAG signal format;

the CPU transmits test data to the appointed CPLD chip through the differential pin or the input/output pin, and the appointed CPLD chip records the received data as a test result;

The CPU transmits a test signal to the appointed CPLD chip through the control pin, and the appointed CPLD chip tests the power pin or the grounding pin to read and record the numerical value of the power pin or the grounding pin as a test result; and

And the CPU generates a test result reading signal, transmits the test result reading signal to the appointed CPLD chip through the control pin so as to acquire a test result through the data transmission pin and feeds back the test result to the detection device.

7. The method according to claim 6, wherein the CPU transmits test data to the designated CPLD chip through the differential pin or the input/output pin, the step of the designated CPLD chip recording the received data as a test result is that the CPU transmits the power test signal to the designated CPLD chip through the control pin as a power test signal or a ground test signal according to the test signal generated by the test signal in the JTAG signal format, the designated CPLD chip tests the power pin to read and record the value of the power pin as a power test result, or the CPU transmits the ground test signal to the designated CPLD chip through the control pin as a ground test result, and the designated CPLD chip tests the ground pin to read and record the value of the ground pin as a ground test result.

8. The method for testing a DIMM socket of a JTAG-free serial test circuit board according to claim 6, wherein said method for testing a DIMM socket of a JTAG-free serial test circuit board further comprises the steps of:

The test circuit board also comprises an analog-to-digital converter (ADC), wherein the ADC is respectively electrically connected with the appointed CPLD chip and the DIMM plug interface; and

The CPU is used for transmitting the power supply test signal to the appointed CPLD chip through the control pin, the appointed CPLD chip is used for testing the power supply pin through the ADC, so that the numerical value of the power supply pin is read by the ADC, and the CPLD chip is used for reading and recording the numerical value of the power supply pin from the ADC as the power supply test result.

9. The method for testing the DIMM socket of the JTAG-free serial test circuit board according to claim 6, wherein said CPU transmits test data to said CPLD chip designated by said CPU via said differential pin or said input/output pin, said CPLD chip designated by said CPU records the received data as a test result, said CPU generates test data as differential test data according to the test signal in the JTAG signal format, said CPU transmits said differential test data to said CPLD chip designated by said differential pin, and said CPLD chip designated by said CPU records the received data as a differential test result.

10. The method for testing a DIMM socket of a circuit board without JTAG serial test of claim 6, wherein said CPU transmits test data to said CPLD chip via said differential pin or said input/output pin, said CPLD chip records the received data as test result, said CPU generates test data as input/output test data according to the test signal in the JTAG signal format, said CPU transmits said input/output test data to said CPLD chip via said input/output pin, and said CPLD chip records the received data as input/output test result.