CN1180461C - Composite high-density structured substrate and its forming method - Google Patents
Composite high-density structured substrate and its forming method Download PDFInfo
- Publication number
- CN1180461C CN1180461C CNB02147141XA CN02147141A CN1180461C CN 1180461 C CN1180461 C CN 1180461C CN B02147141X A CNB02147141X A CN B02147141XA CN 02147141 A CN02147141 A CN 02147141A CN 1180461 C CN1180461 C CN 1180461C
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- Prior art keywords
- substrate
- viscosity
- formation method
- interconnect structure
- multilayer interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present invention relates to a hybrid high-density interconnected substrate and a forming method thereof. The hybrid high-density interconnected substrate is formed by combining a carrier substrate and a multi-level interconnected structure formed on a handling substrate, and the multi-level interconnected structure is formed with the utilization of a depositing process, a micro-imaging process and an etching process of an integrated circuit.
Description
Technical field
The present invention relates to a kind of baseplate and its formation method, particularly a kind of baseplate and its formation method with highdensity composite multi-layer interconnect structure.
Background technology
The substrate that tradition is used for flip chip assembly process comprises layer reinforced structure (Build-up Structure) and pressing structure (Laminate Structure).Fig. 1 shows a composite packing structure.As shown in Figure 1, a high-density multi-layered interconnect structure 102 is formed on the base material (BaseMaterial) 100.High-density multi-layered interconnect structure 102 and base material 100 constitute the substrate of composite packing structures.High-density multi-layered interconnect structure 102 and one cover the chip 112 put by the solder bond of soldering projection 110 and weld pad 108 to form composite packing structure.Multilayer interconnect structure 102 comprises partly 104 and one circuit part 106 of a dielectric.Multilayer interconnect structure 102 has multilayer dielectric layer and circuit layer, and these multilayer dielectric layer and circuit layer are formed by the mode that increases layer or pressing.
Crystal-coated packing substrate plate has by directly being formed at the multilayer interconnect structure person that forms on the base material layer by layer for increasing laminar substrate.This structure is formed on one microscope carrier/core substrate (Carrier Substrate/Core Substrate) by the direct multilayer interconnect structure that forms, and this microscope carrier substrate is a printed circuit board (PCB).Multilayer interconnect structure directly is formed on the microscope carrier substrate, this kind increase the laminar substrate structure have increase accurately layer conductor/spacing and THICKNESS CONTROL, accurately impedance Control with can be directly with advantages such as passive component implantation.In addition, the structure that increases laminar substrate also can directly form multilayer interconnect structure on the two sides of a microscope carrier substrate simultaneously.However, this kind increases laminar substrate can be adjusted because of the change of substrate size and increase a layer processing procedure at every turn, increases manufacturing cost and reduces shortcomings such as yield so can cause.In addition, because multilayer interconnect structure directly is formed on the microscope carrier substrate, the size that increases laminar substrate will be subject to the size of microscope carrier substrate, and the size maximum constraints of present used microscope carrier substrate is about 610 millimeters * 610 millimeters.
Because the shortcoming of above-mentioned conventional substrate structure and processing procedure, therefore be necessary to develop and a kind of novel board structure that improves and processing procedure to overcome the shortcoming of conventional substrate structure and processing procedure.And the present invention just can meet such demand.
Summary of the invention
A purpose of the present invention is for providing a kind of substrate with highdensity composite multi-layer interconnect structure, and this composite base plate is made of low-density substrate that forms respectively and high-density circuit structure, so have the advantage of high yield.
Another object of the present invention is for providing a kind of substrate with highdensity composite multi-layer interconnect structure, this composite base plate is by existing integrated circuits or Thin Film Transistor-LCD (TFT-LCD) process technique and utilize large-size substrate to form, so have the low advantage of production cost.
Another purpose of the present invention is for providing a kind of substrate with highdensity composite multi-layer interconnect structure, and this composite base plate also has the advantage of impedance Control accurately.
Another object of the present invention is for providing a kind of substrate with highdensity composite multi-layer interconnect structure, and this composite base plate has the advantage that can directly passive component be implanted.
In order to reach above-mentioned purpose, the invention provides a kind of formation method with substrate of multilayer interconnect structure, the formation method of this substrate comprises following steps.One printing opacity operation substrate at first is provided and forms a viscosity photolysis dielectric layer on this operation substrate.Then form a multilayer interconnect structure on this viscosity photolysis dielectric layer.Form a viscosity binding film then on this multilayer interconnect structure.This viscosity binding film of patterning is to expose several weld pads of this multilayer interconnect structure.Then combine this multilayer interconnect structure and this microscope carrier substrate with several conductors on the microscope carrier substrate by this weld pad of solder bond.Decompose this viscosity photolysis dielectric layer and remove this operation substrate.Removing this viscosity photolysis dielectric layer at last.
The simple declaration of above-mentioned relevant invention and following detailed description only are example and unrestricted.Other equivalence that does not break away from spirit of the present invention changes or modifies within the scope of the claims of the present invention that all should be included in.
Description of drawings
Fig. 1 shows a composite packing structure;
Fig. 2 A shows that one has the operation substrate of a base material;
Fig. 2 B shows that a multilayer interconnect structure is formed at the result on the base material;
Fig. 2 C shows that formation one binding film on multilayer interconnect structure, then is patterned to expose the result of weld pad;
The result of Fig. 2 D display chip microscope carrier substrate and multilayer interconnect structure solder bond;
Fig. 2 E demonstration will operate substrate and base material removes, and forms one and has the result of the composite base plate of multilayer interconnect structure;
Fig. 2 F shows the result with composite base plate shown in Fig. 2 E and semiconductor chips incorporate.
Symbol description among the figure
100 base materials
102 high-density multi-layered interconnect structures
104 dielectrics partly
106 circuit partly
108 weld pads
110 soldering projections
112 chips
200 operation substrates
202 base materials
204 multilayer interconnect structures
206 dielectrics partly
208 weld pads
210 interlayer plungers
212 weld pads
214 binding films
216 chip microscope carrier substrates
218 printed circuit board (PCB)s
220 interlayer plungers
222 weld pads
224 conductors
228 dielectric materials
230 soldering projections
232 semiconductor chips
Embodiment
In this mandatory declaration is that fabrication steps described below and structure do not comprise complete processing procedure.The present invention can be implemented by various manufacturing method thereofs, only mentions at this and understands manufacturing method thereof required for the present invention.
Below accompanying drawing according to the present invention is described in detail, please notes that icon is simple form and, and size all is beneficial to understand the present invention by exaggerative not according to scaling.
Shown in figure 2A, show that one has the operation substrate (Handle Substrate) 200 of a base material (Base Material) 202.Operation substrate 200 comprises a printing opacity flat board, particularly a quartz base plate or a glass substrate, and this quartz base plate or glass substrate size can be greater than 610 millimeters * 610 millimeters.One preferred embodiments of operation substrate 200 is for being used for the used glass substrate of Thin Film Transistor-LCD (TFT-LCD) processing procedure.Base material 202 has viscosity, and preferable with the macromolecular material or the fractal film (Release Film) of a tool viscosity.Fractal film is the used dielectric film of general encapsulation procedure, is used for preventing that substrate from polluted by external environment condition in the process that is transported to successive process.In addition, base material 202 can be decomposed with laser beam irradiation by for example ultraviolet ray, and can be removed after being decomposed.
Then, show that a multilayer interconnect structure 204 is formed on the base material 202 with reference to shown in the figure 2B.Multilayer interconnect structure 204 comprises partly 206 and one conduction part of a dielectric.The conduction of multilayer interconnect structure 204 partly comprises weld pad 208,212 and interlayer plunger 210.The icon of multilayer interconnect structure 204 shown in Fig. 2 B for simplifying.Multilayer interconnect structure 204 forms with Thin Film Transistor-LCD processing procedure used equipment and processing procedure, and these processing procedures comprise deposition, little shadow and etch process.In addition, passive component can directly be implanted in the multilayer interconnect structure 204.
Shown in figure 2C, show to form a binding film (Bonding Film) 214 on multilayer interconnect structure 204 that this binding film 214 then is patterned to expose weld pad 212.Binding film 214 comprises a dielectric film with viscosity and adhesive force, can have the characteristic of semi-solid preparation (Semi-Cured).Fig. 2 C shows a chip microscope carrier substrate 216 simultaneously.This chip microscope carrier substrate 216 comprises a printed circuit board (PCB) 218, for example a similar cheaply ball-type multiple substrate (BallGrid Array Like Substrate).This chip microscope carrier substrate 216 has a circuit that comprises weld pad 222 and interlayer plunger 220.Shown in Fig. 2 C, conductor 224 is formed on the weld pad 222.And conductor 224 comprises soldering paste (Solder Paste), metal (Metal SurfaceCoating) or metal coupling (Metal Bump) are being plated in the surface.Soldering paste can form with the mode of scraper printing (SqueegeePrinting), and the surface is being plated the mode that metal and metal coupling can electroplate and formed.Binding film 214 also can be formed on the chip microscope carrier substrate 216 and expose weld pad 222 and be not formed on the multilayer interconnect structure 204.
Then with reference to shown in the figure 2D, by viscosity and the adhesive force of solder bond conductor 224 with weld pad 212 and binding film 214, chip microscope carrier substrate 216 and multilayer interconnect structure 204 solder bond.Then base material 202 is by ultraviolet ray or laser beam irradiation and decomposition.The operation substrate 200 that ultraviolet ray or laser beam penetrate light-permeable arrives base material 202, and provides base material 202 to decompose required heat (Heat Dose).
Shown in figure 2E, demonstration will be operated substrate 200 and remove in regular turn with base material 202, and form a composite base plate with multilayer interconnect structure.The base material 202 that decomposes is to divest (Stripping) or etched mode removes.Fig. 2 F shows the result that composite base plate shown in Fig. 2 E is combined with semiconductor chip 232.Composite base plate and semiconductor chip 232 are fixed and are combined by the filling of the solder bond of weld pad 208 and soldering projection 230 and dielectric material 228 and form composite packing structure.Dielectric material 228 comprises Guan Rubber mixture (MoldingCompound) or covers brilliant (Underfill) thing of filling.
The invention provides a kind of composite base plate with highdensity multilayer interconnect structure.Utilize micron/time micron integrated circuit manufacture process and large scale quartz/glass substrate, the meticulous circuit of high density is formed at earlier on quartz/glass substrate, then is transferred to non-cheaply increasing on the laminar substrate again.Owing to use mature and stable process technique and large-sized operation substrate, but not directly the fine circuitry pattern is increased on layer core substrate (CoreSubstrate) that is formed at the limited and low yield of size, the production cost of the composite base plate of this multilayer interconnect structure is lower than traditional laminar substrate that increases.The present invention is simultaneously by forming low-density substrate and high-density circuit structure respectively, but not directly forms the high-density circuit structure on core substrate, can improve the yield of composite base plate, makes its yield be higher than tradition and increases the laminar substrate processing procedure.The multilayer interconnect structure process technique of utilizing high accurancy and precision and density has the circuit and the dielectric layer of meticulous, accurate width and thickness with formation, and the present invention can provide good impedance Control.In addition, passive component is directly implanted in the multilayer interconnect structure can be promoted composite packing structure than excellent electrical property.In addition, utilizing process apparatus, processing procedure and conductor, the dielectric material of existing integrated circuits or Thin Film Transistor-LCD to form multilayer interconnect structure can provide and stablize good properties.
Above-mentioned relevant detailed description of the invention only is an example and unrestricted.Other equivalence that does not break away from spirit of the present invention changes or modifies within claims scope of the present invention that all should be included in.
Claims (10)
1. the formation method with compound high density baseplate of multilayer interconnect structure is characterized in that, the formation method of this substrate comprises:
One printing opacity operation substrate is provided;
Form a viscosity photolysis dielectric layer on this operation substrate;
Form a multilayer interconnect structure on this viscosity photolysis dielectric layer, the surface of this multilayer interconnect structure has several weld pads;
One microscope carrier substrate is provided, and this microscope carrier substrate is provided with several conductors of protuberate;
The viscosity binding film of one patterning is provided, wherein if this viscosity binding film is formed on this multilayer interconnect structure, then expose these several weld pads of this multilayer interconnect body structure surface, if this viscosity binding film is formed at this microscope carrier substrate surface, then expose these several conductors of this microscope carrier substrate surface;
By welding respectively in conjunction with these several conductors on these several weld pads and this microscope carrier substrate, with in conjunction with this multilayer interconnect structure and this microscope carrier substrate;
Decompose this viscosity photolysis dielectric layer;
Remove this operation substrate; And
Remove this viscosity photolysis dielectric layer.
2. the formation method of substrate as claimed in claim 1 is characterized in that, this above-mentioned operation substrate is one of quartz base plate and glass substrate.
3. the formation method of substrate as claimed in claim 1, it is characterized in that, this above-mentioned viscosity photolysis dielectric layer comprises a fractal film, and it is the used dielectric film of general encapsulation procedure, is used for preventing that substrate from polluted by external environment condition being transported to the follow-up process of making.
4. the formation method of substrate as claimed in claim 1 is characterized in that, this above-mentioned multilayer interconnect structure forms with the deposition of Thin Film Transistor-LCD technology, little shadow and etch process.
5. the formation method of substrate as claimed in claim 1 is characterized in that, this above-mentioned viscosity binding film can be half cured film.
6. the formation method of substrate as claimed in claim 1 is characterized in that, this above-mentioned microscope carrier substrate can be a printed circuit board (PCB).
7. the formation method of substrate as claimed in claim 1 is characterized in that, this above-mentioned conductor can be soldering paste, metal coupling, surface plating metal one of them.
8. the formation method of substrate as claimed in claim 1 is characterized in that, this above-mentioned viscosity photolysis dielectric layer is with laser beam and one of them decomposition of ultraviolet ray.
9. the formation method of substrate as claimed in claim 1 is characterized in that, this above-mentioned viscosity photolysis dielectric layer removes with etching method.
10. the formation method of substrate as claimed in claim 1 is characterized in that, is embedded with passive component in this above-mentioned multilayer interconnect structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02147141XA CN1180461C (en) | 2002-10-23 | 2002-10-23 | Composite high-density structured substrate and its forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02147141XA CN1180461C (en) | 2002-10-23 | 2002-10-23 | Composite high-density structured substrate and its forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1405868A CN1405868A (en) | 2003-03-26 |
| CN1180461C true CN1180461C (en) | 2004-12-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB02147141XA Expired - Lifetime CN1180461C (en) | 2002-10-23 | 2002-10-23 | Composite high-density structured substrate and its forming method |
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| Country | Link |
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| CN (1) | CN1180461C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009006761A1 (en) * | 2007-07-12 | 2009-01-15 | Princo Corp. | Multi-layer baseboard and manufacturing method thereof |
| US7656679B2 (en) | 2007-06-20 | 2010-02-02 | Princo Corp. | Multi-layer substrate and manufacture method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9049791B2 (en) * | 2013-06-07 | 2015-06-02 | Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co. Ltd. | Terminations and couplings between chips and substrates |
| CN106658967B (en) * | 2015-10-30 | 2019-12-20 | 奥特斯(中国)有限公司 | Component carrier with alternating vertically stacked layer structure of different charge density |
-
2002
- 2002-10-23 CN CNB02147141XA patent/CN1180461C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7656679B2 (en) | 2007-06-20 | 2010-02-02 | Princo Corp. | Multi-layer substrate and manufacture method thereof |
| WO2009006761A1 (en) * | 2007-07-12 | 2009-01-15 | Princo Corp. | Multi-layer baseboard and manufacturing method thereof |
| EP2190273A1 (en) * | 2007-07-12 | 2010-05-26 | Princo Corp. | Multi-layer baseboard and manufacturing method thereof |
| EP2190273A4 (en) * | 2007-07-12 | 2011-02-16 | Princo Corp | Multi-layer baseboard and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN1405868A (en) | 2003-03-26 |
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