CN118042921A - Method for manufacturing capacitor - Google Patents

Method for manufacturing capacitor Download PDF

Info

Publication number
CN118042921A
CN118042921A CN202311507996.0A CN202311507996A CN118042921A CN 118042921 A CN118042921 A CN 118042921A CN 202311507996 A CN202311507996 A CN 202311507996A CN 118042921 A CN118042921 A CN 118042921A
Authority
CN
China
Prior art keywords
comprised
layer
around
electrode
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311507996.0A
Other languages
Chinese (zh)
Inventor
V·卡罗
Q·保利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Italian Semiconductor International Co
Original Assignee
Italian Semiconductor International Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/385,036 external-priority patent/US20240162279A1/en
Application filed by Italian Semiconductor International Co filed Critical Italian Semiconductor International Co
Publication of CN118042921A publication Critical patent/CN118042921A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present disclosure relates to a method of manufacturing a capacitor comprising the following successive steps: a) Forming a stack including a first electrode, a dielectric layer, a second electrode, and a second conductive layer in this order from a top surface of the first conductive layer; b) Forming a masking layer on a surface of the second conductive layer opposite to the second electrode by photolithography; c) Etching a top portion of the stack through the masking layer by a chlorinated physicochemical plasma etch, the chlorinated physicochemical plasma etch stopping within the dielectric layer; d) Etching a bottom portion of the stack through the masking layer by a fluorinated physicochemical plasma etch that stops on a top surface of the first conductive layer; and e) removing the masking layer.

Description

Method for manufacturing capacitor
Cross Reference to Related Applications
The present application claims the priority of the French patent application No. 22/11799 entitled "Proc de fabric d' un condensateur," filed on month 14 of 2022, which is incorporated herein by reference in its entirety.
Technical Field
The present disclosure relates generally to the fabrication of integrated circuits, and more particularly to the fabrication of integrated circuits including capacitors, such as passive integrated circuits, e.g., RC filters (including resistors and capacitors), LC filters (including inductors and capacitors), or RLC filters (including resistors, inductors, and capacitors).
Background
Various methods of fabricating integrated circuits including capacitors have been provided. These methods have various drawbacks. Accordingly, there is a need for an improved method of manufacturing an integrated circuit comprising a capacitor in order to overcome all or some of the disadvantages of the known methods.
Disclosure of Invention
One embodiment provides a method of manufacturing a capacitor comprising the following successive steps:
a) Forming a stack comprising, in order from a top surface of the first conductive layer, a first electrode, a dielectric layer, a second electrode, and a second conductive layer;
b) Forming a masking layer on a surface of the second conductive layer opposite to the second electrode by photolithography;
c) Etching a top portion of the stack through the masking layer by a chlorinated physicochemical plasma etch that stops within a dielectric layer;
d) Etching a bottom portion of the stack through the masking layer by a fluorinated physicochemical plasma etch that stops on a top surface of the first conductive layer; and
E) The masking layer is removed by a lift-off method and then the etched sides are cleaned by a cleaning method.
According to an embodiment, the first conductive layer is an aluminum-based layer.
According to an embodiment, the second conductive layer is an aluminum-based layer.
According to an embodiment, in step c), chlorine and boron trichloride are injected into the plasma source.
According to an embodiment, in step c), chlorine is injected at a rate comprised between 50sccm and 120sccm, for example around 80sccm, and boron trichloride is injected at a rate comprised between 20sccm and 100sccm, for example around 50 sccm.
According to an embodiment, in step c), the plasma pressure is comprised between 1.33Pa and 6.67Pa, for example around 2Pa, the source power is comprised between 150W and 800W, for example around 400W, and the bias power is comprised between 50W and 500W, for example comprised between 150W and 300W.
According to an embodiment, in step d), sulfur hexafluoride and argon are injected into the plasma source.
According to an embodiment, in step d), sulfur hexafluoride is injected at a rate comprised between 20sccm and 80sccm, for example around 50sccm, and argon is injected at a rate comprised between 10sccm and 100sccm, for example around 20 sccm.
According to an embodiment, in step c), the plasma pressure is comprised between 0.67Pa and 6.67Pa, for example around 1.33Pa, the source power is comprised between 150W and 800W, for example around 500W, and the bias power is comprised between 20W and 500W, for example around 50W.
According to an embodiment, in step e), the cleaning method comprises cleaning the top and side surfaces of the second conductive layer, the side surfaces of the second electrode, the side surfaces of the dielectric layer, the side surfaces of the first electrode and the top surface of the first conductive layer.
According to an embodiment, the stripping step is performed by plasma physicochemical etching.
According to an embodiment, in the stripping step, molecular oxygen and water vapor are injected into the plasma source.
According to an embodiment, in the stripping step, molecular oxygen is injected at a rate comprised between 700sccm and 1000sccm, for example around 810sccm, and water vapour is injected at a rate comprised between 50sccm and 700sccm, for example around 90sccm or around 630 sccm.
According to an embodiment, in the stripping step, the plasma pressure is comprised between 80Pa and 133.32Pa, for example comprised between 100Pa and 120Pa, and the RF power is comprised between 800W and 1500W, for example around 1100W.
According to an embodiment, the cleaning step is performed using a 2- (2-aminoethoxy) ethanol based and a hydroxylamine based solvent.
According to an embodiment, the content of 2- (2-aminoethoxy) ethanol in the solvent is comprised between 55% and 65% and the content of hydroxylamine is comprised between 10% and 20%, wherein each% is weight%.
Drawings
The foregoing and other features and advantages will be described in detail in the following description of particular embodiments, given by way of example and not limitation, with reference to the accompanying drawings, in which:
FIG. 1 is a partial and schematic cross-sectional view of an example capacitor; and
Fig. 2, 3, 4 and 5 illustrate successive steps of an example method of manufacturing a capacitor according to another embodiment.
Detailed Description
Like features are denoted by like reference numerals throughout the various figures. In particular, structural and/or functional features common between the various embodiments may have the same reference numerals and consistent structural, dimensional, and material properties may be deployed.
For clarity, only the operations and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, we primarily consider herein the fabrication of a portion of an integrated circuit that forms a capacitor. More specifically, we consider herein primarily an etching step that allows a metal layer to be exposed to make electrical contacts over the bottom electrode of the capacitor of the integrated circuit. Other steps of the method of manufacturing capacitors and integrated circuits are within the ability of those skilled in the art and will not be described further below.
Unless otherwise indicated, when two elements are referred to as being connected together, this means that there is no direct connection of any intermediate elements other than conductors, and when two elements are referred to as being coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.
In the following disclosure, unless otherwise indicated, when absolute positional qualifiers (such as the terms "front", "rear", "top", "bottom", "left", "right", etc.) are referred to, or when relative positional qualifiers (such as the terms "above", "below", "higher", "lower", etc.) are referred to, or when orientation qualifiers (such as "horizontal", "vertical", etc.) are referred to, reference is made to the orientation shown in the drawings.
Unless specified otherwise, the expressions "about", "approximately", "substantially" and "about" mean within 10%, and preferably within 5%.
Fig. 1 is a partial and schematic cross-sectional view of an example capacitor 11.
The capacitor 11 includes, in order from the top surface of the substrate or holder 21:
the first conductive layer 13, also known as a redistribution layer (RDL);
A first electrode 15, also called bottom electrode;
a layer 17 made of a dielectric material;
a second electrode 19, also called top electrode; and
A second conductive layer 23.
As an example, the bottom electrode 15 contacts the top surface of the layer 13 through its bottom surface. The dielectric layer 17 contacts the top surface of the bottom electrode 15, for example by its bottom surface. The top electrode 19 contacts the top surface of the dielectric layer 17, for example by its bottom surface. The conductive layer 23 contacts the top surface of the top electrode 19, for example, by its bottom surface.
As an example, the conductive layer 13 is made of a metal material. The conductive layer 13 is made of, for example, aluminum or an alloy containing aluminum. The conductive layer 13 is made of, for example, an alloy of aluminum and copper (AlCu) or an alloy of aluminum, copper and silicon (AlSiCu). As an example, the layer 13 has a thickness comprised between 0.5 μm and 3 μm, for example around 1.5 μm.
The electrode 15 is made of, for example, tantalum nitride (TaN). As an example, the electrode 15 has a thickness comprised between 20nm and 200nm, for example around 65 nm. The electrode 19 is made of, for example, tantalum nitride (TaN). As an example, the electrode 19 has a thickness comprised between 20nm and 200nm, for example around 65 nm. The electrodes 15 and 19 are for example made of the same material.
The dielectric layer 17 is made of, for example, silicon nitride. As an example, the dielectric layer 17 has a thickness comprised between 20nm and 600nm, for example comprised between 100nm and 450 nm.
The holder 21 is made of, for example, silicon, and preferably has high resistance. The holder 21 and the layer 13 may be spaced apart from each other by a dielectric layer (not shown), for example an oxide layer, such as Undoped Silicate Glass (USG) or any other silicon oxide. Alternatively, the bottom conductive layer 13 contacts the top surface of the substrate 21 through its bottom surface. The substrate 21 holds, for example, one or more other elements not shown, such as an inductor or a resistor, which is made near the capacitor and electrically connected to the capacitor.
As an example, the conductive layer 23 is made of a metal material. The conductive layer 23 is made of, for example, a metal material that can be etched by plasma (e.g., chlorinated plasma). As an example, the conductive layer 23 is made of aluminum or an aluminum-based alloy. The conductive layer 23 has a thickness comprised between 100nm and 1 μm, for example around 350 nm. Layer 23 in particular allows the conductivity of the top electrode 19 it covers to be increased.
In example fig. 1, the sides of the top portions of conductive layer 23, electrode 19, and dielectric layer 17 are recessed compared to the sides of the bottom portions of electrode 15 and dielectric layer 17. In other words, a portion of the bottom portion of the dielectric layer 17 is not covered by the top portion of the dielectric layer 17, the top electrode 19 and the conductive layer 23. Thus, in fig. 1, there is a first step between the top surface of the top conductive layer 23 and the top surface of the dielectric layer 17. This step allows to introduce a horizontal distance e1 between the sides of the layers 23 and 19 and the top part of the layer 17 on the one hand and the bottom part of the layer 17 and the side of the electrode 15 on the other hand, thus reducing the chance of short circuits.
As an example, the top portions of the conductive layer 23, the electrode 19 and the dielectric layer 17 are aligned vertically in fig. 1, i.e. their sides are aligned. Similarly, the bottom portions of the electrode 15 and the dielectric layer 17 are aligned, for example vertically.
In example fig. 1, electrodes 15 and 19 and layers 23 and 17 are recessed relative to conductive layer 13. In other words, a portion of the top surface of conductive layer 13 is not covered by electrodes 15 and 19 and layers 23 and 17. Thus, in fig. 1, there is a second step between the top surface of the dielectric layer 17 and the top surface of the bottom conductive layer 13. This allows electrical contact to be made to the top electrode 15 of the capacitor during manufacturing steps not described in detail via the conductive layer 13, for example by means of a metal wire soldered to the top surface of the exposed portion of the layer 13.
As an example, to form the structure shown in fig. 1, layer 13, electrode 15, layer 17, electrode 19, and layer 23 are first deposited successively on substrate 21. At this time, each of the layer 13, the electrode 15, the layer 17, the electrode 19, and the layer 23 extends continuously on the top surface of the substrate 21 with a remarkably uniform thickness. Then, during a first photolithography and etching step, the top portions of layer 23, electrode 19 and dielectric layer 17 are locally etched, thereby forming a first step. Then, during the second photolithography and etching step, a bottom portion of the dielectric layer 17 and the bottom electrode 15 are locally removed opposite to a portion of the surface of the dielectric layer 17 exposed at the end of the first step, thereby forming a second step.
As an example, the two etching steps are physicochemical plasma etching by means of plasmas with different recipes.
Etching the stack in two stages allows etching layers 23 and 17 and electrodes 15 and 19 without etching layer 13. Both layers 23 and 13 are, for example, aluminum-based layers, with a top portion of the stack (e.g., at least layer 23) being etched using an etch that is non-selective to aluminum, and a bottom portion of the stack (e.g., at least electrode 15) being etched using an etch that is selective to aluminum. The top portions of the conductive layer 23, the electrode 19 and the dielectric layer 17 are etched, for example, by a chlorided plasma physicochemical etch. The bottom portions of the electrode 15 and the dielectric layer 17 are etched, for example, by a fluorinated plasma physicochemical etch.
During etching of layer 23, however, the chlorided plasma physicochemical etching results in the generation of aluminum-based residues deposited on the sides of the etched area. These residues are, for example, conductive and may cause a short circuit or breakdown opportunity for the capacitor. The first and second steps formed between the top surface of layer 23 and the top surface of layer 17 and between the top surface of layer 17 and the top surface of layer 13, respectively, aim to reduce this problem. In fact, these steps allow to introduce a horizontal distance e1 between the sides of the layers 23 and 19 and of the top portion of the layer 17 on the one hand and the bottom portion of the layer 17 and of the electrode 15 on the other hand, thus reducing the chances of faults (such as short circuits) associated with the presence of residues generated during the first etching step.
The structure of fig. 1 is limited in that its fabrication implies two photolithographic steps to form the first and second steps, respectively. Therefore, the manufacturing cost is high.
Fig. 2, 3, 4 and 5 illustrate successive steps of an example method of manufacturing a capacitor according to another embodiment.
Fig. 2 illustrates an initial stack comprising, in order from the top surface of the substrate 21, a first conductive layer 13, a first electrode 15, a dielectric layer 17, a second electrode 19 and a second conductive layer 23.
Layers 13, 17 and 23 and electrodes 15 and 19 are similar to layers 13, 17 and 23 and electrodes 15 and 19 described in connection with fig. 1. Moreover, the arrangement of these layers and electrodes is similar to that described in connection with fig. 1, except that layers 13, 17 and 23 and electrodes 15 and 19 are now aligned. In particular, electrodes 15 and 19 and layers 13, 17 and 23 each extend over the entire top surface of substrate 21.
Fig. 3 illustrates the structure obtained at the end of the step of forming a masking layer 25 over the top surface of the structure shown in fig. 2. As an example, the masking layer 25 is formed by photolithography.
To this end, a masking layer 25 is formed, for example in a first stage, over the top surface of the layer 23, and contacts, for example, the top surface of the layer 23. In a second stage, masking layer 25 is locally exposed to light radiation, such as ultraviolet radiation (UV), for example, through a photolithographic mask. After development and rinsing, layer 25 remains opposite a portion of the stack where the capacitor is to be formed and is almost entirely removed.
The masking layer 25 is made of, for example, a resin such as a photosensitive resin.
Fig. 4 illustrates the structure obtained at the end of the first step of etching the top portion of the stack of structures shown in fig. 3.
During this step, the top portion of the stack of layers 23, 19 and 17 is etched more precisely by chlorided plasma physicochemical etching, through masking layer 25. Even more precisely, during this step, the top portions of the conductive layer 23, the electrode 19 and the dielectric layer 17 are etched through the masking layer 25. As an example, during this step, the conductive layer 23, the electrode 19 and the top portion of the dielectric layer 17 are removed on the outside opposite the masking layer 25.
During this step, the chlorided plasma physicochemical etch is terminated within the dielectric layer 17.
The chloridized plasma physicochemical etching is, for example, a vertical anisotropic etching. It is oriented and it occurs primarily along a single preferential direction, here the vertical direction in the orientation of fig. 4 (i.e., the direction perpendicular relative to the top surface of the substrate 21).
As an example, the etching step is implemented using a plasma, the pressure of which is, for example, comprised between 5mTorr (i.e. 0.67 Pa) and 100mTorr (i.e. 13.33 Pa), for example comprised between 10mTorr (i.e. 1.33 Pa) and 50mTorr (i.e. 6.67 Pa), for example around 15mTorr (i.e. 2 Pa). During this step, the source power is for example comprised between 100W and 1800W, for example comprised between 150W and 800W, for example around 400W. During this step, the bias power is for example comprised between 20W and 1000W, for example comprised between 50W and 500W, for example comprised between 150W and 300W. During this step, chlorine (Cl 2) is injected, for example, in the plasma source. The rate of chlorine is for example comprised between 10sccm (or cm 3.min-1 at 0 ℃ and atmospheric pressure) and 500sccm, for example comprised between 50sccm and 120sccm, for example around 80 sccm. During this step, for example, boron trichloride (BCl 3) is injected into the plasma source. As an example, during this step, the rate of boron trichloride is comprised between 10sccm and 500sccm, for example comprised between 20sccm and 100sccm, for example around 50 sccm. During this step, boron trichloride and chlorine, for example, are injected into the plasma source. During this step, boron trichloride and chlorine, for example, are injected into the plasma source at the rates described above, for example. As an example, during this step the temperature of the bottom electrode is comprised between 20 ℃ and 100 ℃, for example comprised between 30 ℃ and 70 ℃, for example around 50 ℃. As an example, during this step the temperature of the top electrode is comprised between 20 ℃ and 100 ℃, e.g. comprised between 50 ℃ and 90 ℃, e.g. around 70 ℃.
Fig. 5 illustrates the structure obtained at the end of the second step of etching the bottom portion of the stack of structures shown in fig. 4.
Masking layer 25 is not removed at the end of the chlorided plasma physicochemical etch described with respect to fig. 4, and it is actually held in place during the fluorinated plasma physicochemical etch step described with respect to fig. 5. Thus, both physicochemical etching steps are performed through the same masking layer 25.
During this step, the bottom portion of the stack of layers 23, 19, 17 and 15 is etched more precisely by the fluorinated plasma physicochemical etching, through masking layer 25. Even more precisely, during this step the bottom portion of the dielectric layer 17 and the electrode 15 are etched through the masking layer 25. As an example, during this step, the bottom portion of the dielectric layer 17 and the electrode 15 are removed on the outside opposite the masking layer 25.
The fluorinated plasma physicochemical etching has the following advantages: the bottom portion of dielectric layer 17 and electrode 15 are etched in a selective manner with respect to layer 13, including, for example, aluminum. During this step, the fluorinated plasma physicochemical etch thus stops on the top surface of layer 13 without etching layer 13.
The fluorinated plasma physicochemical etch is, for example, a vertical anisotropic etch. It is oriented and it occurs primarily along a single preferential direction, here the vertical direction in the orientation of fig. 5.
As an example, the etching step is performed by means of a plasma, the pressure of which is for example comprised between 5mTorr (i.e. 0.67 Pa) and 100mTorr (i.e. 13.33 Pa), for example comprised between 5mTorr (i.e. 1.67 Pa) and 50mTorr (i.e. 6.67 Pa), for example around 10mTorr (i.e. 1.33 Pa). During this step, the source power is for example comprised between 100W and 1800W, for example comprised between 150W and 800W, for example around 500W. During this step, the bias power is for example comprised between 20W and 1000W, for example comprised between 20W and 500W, for example around 50W. During this step, sulfur hexafluoride (SF 6) is injected into the plasma source, for example. The rate of sulfur hexafluoride power is, for example, comprised between 10sccm (or cm 3.min-1 at 0 ℃ and atmospheric pressure) and 500sccm, for example comprised between 20sccm and 80sccm, for example around 50 sccm. During this step, for example, argon (Ar) is injected into the plasma source. As an example, during this step, the rate of argon is comprised between 10sccm and 500sccm, for example comprised between 10sccm and 100sccm, for example around 20 sccm. During this step, sulfur hexafluoride and argon are injected into the plasma source, for example. By way of example, sulfur hexafluoride and argon are injected into the plasma source during this step, for example, at the rates mentioned above. As an example, during this step the temperature of the bottom electrode is comprised between 20 ℃ and 100 ℃, for example comprised between 30 ℃ and 70 ℃, for example around 50 ℃. As an example, during this step the temperature of the top electrode is comprised between 20 ℃ and 100 ℃, e.g. comprised between 50 ℃ and 90 ℃, e.g. around 70 ℃.
As an example, both the fluorinated plasma physicochemical etching step and the chlorinated plasma physicochemical etching step are performed in two etching processes (settlement) of the same type.
Masking layer 25 is removed at the end of the step of etching the bottom portions of electrode 15 and dielectric layer 17 using the fluorinated plasma.
For example, masking layer 25 is removed during the lift-off step. This step corresponds for example to downstream plasma physicochemical etching. As an example, this step is performed in the same etching process (settlement) as the chloridized plasma physicochemical etching step (fig. 4) and/or the fluorinated plasma physicochemical etching step (fig. 5). As an example, the lift-off step of the masking layer 25 is performed at a pressure comprised, for example, between 300mTorr (i.e., 40 Pa) and 1200mTorr (i.e., 160 Pa), for example, between 600mTorr (i.e., 80 Pa) and 1000mTorr (i.e., 133.32 Pa), for example, between 750mTorr (i.e., 100 Pa) and 900mTorr (i.e., 120 Pa). During this step, the RF power is for example comprised between 600W and 1800W, for example comprised between 800W and 1500W, for example around 1100W. During this step, oxygen (O 2) is injected into the plasma source, for example. The oxygen rate is for example comprised between 500sccm and 1200sccm, for example comprised between 700sccm and 1000sccm, for example around 810 sccm. During this step, for example, water vapor (H 2 O) is injected into the plasma source. The rate of water vapor is for example comprised between 10sccm and 1000sccm, for example comprised between 50sccm and 700sccm, for example around 90sccm or around 630 sccm. As an example, during this step, water vapor and oxygen are injected into the plasma source. As an example, during this step, water vapor and oxygen are injected into the plasma source at the rates mentioned above. As an example, the duration of the peeling step is comprised between 1 second and 150 seconds, for example comprised between 2 seconds and 120 seconds, for example comprised between 5 seconds and 90 seconds.
For example, after the stripping step, the top surface of conductive layer 23, the top surface of layer 13, and the sides of layers 23, 17, and 13 and electrodes 19 and 15 are cleaned. This step allows, for example, to remove residues (e.g., polymer residues) present at the surface of the conductive layer 23 from the masking layer 25. This step also allows, as an example, the removal of etching residues of layers 23 and 17 and of electrodes 19 and 15 formed on the sides of these same layers and electrodes. This step is performed, for example, using a solvent.
This step is performed using, as an example, 2- (2-aminoethoxy) ethanol and hydroxylamine-based solvents. This step is carried out using, as an example, solvents based on 2- (2-aminoethoxy) ethanol, on hydroxylamine, on catechol and on hydroquinone.
As an example, this step is performed using a 2- (2-aminoethoxy) ethanol-based and a hydroxylamine-based solvent, the content of 2- (2-aminoethoxy) ethanol being for example comprised between 35% and 80%, for example comprised between 55% and 65%, and the content of hydroxylamine being for example comprised between 10% and 20%. As an example, this step is performed using a hydroxylamine-based, catechol-based and hydroquinone-based solvent based on 2- (2-aminoethoxy) ethanol, the content of 2- (2-aminoethoxy) ethanol being for example comprised between 35% and 80%, for example comprised between 55% and 65%, and the content of hydroxylamine being for example comprised between 2% and 35%, for example comprised between 10% and 20%, the content of catechol being for example comprised between 1% and 20%, for example comprised between 3% and 10%, and the content of hydroquinone being for example comprised between 0.001% and 1%, for example comprised between 0.01% and 0.1%.
This step is performed using, as an example, a solvent of the type sold by dupont under reference EKC 265.
At the end of the method described in connection with fig. 3 to 5, the sides of layers 17 and 23 and electrodes 15 and 19 are clearly aligned vertically.
It should be noted that the etching rate of electrodes 15 and 19 may be slightly higher than the etching rate of layers 17 and 23, depending on the materials used. In this case, at the end of the etching step, the sides of electrodes 15 and 19 may exhibit a depression with respect to the sides of layers 17 and 23.
At the end of the method described in connection with fig. 2 to 5, a metal pad (not shown), for example made of copper, is for example arranged on the top surface of the conductive layer 23 and contacts the top surface of the conductive layer 23.
The advantages of this embodiment relate to the choice of etching recipe, the choice of stripping mode and the choice of cleaning, which allows to limit the formation of conductive residues on the sides of the etched area.
The formation of the step (guard distance e 1) described with respect to fig. 1 can therefore be omitted.
An advantage is that it allows to reduce the number of steps and thus the manufacturing costs of the capacitor with respect to a method of the type described in relation to fig. 1. In particular, the method described with respect to fig. 2 to 5 comprises a single lithographic step (single lithographic mask) compared to two lithographic steps in the method described with respect to fig. 1.
Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of the embodiments may be combined and that other variations will readily occur to those skilled in the art. In particular, although the chlorided plasma physicochemical etch has been described as stopping within layer 17, the physicochemical etch may stop on the top surface of dielectric layer 17.
Finally, based on the functional description provided above, the actual implementation of the embodiments and variants described herein is within the ability of those skilled in the art.

Claims (16)

1. A method of manufacturing a capacitor comprising the successive steps of:
a) Forming a stack comprising, in order from a top surface of the first conductive layer, a first electrode, a dielectric layer, a second electrode, and a second conductive layer;
b) Forming a masking layer on a surface of the second conductive layer opposite to the second electrode by photolithography;
c) Etching a top portion of the stack through the masking layer by a chlorinated physicochemical plasma etch that stops within a dielectric layer;
d) Etching a bottom portion of the stack through the masking layer by a fluorinated physicochemical plasma etch that stops on a top surface of the first conductive layer;
e) The masking layer is removed by a lift-off method and then the etched sides are cleaned by a cleaning method.
2. The method of claim 1, wherein the first conductive layer is an aluminum-based layer.
3. The method of claim 1, wherein the second conductive layer is an aluminum-based layer.
4. The method of claim 1, wherein in step c), chlorine and boron trichloride are injected into the plasma source.
5. The method according to claim 4, wherein in step c) chlorine is injected at a rate comprised between 50 seem and 120 seem, for example around 80 seem, and boron trichloride is injected at a rate comprised between 20 seem and 100 seem, for example around 50 seem.
6. The method according to claim 1, wherein in step c) the plasma pressure is comprised between 1.33Pa and 6.67Pa, such as around 2Pa, the source power is comprised between 150W and 800W, such as around 400W, and the bias power is comprised between 50W and 500W, such as comprised between 150W and 300W.
7. The method of claim 1, wherein in step d), sulfur hexafluoride and argon are injected into the plasma source.
8. The method according to claim 7, wherein in step d) sulphur hexafluoride is injected at a rate comprised between 20 seem and 80 seem, for example around 50 seem, and argon is injected at a rate comprised between 10 seem and 100 seem, for example around 20 seem.
9. The method according to claim 1, wherein in step c) the plasma pressure is comprised between 0.67Pa and 6.67Pa, such as around 1.33Pa, the source power is comprised between 150W and 800W, such as around 500W, and the bias power is comprised between 20W and 500W, such as around 50W.
10. The method of claim 1, wherein in step e), the cleaning method comprises cleaning the top and side surfaces of the second conductive layer, the side surfaces of the second electrode, the side surfaces of the dielectric layer, the side surfaces of the first electrode, and the top surface of the first conductive layer.
11. The method of claim 10, wherein the step of stripping is performed by physicochemical plasma etching.
12. The method of claim 11, wherein in the stripping step, molecular oxygen and water vapor are injected into the plasma source.
13. The method of claim 12, wherein in the stripping step, molecular oxygen is injected at a rate comprised between 700sccm and 1000sccm, such as around 810sccm, and water vapor is injected at a rate comprised between 50sccm and 700sccm, such as around 90sccm or around 630 sccm.
14. The method according to claim 11, wherein in the stripping step the plasma pressure is comprised between 80Pa and 133.32Pa, such as comprised between 100Pa and 120Pa, and the RF power is comprised between 800W and 1500W, such as around 1100W.
15. The method of claim 10, wherein the cleaning step is performed using a 2- (2-aminoethoxy) ethanol-based and hydroxylamine-based solvent.
16. The method of claim 15, wherein the content of 2- (2-aminoethoxy) ethanol in the solvent is comprised between 55% and 65% and the content of hydroxylamine is comprised between 10% and 20%, wherein each% is weight%.
CN202311507996.0A 2022-11-14 2023-11-14 Method for manufacturing capacitor Pending CN118042921A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2211799 2022-11-14
US18/385,036 2023-10-30
US18/385,036 US20240162279A1 (en) 2022-11-14 2023-10-30 Method of fabricating a capacitor

Publications (1)

Publication Number Publication Date
CN118042921A true CN118042921A (en) 2024-05-14

Family

ID=90995840

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311507996.0A Pending CN118042921A (en) 2022-11-14 2023-11-14 Method for manufacturing capacitor

Country Status (1)

Country Link
CN (1) CN118042921A (en)

Similar Documents

Publication Publication Date Title
US8282842B2 (en) Cleaning method following opening etch
JP4557479B2 (en) Photoresist removal process using forming gas plasma
US6331480B1 (en) Method to improve adhesion between an overlying oxide hard mask and an underlying low dielectric constant material
US7759244B2 (en) Method for fabricating an inductor structure or a dual damascene structure
CN101211819A (en) Semiconductor device metal connection hole preparation method
CN118042921A (en) Method for manufacturing capacitor
KR100551326B1 (en) Method for manufacturing a semiconductor device having capacitor
JP2004235256A (en) Semiconductor device and its fabricating process
US20220190103A1 (en) Capacitor manufacturing method
TWI354333B (en) Cleaning method following opening etch
JP5234047B2 (en) Manufacturing method of semiconductor device
KR100778869B1 (en) Method for forming contact of semiconductor device
US20240162279A1 (en) Method of fabricating a capacitor
KR100824627B1 (en) Method of manufaturing semiconductor device
KR100492914B1 (en) Fabrication method of metal interconnection for semiconductor
KR100833394B1 (en) Method of forming capacitor
TWI701768B (en) Method of manufacturing interconnect structure
KR100253315B1 (en) Etching method in oder to form wire of semiconductor device
KR100802311B1 (en) Method for fabricating cmos image sensor
US20240258108A1 (en) Selective Deposition of Passivating Layer During Spacer Etching
KR20100077858A (en) Method for forming metal line of semiconductor device
KR100355873B1 (en) a method of manufacturing a semiconductor device
JPH11238732A (en) Wiring structure and formation of bonding pad opening
KR100876860B1 (en) Method of forming multi-layer metal wiring of semiconductor device
JP3592642B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination