CN118039729A

CN118039729A - Semiconductor structure and preparation method thereof, detection substrate and preparation method thereof, and detection device

Info

Publication number: CN118039729A
Application number: CN202410176051.3A
Authority: CN
Inventors: 李伟; 章凯迪; 林柏全; 张东莉; 王丽影; 潘俊涛
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2024-02-07
Filing date: 2024-02-07
Publication date: 2024-05-14

Abstract

The invention discloses a semiconductor structure, a preparation method thereof, a detection substrate, a preparation method thereof and a detection device. The semiconductor structure comprises a substrate, a semiconductor layer and a gate layer, wherein the semiconductor layer and the gate layer are arranged on one side of the substrate, the gate layer and the semiconductor layer are insulated, the semiconductor layer comprises an N-type doped region, an N-type semiconductor region and a P-type doped region, the N-type semiconductor region is arranged between the N-type doped region and the P-type doped region, the ion doping concentration of the N-type doped region is larger than that of the N-type semiconductor region, the ion doping concentration of the P-type doped region is larger than that of the N-type semiconductor region, and the gate layer covers the N-type semiconductor region along the thickness direction of the substrate. The semiconductor structure, the preparation method thereof, the detection substrate, the preparation method thereof and the detection device provided by the embodiment of the invention realize the functions of signal conversion and optical detection, and simultaneously have the advantages of less number of process procedures, simple manufacturing process and low preparation cost.

Description

Semiconductor structure and preparation method thereof, detection substrate and preparation method thereof, and detection device

Technical Field

The invention relates to the technical field of display, in particular to a semiconductor structure, a preparation method thereof, a detection substrate, a preparation method thereof and a detection device.

Background

In the fields of signal conversion, optical detection and the like, a photosensitive device plays a key role.

Currently, the photosensitive devices commonly used in the fields of signal conversion, optical detection and the like comprise PIN type photodiodes, the PIN type photodiodes adopt a three-layer structure and are manufactured based on a silicon-based manufacturing process, and the manufacturing process is complex and has high cost.

Disclosure of Invention

The invention provides a semiconductor structure and a preparation method thereof, a detection substrate and a preparation method thereof, and a detection device, so that the signal conversion and optical detection functions are realized, the manufacturing process is simplified, and the cost is reduced.

According to an aspect of the present invention, there is provided a semiconductor structure including a substrate, and a semiconductor layer and a gate layer located on one side of the substrate, the gate layer being insulated from the semiconductor layer;

The semiconductor layer comprises an N-type doped region, an N-type semiconductor region and a P-type doped region, and the N-type semiconductor region is positioned between the N-type doped region and the P-type doped region;

The ion doping concentration of the N-type doped region is greater than that of the N-type semiconductor region;

the ion doping concentration of the P-type doping region is greater than that of the N-type semiconductor region;

And the grid electrode layer covers the N-type semiconductor region along the thickness direction of the substrate base plate.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor structure, including:

preparing an N-type semiconductor material layer on one side of a substrate;

patterning the N-type semiconductor material layer to form a semiconductor layer, wherein the semiconductor layer comprises an N-type semiconductor region;

Carrying out a heavy doping ion implantation process on the semiconductor layer to form a P-type doped region and an N-type doped region, wherein the N-type semiconductor region is positioned between the N-type doped region and the P-type doped region;

before preparing the N-type semiconductor material layer on one side of the substrate, the method further comprises:

preparing a grid layer on one side of the substrate;

Preparing a gate insulating layer on one side of the gate layer away from the substrate base plate;

wherein, along the thickness direction of the semiconductor layer, the gate layer covers the N-type semiconductor region;

Or alternatively

After forming the semiconductor layer, further comprising:

Preparing a gate insulating layer on one side of the semiconductor layer away from the substrate base plate;

And preparing a gate layer on one side of the gate insulating layer, which is away from the substrate, and covering the N-type semiconductor region along the thickness direction of the semiconductor layer.

According to another aspect of the present invention, there is provided a detection substrate including a detection unit;

The detection unit comprises the semiconductor structure of the first aspect.

According to another aspect of the present invention, there is provided a detection device comprising the detection substrate described in the above aspect.

According to another aspect of the present invention, there is provided a method of manufacturing a detection substrate including a semiconductor structure and a transistor including a P-type transistor, the method comprising:

preparing an N-type semiconductor material layer on one side of a substrate;

Patterning the N-type semiconductor material layer to form an active layer of the P-type transistor and a semiconductor layer of the semiconductor structure, wherein the semiconductor layer comprises an N-type semiconductor region;

Performing an N-type heavy doping ion implantation process on the semiconductor layer to form an N-type doped region on the semiconductor layer;

Preparing a gate insulating layer on one side of the active layer and the semiconductor layer of the P-type transistor, which is away from the substrate base plate;

Preparing a gate material layer on one side of the gate insulating layer, which is away from the substrate, and patterning the gate material layer to form a gate layer of the P-type transistor and a gate layer of the semiconductor structure, wherein the gate layer of the semiconductor structure covers the N-type semiconductor region along the thickness direction of the semiconductor layer;

And carrying out a P-type heavy doping ion implantation process on the active layer of the P-type transistor and the semiconductor layer of the semiconductor structure to form a heavy doping region in the active layer of the P-type transistor, and forming a P-type doping region in the semiconductor layer, wherein the N-type semiconductor region is positioned between the N-type doping region and the P-type doping region.

The semiconductor structure comprises a semiconductor layer and a grid layer which are stacked, wherein the semiconductor layer comprises an N-type doped region, a P-type doped region and an N-type semiconductor region positioned between the N-type doped region and the P-type doped region, the ion doping concentration of the N-type doped region is greater than that of the N-type semiconductor region, and the ion doping concentration of the P-type doped region is greater than that of the N-type semiconductor region. The voltage change on the gate layer of the semiconductor structure can cause the on-current of the semiconductor structure to change exponentially, so that the semiconductor structure can be used as a signal sensor structure to be applied to a detection substrate in the fields of signal conversion and the like. Meanwhile, the semiconductor structure has photosensitive characteristics and unidirectional conductivity, can convert optical signals into electric signals, and can be further used as a signal sensor structure to be applied to detection substrates in the fields of optical detection and the like. Compared with the PIN type photodiode, the technical scheme provided by the embodiment of the invention has the advantages of less Mask (Mask) process, simple manufacturing process and reduced preparation cost.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a PIN photodiode in the related art;

Fig. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view of FIG. 2 taken along the direction A-A';

FIG. 4 is a schematic diagram of an Id-Vg curve of a semiconductor structure according to an embodiment of the present invention;

Fig. 5 is a schematic cross-sectional structure of a semiconductor structure according to an embodiment of the present invention;

Fig. 6 is a schematic structural diagram of another semiconductor structure according to an embodiment of the present invention;

FIG. 7 is a schematic cross-sectional view of FIG. 6 along the direction B-B';

Fig. 8 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

Fig. 9 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

fig. 10 is a schematic flow chart of another method for manufacturing a semiconductor structure according to an embodiment of the present invention;

FIG. 11 is a schematic flow chart of another method for fabricating a semiconductor structure according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of a detection substrate according to an embodiment of the present invention;

FIG. 13 is a schematic cross-sectional view of FIG. 12 along the direction C-C';

fig. 14 is a schematic circuit diagram of a detection unit according to an embodiment of the present invention;

FIG. 15 is a schematic cross-sectional view of a detection substrate according to an embodiment of the present invention;

FIG. 16 is a schematic cross-sectional view of another exemplary embodiment of a detection substrate;

fig. 17 is a schematic cross-sectional structure of a detection substrate in the related art;

FIG. 18 is a schematic cross-sectional view of a detecting device according to an embodiment of the present invention;

FIG. 19 is a schematic cross-sectional view of another detecting device according to an embodiment of the present invention;

FIG. 20 is a schematic flow chart of a method for manufacturing a detection substrate according to an embodiment of the present invention;

Fig. 21 is a schematic flow chart of a method for manufacturing a detection substrate according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural diagram of a PIN photodiode in the related art, as shown in fig. 1, the PIN photodiode 1 includes a P-type silicon layer (P-layer) 11, an intrinsic silicon layer (I-layer) 12 and an N-type silicon layer (N-layer) 13, which are stacked, and a plurality of Mask (Mask) process steps are required for preparation, so that the number of the process steps is large, and the preparation cost is high.

Meanwhile, in order to ensure photoelectric conversion efficiency, the intrinsic silicon layer (I layer) 12 in the PIN-type photodiode needs to have a larger thickness, which results in a larger overall thickness of the PIN-type photodiode, and is not beneficial to the thin design of the detection substrate when the PIN-type photodiode is applied to the detection substrate in the fields of signal conversion, optical detection and the like.

In addition, the PIN photodiodes are manufactured based on an a-si process, and due to the limitation of a process route, the intrinsic silicon layer (I layer) 12 cannot be modulated, if a plurality of PIN photodiodes are arranged on the same substrate in an array manner, the photoelectric conversion efficiency of each manufactured PIN photodiode is consistent and fixed, and flexible adjustment of the photoelectric conversion efficiency of each PIN photodiode according to different products or different area requirements cannot be realized.

Based on the above technical problems, fig. 2 is a schematic structural view of a semiconductor structure according to an embodiment of the present invention, fig. 3 is a schematic structural view of a cross-section along A-A' direction of fig. 2, and as shown in fig. 2 and 3, an embodiment of the present invention provides a semiconductor structure, which includes a substrate 20, and a semiconductor layer 21 and a gate layer 22 located on one side of the substrate 20, wherein the gate layer 22 is insulated from the semiconductor layer 22. The semiconductor layer 21 includes an N-type doped region 211, an N-type semiconductor region 212, and a P-type doped region 213, and the N-type semiconductor region 212 is located between the N-type doped region 211 and the P-type doped region 213. The ion doping concentration of the N-type doped region 211 is greater than the ion doping concentration of the N-type semiconductor region 212, and the ion doping concentration of the P-type doped region 213 is greater than the ion doping concentration of the N-type semiconductor region 212. The gate layer 22 covers the N-type semiconductor region 212 in the thickness direction of the base substrate 20.

Specifically, as shown in fig. 2 and 3, the substrate 20 is used to carry a semiconductor structure, and the semiconductor structure may be directly prepared on the substrate 20.

The substrate 20 may include a glass substrate, so that when the semiconductor structure is applied to a detection substrate in the fields of signal conversion, optical detection, etc., the manufacturing process of the detection substrate may be compatible, and the manufacturing efficiency of the detection substrate may be improved, but is not limited thereto.

A semiconductor layer 21 is provided on the substrate 20 side, and the semiconductor layer 21 is made of a semiconductor material.

The thickness of the semiconductor layer 21 may be smaller, for example, the thickness of the semiconductor layer 21 may be 10nm to 100nm, so that the thickness of the semiconductor structure is smaller, which is beneficial to realizing thin design.

Further, the semiconductor layer 21 includes an N-type doped region 211, a P-type doped region 213, and an N-type semiconductor region 212 between the N-type doped region 211 and the P-type doped region 213.

The N-type doped region 211 is an N-type heavily doped region (n+ region), N-type ions are doped in the N-type doped region 211, and the ion doping concentration of the N-type doped region 211 is greater than that of the N-type semiconductor region 212. The pattern of the semiconductor layer 21 may be N-type ion doped by a heavily doped ion implantation process to form the N-type doped region 211.

The P-type doped region 213 is a P-type heavily doped region (p+ region), P-type ions are doped in the P-type doped region 213, and the ion doping concentration of the P-type doped region 213 is greater than that of the N-type semiconductor region 212. The P-type doped region 213 may be formed by performing P-type ion doping on the pattern of the semiconductor layer 21 through a heavily doped ion implantation process.

The N-type semiconductor region 212 is an N-type lightly doped region (N-region), and N-type ions may be doped in the N-type semiconductor region 212, but the ion doping concentration of the N-type semiconductor region 212 needs to be smaller than that of the N-type doped region 211 and smaller than that of the P-type doped region 213.

The N-type semiconductor region 212 may be formed by performing N-type ion doping on the pattern of the semiconductor layer 21 through a lightly doped ion implantation process, but is not limited thereto.

Further, the semiconductor structure further includes a gate layer 22 insulated from the semiconductor layer 21, and a vertical projection of the gate layer 22 on the substrate 20 covers a vertical projection of the N-type semiconductor region 212 on the substrate 20.

Wherein the gate layer 22 may act as a gate modulation for the N-type semiconductor region 212.

Specifically, fig. 4 is a schematic diagram of an Id-Vg curve of a semiconductor structure according to an embodiment of the present invention, where Vg is a gate voltage of the semiconductor structure and Id is an on current of the semiconductor structure. As shown in fig. 2 to 4, when the voltage Vg applied to the gate layer 22 of the semiconductor structure is low, the N-type doped region 211 and the P-type doped region 213 are not conducted, or the N-type doped region 211 and the P-type doped region 213 are maintained at a low leakage current level; when the voltage Vg applied to the gate layer 22 of the semiconductor structure is high and a forward voltage (i.e., the potential of the P-type doped region 213 is higher than that of the N-type doped region 211) is applied to the semiconductor structure, the N-type doped region 211 and the P-type doped region 213 are turned on, and a unidirectional conduction is performed, and a conduction current flows from the P-type doped region 213 to the N-type doped region 211, and with the increase of Vg, the conduction current Id of the semiconductor structure increases exponentially, i.e., a smaller Vg change causes a larger Id change.

It should be noted that, the voltage Vg applied to the gate layer 22 of the semiconductor structure being at a low level means that the absolute value |vg| of Vg is smaller, or is close to 0; the voltage Vg applied to the gate layer 22 of the semiconductor structure being high means that the absolute value of Vg is large.

In addition, the semiconductor structure has photosensitive characteristics and unidirectional conductivity, and can convert an optical signal into an electrical signal. The semiconductor structure is subjected to illumination to generate leakage current, and the leakage current of the semiconductor structure is determined by the illumination intensity of the semiconductor structure, namely the semiconductor structure is subjected to different illumination intensities, so that the detection of the light intensity can be realized by detecting the leakage current information of the semiconductor structure.

Meanwhile, the ion doping concentration of the N-type semiconductor region 212 affects the photoelectric conversion efficiency of the semiconductor structure, so that when the semiconductor structure is applied to light intensity detection, the ion doping concentration of the N-type semiconductor region 212 can be adjusted to change the photoelectric conversion efficiency of the semiconductor structure, and when a plurality of semiconductor structures are arranged on the same substrate in an array manner, the photoelectric conversion efficiency of each semiconductor structure can be flexibly adjusted according to different products or different region requirements.

In addition, since the gate layer 22 can play a role in gate modulation on the N-type semiconductor region 212, when the semiconductor structure is used for light intensity detection, different voltages can be applied to the gate layer 22 to adjust the carrier concentration in the N-type semiconductor region 212, and further adjust the photoelectric conversion efficiency of the semiconductor structure, so that the ion doping concentration error caused by the doping process error can be calibrated, and finally, the larger leakage current variation caused by smaller light intensity can be caused, and the response speed of light intensity detection is improved.

It should be noted that, the higher the ion doping concentration of the N-type doped region 211 and the P-type doped region 213, the larger the on-current of the semiconductor structure; the lower the ion doping concentration of the N-type semiconductor region 212, the more advantageous it is to improve the photoelectric conversion efficiency of the semiconductor structure.

In the embodiment of the present invention, the doping concentrations of the N-type doped region 211, the N-type semiconductor region 212 and the P-type doped region 213 may be set according to practical requirements, which is not particularly limited in the embodiment of the present invention.

In summary, the semiconductor structure provided in the embodiment of the invention includes a semiconductor layer and a gate layer, which are stacked, wherein the semiconductor layer includes an N-type doped region, a P-type doped region, and an N-type semiconductor region located between the N-type doped region and the P-type doped region, an ion doping concentration of the N-type doped region is greater than an ion doping concentration of the N-type semiconductor region, and an ion doping concentration of the P-type doped region is greater than an ion doping concentration of the N-type semiconductor region.

The voltage change on the gate layer of the semiconductor structure can cause the on-current of the semiconductor structure to change exponentially, so that the semiconductor structure can be used as a signal sensor structure to be applied to a detection substrate in the fields of signal conversion and the like.

Meanwhile, the semiconductor structure has photosensitive characteristics and unidirectional conductivity, can convert optical signals into electric signals, and can be further used as a signal sensor structure to be applied to detection substrates in the fields of optical detection and the like.

Therefore, the semiconductor structure provided by the embodiment of the invention can realize the photoelectric conversion function of the PIN type photodiode.

Further, the semiconductor structure provided by the embodiment of the invention only comprises a semiconductor layer and a grid layer, and compared with the PIN type photodiode, the Mask (Mask) process has fewer processes, so that the preparation cost is reduced.

Meanwhile, the semiconductor layer and the grid layer can be smaller in thickness, and compared with a PIN type photodiode, the semiconductor structure provided by the embodiment of the invention is smaller in thickness and more beneficial to realizing thin design.

In addition, the ion doping concentration of the N-type semiconductor region in the semiconductor layer can be adjusted to change the photoelectric conversion efficiency of the semiconductor structure, so that when a plurality of semiconductor structure arrays are arranged on the same substrate, the photoelectric conversion efficiency of each semiconductor structure can be flexibly adjusted according to different products or different region requirements.

In addition, the semiconductor structure provided by the embodiment of the invention can further adjust the photoelectric conversion efficiency of the semiconductor structure by applying different voltages to the gate layer, so that the ion doping concentration error caused by the doping process error can be calibrated, and finally, the larger leakage current change caused by smaller light intensity can be caused, and the response speed of light intensity detection is improved.

Alternatively, the material of the semiconductor layer 21 includes polysilicon.

The polysilicon is an N-type semiconductor material, so that the N-type semiconductor region 212 can be formed by setting the material of the semiconductor layer 21 to be polysilicon without performing an additional ion implantation process on the semiconductor layer 21, thereby reducing the process of the ion implantation process, shortening the preparation time and reducing the preparation cost.

In addition, when the semiconductor structure is applied to a detection substrate with a low temperature polysilicon (Low Temperature Poly-silicon, LTPS) thin film transistor (Thin Film Transistor, TFT), the semiconductor layer 21 and the active layer of the thin film transistor are made of polysilicon materials, and the thickness of the semiconductor layer 21 is the same as that of the active layer of the thin film transistor, so that the semiconductor layer 21 and the active layer of the thin film transistor can be prepared in the same process, the preparation of the semiconductor structure can be realized without adjusting the existing LTPS process route, and therefore, the Mask (Mask) process can be reduced, and the process time can be shortened; meanwhile, the semiconductor layer 21 and the active layer of the thin film transistor are positioned on the same film layer, so that the arrangement of one film layer can be reduced, and the purposes of reducing the production cost and the thickness of the substrate are achieved.

Optionally, the doping ions of the N-type doping region 211 include one of phosphorus ions, nitrogen ions, and arsenic ions, and the doping ions of the P-type doping region 213 include one of boron ions, indium ions, and aluminum ions.

The N-type doped region 211 may be formed on the semiconductor layer 21 by doping a partial region of the semiconductor layer 21 with phosphorus ions, nitrogen ions, or arsenic ions. For example, when the semiconductor layer 21 is made of a polysilicon material, the N-type doped region 211 of the semiconductor layer 21 is doped with phosphorus ions, nitrogen ions, or arsenic ions, so that the intrinsic polysilicon of the N-type doped region 211 becomes N-type polysilicon.

Meanwhile, the P-type doped region 213 may be formed on the semiconductor layer 21 by doping a partial region of the semiconductor layer 21 with boron ions, indium ions, and aluminum ions. For example, when the semiconductor layer 21 is made of a polysilicon material, the P-type doped region 213 of the semiconductor layer 21 is doped with boron ions, indium ions, and aluminum ions, so that the intrinsic polysilicon of the P-type doped region 213 becomes P-type polysilicon.

Optionally, the doping ions of the N-type doped region 211 are phosphorus ions, and the doping ions of the P-type doped region 213 are boron ions, so that the manufacturing process of the semiconductor structure can be compatible with the manufacturing process of the thin film transistor when the semiconductor structure is applied to the detection substrate with a Low Temperature Polysilicon (LTPS) thin film transistor (Thin Film Transistor, TFT). Specifically, doping of the semiconductor layer 21 can be simultaneously achieved while doping the active layer of the thin film transistor by the ion implantation process, i.e., doping of the semiconductor layer 21 and the active layer of the thin film transistor can be achieved in the same ion implantation process.

With continued reference to fig. 2, optionally, the length of the N-type semiconductor region 212 is less than or equal to the length of the N-type doped region 211, and the length of the N-type semiconductor region 212 is less than or equal to the length of the P-type doped region 213 along the direction in which the N-type doped region 211 points to the P-type doped region 213.

Specifically, as shown in fig. 2, along the direction in which the N-type doped region 211 points to the P-type doped region 213, the length of the N-type semiconductor region 212 is L1, the length of the N-type doped region 211 is L2, and the length of the P-type doped region 213 is L3, wherein L1 is L2 and L1 is L3.

The smaller the length of the N-type semiconductor region 212 is, the larger the on-current value of the semiconductor structure when the semiconductor structure is turned on is along the direction that the N-type doped region 211 points to the P-type doped region 213.

In this embodiment, the N-type doped region 211 points to the P-type doped region 213, and the length of the N-type semiconductor region 212 is smaller, which is beneficial to improving the on-current value of the semiconductor structure during on, so as to improve the signal conversion and the optical detection sensitivity of the semiconductor structure.

With continued reference to FIG. 2, the N-type semiconductor region 212 may optionally have a length L1 along the direction in which the N-type doped region 211 points toward the P-type doped region 213, wherein 3 μm L1 is less than or equal to 5 μm.

As described above, the smaller the length of the N-type semiconductor region 212 is, the larger the on-current value of the semiconductor structure when turned on is, along the direction in which the N-type doped region 211 points to the P-type doped region 213.

In this embodiment, by setting the length L1 of the N-type semiconductor region 212 to be 3 μm or less and L1 or less and 5 μm or less, the length L1 of the N-type semiconductor region 212 is made small under the condition of process permission, so that the on-current value of the semiconductor structure during on is improved, the process difficulty is low, and the implementation is easy, thereby being beneficial to reducing the cost.

With continued reference to fig. 2 and 3, optionally, the semiconductor structure provided by the embodiment of the present invention further includes a gate insulating layer 23, where the gate insulating layer 23 is located between the semiconductor layer 21 and the gate layer 22, and the gate insulating layer 23 includes at least one of a silicon nitride layer and a silicon oxide layer.

The gate insulating layer 23 is used to insulate the semiconductor layer 21 from the gate layer 22, so as to ensure insulation between the semiconductor layer 21 and the gate layer 22.

Alternatively, the gate insulating layer 23 is a silicon nitride layer having a large dielectric constant, so that good electrical insulation between the semiconductor layer 21 and the gate layer 22 can be ensured.

Optionally, the gate insulating layer 23 is a silicon oxide layer, where the silicon oxide layer has a strong adhesion with the semiconductor layer 21, so that the adhesion between the semiconductor layer 21 and the silicon oxide layer can be improved, and the film peeling can be avoided.

Fig. 5 is a schematic cross-sectional structure of a semiconductor structure according to an embodiment of the present invention, as shown in fig. 5, optionally, the gate insulating layer 23 includes a first gate insulating layer 231 and a second gate insulating layer 232 stacked together, where the first gate insulating layer 231 is located on a side of the second gate insulating layer 232 near the semiconductor layer 21, and the first gate insulating layer 231 is a silicon oxide layer, and the second gate insulating layer 232 is a silicon nitride layer.

With continued reference to fig. 2 and 3, optionally, a gate layer 22 is located on a side of the semiconductor layer 21 facing away from the substrate 20.

When the semiconductor structure is applied to a detection substrate in the fields of signal conversion and the like, the gate layer 22 can shield external light, so that the external light is prevented from irradiating the semiconductor layer 21, the photo-generated current of the semiconductor layer 21 is reduced, and the stability of the semiconductor structure is prevented from being greatly influenced by illumination. Therefore, the gate layer 22 is disposed on the side of the semiconductor layer 21 away from the substrate 20, i.e. the semiconductor structure adopts a top gate structure, which is beneficial to the application of the semiconductor structure in the detection substrate in the fields of signal conversion and the like.

Fig. 6 is a schematic structural diagram of another semiconductor structure according to an embodiment of the present invention, and fig. 7 is a schematic structural diagram of a cross-section of fig. 6 along a direction B-B', where, as shown in fig. 6 and fig. 7, the gate layer 22 is located on a side of the semiconductor layer 21 near the substrate 20.

When the semiconductor structure is applied to a detection substrate in the fields of light intensity detection and the like, the shielding of the light beam to be detected by the gate layer 22 can be avoided, the light beam to be detected can be ensured to irradiate onto the semiconductor layer 21, and therefore the accuracy of light intensity detection is ensured. Therefore, the present embodiment is advantageous in that the semiconductor structure is suitable for use in a detection substrate in the field of light intensity detection and the like by disposing the gate layer 22 on the side of the semiconductor layer 21 close to the substrate 20.

Based on the same inventive concept, the embodiments of the present invention further provide a method for manufacturing a semiconductor structure, which is used for manufacturing any semiconductor structure provided in the foregoing embodiments, and explanations of structures and terms that are the same as or corresponding to those of the foregoing embodiments are not repeated herein.

FIG. 8 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present invention,

FIG. 9 is a schematic flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present invention,

Fig. 10 is a schematic flow chart of another method for manufacturing a semiconductor structure according to an embodiment of the present invention, and fig. 11 is a schematic flow chart of another method for manufacturing a semiconductor structure according to an embodiment of the present invention, as shown in fig. 8 to 11, where the method for manufacturing a semiconductor structure includes:

S11, an N-type semiconductor material layer 210 is prepared on the side of the substrate 20.

In particular, as shown in fig. 8-11, the substrate 20 is used to carry a semiconductor structure, which may be directly fabricated on the substrate 20.

Further, an N-type semiconductor material layer 210 is prepared on the side of the substrate base 20.

The material of the N-type semiconductor material layer 210 may be polysilicon, so that the N-type semiconductor material layer 210 is formed by using a low-temperature polysilicon process, so that the manufacturing process of the semiconductor structure may be compatible with the manufacturing process of the thin film transistor.

Specifically, a layer of amorphous silicon (a-Si) is prepared on one side of the substrate base 20, and then the amorphous silicon (a-Si) is crystallized (polycrystallized) by an Excimer laser annealing (specifier LASER ANNEALING, ELA) process to form a polysilicon layer, i.e., an N-type semiconductor material layer 210.

S12, patterning the N-type semiconductor material layer 210 to form a semiconductor layer 21, where the semiconductor layer 21 includes an N-type semiconductor region 212.

Specifically, after the N-type semiconductor material layer 210 is formed, the N-type semiconductor material layer 210 may be patterned by exposing, developing, etching, and the like to form the semiconductor layer 21.

Because the N-type semiconductor material layer 210 is made of an N-type semiconductor material, the N-type semiconductor region 212 can be formed without performing an additional ion implantation process on the semiconductor layer 21, so that the process of the ion implantation process can be reduced, the preparation time can be shortened, and the preparation cost can be reduced.

The thickness of the semiconductor layer 21 may be 10nm to 100nm, which is advantageous for making the thickness of the semiconductor structure small and for realizing a thin design.

S13, performing a heavy doping ion implantation process on the semiconductor layer 21 to form a P-type doped region 213 and an N-type doped region 211, wherein the N-type semiconductor region 212 is located between the N-type doped region 211 and the P-type doped region 213.

Specifically, the N-type doped region 211 may be formed by performing N-type ion doping on a partial region of the semiconductor layer 21 through a heavily doped ion implantation process. The P-type doped region 213 may be formed by performing P-type ion doping on a partial region of the semiconductor layer 21 through a heavily doped ion implantation process. The N-type doped region 211 and the P-type doped region 213 are located at two sides of the N-type semiconductor region 212, respectively.

It should be noted that the order of forming the N-type doped region 211 and the P-type doped region 213 by the heavily doped ion implantation process may be set according to practical requirements.

For example, the N-type ion doping may be performed on the partial region of the semiconductor layer 21 by the heavily doped ion implantation process to form the N-type doped region 211, and then the P-type ion doping may be performed on the partial region of the semiconductor layer 21 by the heavily doped ion implantation process to form the P-type doped region 213; or the P-type ion doping is performed on the partial region of the semiconductor layer 21 by the heavily doped ion implantation process to form the P-type doped region 213, and then the N-type ion doping is performed on the partial region of the semiconductor layer 21 by the heavily doped ion implantation process to form the N-type doped region 211, which is not particularly limited in the embodiment of the present invention.

The doping ions of the N-type doping region 211 may include one of phosphorus ions, nitrogen ions, and arsenic ions, and the doping ions of the P-type doping region 213 may include one of boron ions, indium ions, and aluminum ions, but are not limited thereto.

With continued reference to fig. 10 and 11, optionally, before preparing the N-type semiconductor material layer 210 on one side of the substrate 20, further includes:

S101, preparing the gate layer 22 on the substrate 20 side.

S102, preparing a gate insulating layer 23 on a side of the gate layer 22 facing away from the substrate 20.

Specifically, when the semiconductor structure is applied to a detection substrate in the fields of light intensity detection and the like, the semiconductor structure with the bottom gate structure formed based on the preparation process can avoid the shielding of the light beam to be detected by the gate layer 22, and ensure that the light beam to be detected can irradiate onto the semiconductor layer 21, thereby ensuring the accuracy of light intensity detection.

The gate layer 22 covers the N-type semiconductor region 212 along the thickness direction of the semiconductor layer 21, so that the gate layer 22 can perform bottom gate modulation on the N-type semiconductor region 212.

With continued reference to fig. 11, the gate insulating layer 23 may alternatively include a first gate insulating layer (not shown) and a second gate insulating layer (not shown) that are stacked, the first gate insulating layer being located on a side of the second gate insulating layer adjacent to the semiconductor layer 21.

Specifically, when the gate insulating layer 23 is prepared on the side of the gate layer 22 facing away from the substrate 20, a second gate insulating layer may be prepared on the side of the gate layer 22 facing away from the substrate 20, then a first gate insulating layer may be prepared on the side of the second gate insulating layer facing away from the gate layer 22, and then the N-type semiconductor material layer 210 may be prepared on the side of the first gate insulating layer facing away from the second gate insulating layer.

The first gate insulating layer may be a silicon oxide layer, and the second gate insulating layer may be a silicon nitride layer, so that the adhesion between the semiconductor layer 21 and the gate insulating layer 23 is improved while good electrical insulation between the semiconductor layer 21 and the gate layer 22 is ensured, and the film peeling is avoided, but the present invention is not limited thereto.

With continued reference to fig. 8 and 9, optionally, after forming the semiconductor layer 21, further includes:

S141, preparing a gate insulating layer 23 on a side of the semiconductor layer 21 facing away from the substrate 20.

S142, a gate layer 22 is prepared on a side of the gate insulating layer 23 facing away from the substrate 20, and the gate layer 22 covers the N-type semiconductor region 212 along the thickness direction of the semiconductor layer 21.

Specifically, when the semiconductor structure is applied to a detection substrate in the fields of signal conversion and the like, the gate layer 22 can play a role in shielding external light, so that the external light is prevented from irradiating the semiconductor layer 21, the photo-generated current of the semiconductor layer 21 is reduced, and the stability of the semiconductor structure is prevented from being greatly influenced by the light.

The gate layer 22 covers the N-type semiconductor region 212 along the thickness direction of the semiconductor layer 21, so that the gate layer 22 can perform a top gate modulation function on the N-type semiconductor region 212.

With continued reference to fig. 9, the gate insulating layer 23 may alternatively include a first gate insulating layer (not shown) and a second gate insulating layer (not shown) that are stacked, the first gate insulating layer being located on a side of the second gate insulating layer adjacent to the semiconductor layer 21.

Specifically, when the gate insulating layer 23 is prepared on the side of the semiconductor layer 21 facing away from the substrate 20, a first gate insulating layer may be prepared on the side of the semiconductor layer 21 facing away from the substrate 20, then a second gate insulating layer may be prepared on the side of the first gate insulating layer facing away from the semiconductor layer 21, and then the gate layer 22 may be prepared on the side of the second gate insulating layer facing away from the first gate insulating layer.

With continued reference to fig. 8 and 9, optionally, before the N-type semiconductor material layer 210 is formed on the side of the substrate 20, a buffer layer (not shown) may be formed on the side of the substrate 20, and then the N-type semiconductor material layer 210 may be formed on the side of the buffer layer facing away from the substrate 20.

Wherein the buffer layer is located between the substrate 20 and the N-type semiconductor material layer 210, and is used to prevent impurities in the substrate 20 from penetrating into the N-type semiconductor material layer 210, thereby protecting the N-type semiconductor material layer 210 from impurities in the substrate 20.

Optionally, the buffer layer includes a silicon oxide layer and a silicon nitride layer that are stacked, and the silicon oxide layer is located on a side of the silicon nitride layer near the N-type semiconductor material layer 210.

Specifically, a silicon nitride layer is first prepared on a side of the substrate 20, then a silicon oxide layer is prepared on a side of the silicon nitride layer facing away from the substrate 20, and then an N-type semiconductor material layer 210 is prepared on a side of the silicon oxide layer facing away from the silicon nitride layer.

The silicon nitride layer may serve as a good barrier to prevent impurities in the substrate 20 from penetrating into the N-type semiconductor material layer 210. The silicon oxide layer and the semiconductor layer 21 have stronger adhesion, so that the adhesion performance between the semiconductor layer 21 and the buffer layer can be improved, and the film layer is prevented from peeling.

It should be noted that the order of forming the N-type doped region 211/P-type doped region 213 on the semiconductor layer 21 by the heavily doped ion implantation process and preparing the gate layer 22 is not limited to the above embodiment.

In some embodiments, the step of preparing the gate layer 22 may be located before forming the N-type doped region 211 and/or forming the P-type doped region 213, and at this time, the gate layer 22 may be used as a blocking mask to perform a heavily doped ion implantation process on the semiconductor layer 21, so as to form the N-type doped region 211 or the P-type doped region 213, so that the formed N-type doped region 211 or the P-type doped region 213 and the gate layer 22 may be automatically aligned, while ensuring alignment accuracy, which is helpful for reducing process difficulty, but is not limited thereto.

In summary, the method for manufacturing a semiconductor structure according to any embodiment of the present invention may implement the manufacturing of a semiconductor structure according to any embodiment of the present invention, where the manufactured semiconductor structure has the technical effects of the technical solution in any embodiment described above, and will not be described herein.

Based on the same inventive concept, the embodiment of the present invention further provides a detection substrate, and fig. 12 is a schematic structural diagram of the detection substrate provided by the embodiment of the present invention, as shown in fig. 12, where the detection substrate includes a detection unit 30, and the detection unit 30 includes the semiconductor structure described in any embodiment of the present invention, so that the detection substrate provided by the embodiment of the present invention has the technical effects of the technical solution in any embodiment, and the same or corresponding structure and explanation of terms as those of the embodiment are not repeated herein.

The detection substrate provided in the embodiment of the present invention may be a detection substrate in the fields of signal conversion, optical detection, etc., and the detection unit 30 may implement a signal conversion or optical detection function through a semiconductor structure, which is not limited in particular in the embodiment of the present invention.

Fig. 13 is a schematic diagram of a cross-sectional structure along a direction C-C' of fig. 12, and fig. 14 is a schematic diagram of a circuit structure of a detection unit according to an embodiment of the present invention, as shown in fig. 12-14, optionally, the detection unit 30 further includes a first capacitor 31, the first capacitor 31 is located on a side of the semiconductor layer 21 of the semiconductor structure 32 facing away from the substrate 20, a first electrode plate 311 of the first capacitor 31 is electrically connected to the gate layer 22 of the semiconductor structure 32, and a second electrode plate 312 of the first capacitor 31 is located on a side of the first electrode plate 311 of the first capacitor 31 facing away from the substrate 20.

Specifically, the first capacitor 31 may be disposed on a side of the gate layer 22 of the semiconductor structure 32 facing away from the substrate 20, and the first electrode plate 311 and the second electrode plate 312 of the first capacitor 31 at least partially overlap along the thickness direction of the substrate 20.

The first capacitor 31 and the first electrode plate 311 can realize a droplet detection function.

Specifically, as shown in fig. 12-14, the detection substrate includes a plurality of detection units 30 arranged in an array, when the droplet 40 receives the driving force to reach a position of one detection unit 30, the droplet 40 is coupled with the second plate 312 of the first capacitor 31 in the detection unit 30 to form a new capacitor, the coupling voltage is the voltage Vg on the gate layer 22 of the semiconductor structure 32, and according to the principle of the semiconductor structure described in the foregoing embodiment, the voltage Vg on the gate layer 22 of the semiconductor structure 32 changes slightly, which causes the larger on-current Id of the semiconductor structure 32 to change. Therefore, the presence or absence of the droplet 40 in any of the detection units 30 causes the semiconductor structure 32 to output different current signals, and the presence or absence of the droplet 40 at the position of the detection unit 30 can be determined by the current signals output from the semiconductor structure 32. Based on the above principle, the positions of the droplets may be detected by the detection units 30 arranged in an array, so as to count the number of times the droplets 40 are moved, and the positions of the droplets 40 in any period of time, and the like, but is not limited thereto.

It should be noted that, the first capacitor 31 is disposed on a side of the semiconductor layer 21 of the semiconductor structure 32 facing away from the substrate 20, and the second electrode plate 312 of the first capacitor 31 is disposed on a side of the first electrode plate 311 of the first capacitor 31 facing away from the substrate 20, so that the first capacitor 31 and the second electrode plate 312 of the first capacitor 31 are closer to the film layer where the droplet 40 flows, thereby being beneficial to improving the sensitivity of droplet detection.

With continued reference to fig. 12-14, the detection unit 30 may optionally further include a first electrode 321 and a second electrode 322, where the first electrode 321 is electrically connected to the N-doped region 211 of the semiconductor structure 32 and the second electrode 322 is electrically connected to the P-doped region 213 of the semiconductor structure 32. The first electrode 321 is configured to receive a first power signal Vdd to apply a forward voltage to the semiconductor structure 32, and the second electrode 322 is configured to output a current signal Vout.

Further, as shown in fig. 13, the first electrode 321, the second electrode 322 and the first electrode plate 311 of the first capacitor 31 may be located in the same film layer, so as to reduce the arrangement of the metal layer, thereby achieving the purposes of reducing the production cost and reducing the thickness of the substrate. Meanwhile, the first electrode 321, the second electrode 322 and the first electrode plate 311 of the first capacitor 31 may be made of the same material, so that the first electrode 321, the second electrode 322 and the first electrode plate 311 of the first capacitor 31 may be manufactured in the same process, thereby shortening the process time.

The materials of the first electrode 321, the second electrode 322, and the first electrode plate 311 of the first capacitor 31 may be metal, but are not limited thereto.

With continued reference to fig. 13, optionally, the gate layer 22 of the semiconductor structure 32 is located on a side of the semiconductor layer 21 facing away from the substrate 20.

Specifically, as shown in fig. 13, by disposing the gate layer 22 on the side of the semiconductor layer 21 away from the substrate 20, that is, the semiconductor structure 32 adopts a top gate structure, the gate layer 22 can shield external light, so as to prevent the external light from irradiating the semiconductor layer 21 to generate photo-generated current, thereby preventing the stability of the semiconductor structure from being greatly affected by light.

Meanwhile, the gate layer 22 is disposed on the side of the semiconductor layer 21 away from the substrate 20, so as to facilitate the connection between the first electrode plate 311 of the first capacitor 31 and the gate layer 22.

Fig. 15 is a schematic cross-sectional structure of a test substrate according to an embodiment of the present invention, and as shown in fig. 15, optionally, the gate layer 22 of the semiconductor structure 32 is located on a side of the semiconductor layer 21 near the substrate 20.

Specifically, as shown in fig. 15, by disposing the gate layer 22 of the semiconductor structure 32 on the side of the semiconductor layer 21 close to the substrate 20, that is, the semiconductor structure 32 adopts a bottom gate structure, when the semiconductor structure is applied to a detection substrate in the field of light intensity detection, the gate layer 22 can be prevented from shielding a light beam to be detected, so that the light beam to be detected can be ensured to irradiate the semiconductor layer 21, and the accuracy of light intensity detection is ensured.

With continued reference to fig. 15, taking the fluorescent detection of semiconductor structure 32 for use in biochemical experiments as an example, after the completion of the reaction of the biological reagents (reaction substrate and reactant) on the detection substrate, a corresponding tracer may be added to the reaction product layer 50, and a fluorescence signal 51 may be excited by a laser, wherein the components of the reaction product layer 50 may be analyzed by the intensity of the generated fluorescence signal, and thus the presence or absence (positive) of the reaction of the biological reagents (reaction substrate and reactant) may be determined.

According to the principle of the semiconductor structure described in the above embodiment, when the fluorescent signal 51 irradiates the semiconductor structure 32, the semiconductor structure 32 generates a leakage current, and the magnitude of the leakage current of the semiconductor structure 32 is determined by the intensity of the fluorescent signal 51 received by the semiconductor structure 32, so that the semiconductor structure 32 in this embodiment generates and outputs a current signal corresponding to the intensity of the fluorescent signal 51 after receiving the fluorescent signal 51, and the current signal output by the semiconductor structure 32 can count the intensity information of the fluorescent light, thereby realizing the intensity detection of the fluorescent signal.

Fig. 16 is a schematic cross-sectional structure of another detection substrate provided in an embodiment of the present invention, as shown in fig. 12-16, optionally, the detection unit 30 further includes a transistor 60 and a driving electrode 61, where the driving electrode 61 is located on a side of the transistor 60 facing away from the substrate 20, and a source-drain electrode layer 601 of the transistor 60 is electrically connected to the driving electrode 61.

Specifically, as shown in fig. 12 to fig. 16, the detection substrate provided by the embodiment of the present invention may be a microfluidic substrate, where the microfluidic substrate may be used to control the flow position of the micro droplet by setting the electric field intensity of different areas on the microfluidic substrate by adopting the electrowetting principle, so as to realize the driving of the micro droplet.

As shown in fig. 12 to 16, the detection substrate provided in this embodiment includes a plurality of detection units 30 arranged in an array, where the detection units 30 include at least a transistor 60 and a driving electrode 61 that are electrically connected, and the driving electrode 61 is used to provide a voltage/electric field for driving the droplet 40 to travel.

The transistor 60 includes an active layer 602, a gate layer 603, and a source-drain electrode layer 601, which are stacked. The source-drain electrode layer 601 of the transistor 60 and the driving electrode 61 are electrically connected so that the transistor 60 can be connected in series between the driving electrode 61 and the data line on the detection substrate, the transistor 60 functioning as a switching element for supplying a voltage signal to the driving electrode 61, and the data line applying the data voltage signal to the driving electrode 61 when the transistor 60 is turned on to supply a voltage/electric field for driving the droplet 40 to travel. By applying different data voltage signals to the respective detection units 30, the droplet 40 can be caused to reach a desired position by the driving force.

Further, as shown in fig. 13, the semiconductor structure 32 in the detection unit 30 may feed back the position of the droplet 40 in real time during the movement of the droplet 40 so as to precisely control the travel path of the droplet 40. The principle of detecting the position of the droplet 40 of the semiconductor structure 32 can refer to the above embodiment, and will not be described herein.

In other embodiments, as shown in fig. 16, semiconductor structures 32 in detection unit 30 may be used to optically detect droplets 40 to analyze fluorescence intensity and the corresponding composition of droplets 40. The optical detection principle of the semiconductor structure 32 can refer to the above embodiments, and will not be described herein.

Fig. 17 is a schematic cross-sectional structure of a related art detection substrate, as shown in fig. 17, the detection substrate includes a PIN-type photodiode 1, a transistor 60 and a driving electrode 61, the PIN-type photodiode 1 includes a P-type silicon layer (P-layer) 11, an intrinsic silicon layer (I-layer) 12 and an N-type silicon layer (N-layer) 13 which are stacked, wherein the PIN-type photodiode 1 is manufactured based on a silicon-based manufacturing process, and the transistor 60 is generally manufactured by an LTPS process, and the PIN-type photodiode 1 and the transistor 60 need to be manufactured separately due to a process route limitation, so that a plurality of Mask (Mask) process processes are required for manufacturing, the number of processes is large, and the manufacturing cost is high.

Based on the above technical problem, with continued reference to fig. 13 and 16, alternatively, the active layer 602 of the transistor 60 and the semiconductor layer 21 of the semiconductor structure 32 are located in the same film.

Wherein, by disposing the active layer 602 of the transistor 60 and the semiconductor layer 21 of the semiconductor structure 32 on the same film, the number of the film layers can be reduced, thereby achieving the purpose of reducing the thickness of the substrate. Meanwhile, the active layer 602 of the transistor 60 and the semiconductor layer 21 of the semiconductor structure 32 may be made of the same material, so that the active layer 602 of the transistor 60 and the semiconductor layer 21 of the semiconductor structure 32 may be prepared in the same process, thereby shortening the process time and reducing the production cost.

Alternatively, as shown in fig. 13 and 16, the transistor 60 may include a P-type transistor and/or an N-type transistor, where the active layer 602 in the transistor 60 includes a channel region 73 as two heavily doped regions 71 respectively located at two sides of the channel region 73, and the two heavily doped regions 71 respectively form a source region and a drain region of the transistor 60.

As shown in fig. 13 and 16, alternatively, the transistor 60 is a low temperature polysilicon (Low Temperature Poly-silicon, LTPS) thin film transistor (Thin Film Transistor, TFT), and the active layer 602 of the transistor 60 and the semiconductor layer 21 of the semiconductor structure 32 may be made of polysilicon materials, so that the preparation of the active layer 602 of the transistor 60 and the semiconductor layer 21 of the semiconductor structure 32 can be achieved in the same process without adjusting the existing LTPS process route.

With continued reference to fig. 13 and 16, taking the transistor 60 as the P-type transistor T0 as an example, in the process of preparing the P-type transistor T0, the P-type doping may be performed on the active layer 602 by a heavily doped ion implantation process to form the heavily doped region 71, in which the P-type ion doping may be performed on the semiconductor layer 21 simultaneously to form the P-type doped region 213, thereby reducing the number of processes of the ion implantation process, shortening the preparation time, and reducing the preparation cost.

In other embodiments, if transistor 60 comprises an N-type transistor, the active layer of the N-type transistor may be N-doped by a heavily doped ion implantation process to form a heavily doped region. In the heavily doped ion implantation process, N-type ion doping can be performed on the semiconductor layer 21 simultaneously to form the N-type doped region 211, so that the number of processes of the ion implantation process can be reduced, the preparation time can be shortened, and the preparation cost can be reduced.

With continued reference to fig. 13 and 16, optionally, a lightly doped region 72 may be disposed between the heavily doped region 71 and the channel region 73, and the lightly doped region 72 may serve the purpose of suppressing leakage current and hot carrier effects, but is not limited thereto.

With continued reference to fig. 13 and 16, optionally, the gate layer 603 of transistor 60 and the gate layer 22 of semiconductor structure 32 are located at the same film layer.

By providing the gate layer 603 of the transistor 60 and the gate layer 22 of the semiconductor structure 32 in the same layer, the number of layers can be reduced, thereby achieving the purpose of reducing the thickness of the substrate and reducing the production cost. Meanwhile, the gate layer 603 of the transistor 60 and the gate layer 22 of the semiconductor structure 32 may be made of the same material, so that the gate layer 603 of the transistor 60 and the gate layer 22 of the semiconductor structure 32 may be prepared in the same process, thereby shortening the process time.

In addition, the closer the distance between the gate layer 22 and the semiconductor layer 21 of the semiconductor structure 32, the greater the effect of the voltage on the gate layer 22 on the N-type semiconductor region 212, thereby making the gate modulation effect of the gate layer 22 on the N-type semiconductor region 212 stronger.

The gate layer 603 of the transistor 60 and the active layer 602 thereof are typically located in a metal film layer that is closer to each other, so that the gate layer 22 of the semiconductor structure 32 and the gate layer 603 of the transistor 60 are disposed in the same layer, so that the distance between the gate layer 22 of the semiconductor structure 32 and the semiconductor layer 21 thereof is smaller, and the gate layer 22 can perform a stronger top gate modulation function on the N-type semiconductor region 212.

The spacing between the gate layer 22 and the semiconductor layer 21 of the semiconductor structure 32 may be set according to practical requirements, which is not particularly limited in the embodiment of the present invention.

With continued reference to fig. 12 and 13, optionally, the detecting unit 30 further includes a first capacitor 31, where the first capacitor 31 is located on a side of the semiconductor layer 21 of the semiconductor structure 32 facing away from the substrate 20, and a first electrode plate 311 of the first capacitor 31 is electrically connected to the gate layer 22 of the semiconductor structure 32, and a second electrode plate 312 of the first capacitor 31 is located on a side of the first electrode plate 311 of the first capacitor 31 facing away from the substrate 20. The first electrode plate 311 of the first capacitor 31 and the source-drain electrode layer 601 of the transistor 60 are located in the same film layer, and the second electrode plate 312 of the first capacitor 31 and the driving electrode 61 are located in the same film layer.

The structure and function of the first capacitor 31 may refer to the above embodiment, and will not be described herein.

In this embodiment, the first electrode plate 311 of the first capacitor 31 and the source-drain electrode layer 601 of the transistor 60 are disposed on the same film layer, so that the number of metal layers can be reduced, thereby achieving the purposes of reducing the production cost and reducing the thickness of the substrate. Meanwhile, the first electrode plate 311 of the first capacitor 31 and the source-drain electrode layer 601 of the transistor 60 may be made of the same material, so that the first electrode plate 311 of the first capacitor 31 and the source-drain electrode layer 601 of the transistor 60 may be prepared in the same process, thereby shortening the process time.

Meanwhile, the second polar plate 312 of the first capacitor 31 and the driving electrode 61 are arranged on the same film layer, so that the number of the film layers is reduced, and the purposes of reducing the production cost and the thickness of the substrate are achieved. The driving electrode 61 and the second plate 312 of the first capacitor 31 may be made of the same material, so that the driving electrode 61 and the second plate 312 of the first capacitor 31 may be manufactured in the same process, thereby shortening the process time.

The material of the driving electrode 61 and the second plate 312 of the first capacitor 31 may include Indium Tin Oxide (ITO), but is not limited thereto.

In addition, the closer the distance between the first electrode plate 311 and the second electrode plate 312 of the first capacitor 31, the larger the capacitance value of the first capacitor 31, thereby contributing to a reduction in the occupied area of the first capacitor 31 under the condition that the first capacitor 31 satisfies the required capacitance value.

In this embodiment, the first electrode plate 311 and the second electrode plate 312 of the first capacitor 31 are respectively located in adjacent conductive film layers, so that the distance between the first electrode plate 311 and the second electrode plate 312 of the first capacitor 31 is smaller, and a larger capacitance value is realized with a smaller occupied area.

The distance between the first electrode 311 and the second electrode 312 of the first capacitor 31 may be set according to practical requirements, which is not limited in the embodiment of the present invention.

With continued reference to fig. 16, the detection unit 30 may optionally further include a light shielding layer 62, where the light shielding layer 62 is located on a side of the active layer 602 of the transistor 60 near the substrate 20. The light shielding layer 62 and the active layer 602 at least partially overlap in the thickness direction of the base substrate 20. The gate layer 22 and the light shielding layer 62 of the semiconductor structure 32 are located in the same film layer.

The light shielding layer 62 is used for shielding the channel region 73 of the active layer 602 to prevent external light from irradiating the active layer 602, so as to prevent the active layer 602 from being irradiated with light and affecting the off-state current of the transistor 60, and prevent the transistor 60 from being adversely affected by the light.

Further, as shown in fig. 16, the gate layer 22 and the light shielding layer 62 of the semiconductor structure 32 are disposed on the same layer, so that the number of layers can be reduced, thereby achieving the purpose of reducing the thickness of the substrate. Meanwhile, the gate layer 22 and the light shielding layer 62 of the semiconductor structure 32 may be made of the same metal material, so that the gate layer 22 and the light shielding layer 62 of the semiconductor structure 32 may be prepared in the same process, thereby shortening the process time and reducing the production cost.

With continued reference to fig. 12-14 and 16, the detecting unit 30 may further include a second capacitor 33, where the first plate 331 of the second capacitor 33 is electrically connected to the driving electrode 61, and the second plate 332 of the second capacitor 33 is electrically connected to the common voltage signal line Vcom.

The common voltage signal line Vcom is used for accessing a common voltage signal.

Specifically, as shown in fig. 13 and 16, the first electrode plate 331 and the second electrode plate 332 at least partially overlap in the thickness direction of the base substrate 20, forming the second capacitor 33.

After the driving electrode 61 is connected to the data voltage signal when the transistor 60 is turned on, the second capacitor 33 may be used to maintain an electric field for driving the droplet to travel so as to ensure the droplet traveling effect.

It should be noted that, in the present embodiment, the film layer where the first electrode plate 331 and the second electrode plate 332 of the second capacitor 33 are located is not limited, where the first electrode plate 331 and the second electrode plate 332 of the second capacitor 33 may be located at the same film layer as other metal layers in the detection substrate, so as to reduce the number of film layers, thereby achieving the purpose of reducing the thickness of the substrate. Meanwhile, the first electrode plate 331 and the second electrode plate 332 of the second capacitor 33 may be made of the same material as the metal layer disposed on the same layer, so that the first electrode plate 331 and the second electrode plate 332 of the second capacitor 33 may be manufactured in the same process with the metal layer disposed on the same layer, thereby shortening the process time and reducing the production cost, but not limited thereto.

Based on the same inventive concept, the embodiment of the present invention further provides a detection device, fig. 18 is a schematic cross-sectional structure of the detection device provided by the embodiment of the present invention, fig. 19 is a schematic cross-sectional structure of another detection device provided by the embodiment of the present invention, and as shown in fig. 18 and 19, the detection device includes a detection substrate 80 according to any embodiment of the present invention, so that the detection device provided by the embodiment of the present invention has the technical effects of any embodiment of the present invention, and the explanation of the same or corresponding structure and terms as those of the embodiment of the present invention is not repeated herein.

With continued reference to fig. 18 and 19, alternatively, the detection device provided in an embodiment of the present invention may be a microfluidic device, where the detection device further includes a counter substrate 81 disposed opposite to the detection substrate 80, and a droplet 40 located between the detection substrate 80 and the counter substrate 81.

Alternatively, the side of the opposite substrate 81 facing the detection substrate 80, and the side of the detection substrate 80 facing the opposite substrate 81 may further include a hydrophobic layer to realize a droplet control function of the detection device.

With continued reference to fig. 18 and 19, an exemplary side of the opposite substrate 81 facing the detection substrate 80 includes an electrode layer 811, where the electrode layer 811 may be connected to a fixed dc potential signal, such as a ground signal, and the electrode layer 811 may be disposed on the entire surface of the opposite substrate 81 facing the detection substrate 80, where a driving electric field for driving the droplet 40 to move is formed between the electrode layer 811 and the driving electrode 61 of each detection unit, and by providing different voltage signals on the driving electrodes 61 of different detection units, the electric field formed between the electrode layer 811 and the driving electrode 61 of the adjacent detection unit may be made different, and thus the droplet 40 may travel toward the position of the electric field, and thus the effect of driving the droplet 40 between the detection substrate 80 and the opposite substrate 81 of the detection device may be achieved.

With continued reference to fig. 18, when the hydrophobic layer film forming process in the microfluidic device is unstable or the interface is contaminated by dust particles, the movement of the droplet 40 is often not consistent, which may cause the droplet 40 to be trapped at a point, if the microfluidic device is driven for a long time and is not observed by a person, the microfluidic device needs to self-detect the droplet position, and determine when the movement of the droplet 40 is stopped, in this embodiment, the semiconductor structure 32 may be used for detecting the position of the driving droplet on the microfluidic device. The principle of detecting the droplet position of the semiconductor structure 32 can refer to the above embodiment, and will not be described herein.

With continued reference to fig. 19, the microfluidic device may also be used in biochemical analytical detection fields, such as quantitative fluorescent PCR (polymerase chain reaction ) detection fields, where optical detection of droplets is required to analyze the fluorescence intensity and the corresponding droplet composition.

For example, various biological reagents (reaction substrates and reactants) such as cells can move and react in a microfluidic device in the form of droplets, when the biological reagents (reaction substrates and reactants) complete the reaction, corresponding tracers can be added into the reaction products, and fluorescence signals are excited by laser, so that the components of the reaction products can be analyzed through the intensity of the generated fluorescence signals, and further, whether the biological reagents (reaction substrates and reactants) react (whether the reaction is positive or not) can be judged.

When the fluorescent signal irradiates the semiconductor structure 32, the semiconductor structure 32 generates a leakage current, and the magnitude of the leakage current of the semiconductor structure 32 is determined by the intensity of the fluorescent signal received by the semiconductor structure 32, so that the semiconductor structure 32 in this embodiment generates and outputs a current signal corresponding to the intensity of the fluorescent signal after receiving the fluorescent signal, and the current signal output by the semiconductor structure 32 can count the intensity information of the fluorescent signal, thereby realizing the intensity detection of the fluorescent signal.

It should be noted that, the detection device provided by the embodiment of the present invention has the beneficial effects of the detection substrate provided by the embodiment of the present invention, and specific description of the detection substrate by referring to the above embodiments may be referred to, and this embodiment is not repeated here.

Based on the same inventive concept, the embodiment of the present invention further provides a method for preparing a detection substrate, which is used for preparing any one of the detection substrates provided in the above embodiment, and the explanation of the same or corresponding structure and terms as those of the above embodiment is not repeated here.

With continued reference to fig. 13 and 16, the detection substrate includes a semiconductor structure 32 and a transistor 60, the transistor 60 including a P-type transistor T0. The specific structure of the detection substrate may refer to the above embodiments, and will not be described herein.

Fig. 20 is a flow chart of a preparation method of a detection substrate according to an embodiment of the present invention, and as shown in fig. 20, the preparation method provided by the embodiment of the present invention includes:

s21, preparing an N-type semiconductor material layer on one side of the substrate.

Specifically, fig. 21 is a schematic flow chart of a method for manufacturing a detection substrate according to an embodiment of the present invention, as shown in fig. 21, a substrate 20 is used to carry a semiconductor structure 32 and a transistor 60, and the semiconductor structure 32 and the transistor 60 may be directly manufactured on the substrate 20.

The substrate 20 may include a glass substrate, so that the manufacturing process of the semiconductor structure 32 and the transistor 60 may be compatible, and the manufacturing efficiency of the detection substrate may be improved, but is not limited thereto.

Further, the N-type semiconductor material layer 210 is prepared on the substrate 20 side, and the thickness of the N-type semiconductor material layer 210 may be 10nm to 100nm, which is beneficial to the realization of thin design, but is not limited thereto.

The material of the N-type semiconductor material layer 210 may be polysilicon, so that the N-type semiconductor material layer 210 is formed by using a low-temperature polysilicon process, so that the manufacturing process of the semiconductor structure 32 is compatible with the manufacturing process of the transistor 30.

Alternatively, a layer of amorphous silicon (a-Si) is prepared on one side of the substrate base 20, and then the amorphous silicon (a-Si) is crystallized (polycrystallized) by an Excimer laser annealing (specifier LASER ANNEALING, ELA) process to form a polysilicon layer, i.e., an N-type semiconductor material layer 210.

Alternatively, before the N-type semiconductor material layer 210 is formed on the side of the substrate 20, a buffer layer may be formed on the side of the substrate 20, and then the N-type semiconductor material layer 210 may be formed on the side of the buffer layer facing away from the substrate 20.

The silicon nitride layer may serve as a good barrier to prevent impurities in the substrate 20 from penetrating into the N-type semiconductor material layer 210. The silicon oxide layer and the N-type semiconductor material layer 210 have strong adhesion, so that the adhesion performance between the N-type semiconductor material layer 210 and the buffer layer can be improved, and the film layer is prevented from being stripped.

And S22, patterning the N-type semiconductor material layer to form an active layer of the P-type transistor and a semiconductor layer of the semiconductor structure, wherein the semiconductor layer comprises an N-type semiconductor region.

Specifically, as shown in fig. 21, after the N-type semiconductor material layer 210 is formed, the N-type semiconductor material layer 210 may be patterned by exposing, developing, etching, and the like, to form an active layer 602 of a P-type transistor and a semiconductor layer 21 of a semiconductor structure.

Wherein the active layer 602 and the semiconductor layer 21 are formed in the same process, which can shorten the preparation time and reduce the preparation cost.

It should be noted that, since the N-type semiconductor material layer 210 is made of an N-type semiconductor material, the N-type semiconductor region 212 of the semiconductor layer 21 can be formed without performing an additional ion implantation process on the semiconductor layer 21, so that the process of the ion implantation process can be reduced, the preparation time can be shortened, and the preparation cost can be reduced.

S23, performing an N-type heavy doping ion implantation process on the semiconductor layer to form an N-type doped region on the semiconductor layer.

Specifically, as shown in fig. 21, the N-type ion doping may be performed on a partial region of the semiconductor layer 21 by a heavily doped ion implantation process to form an N-type doped region 211 on the semiconductor layer 21, wherein the N-type ion doped doping ions may include, but are not limited to, phosphorus ions.

In the heavily doped ion implantation process, the N-type semiconductor region 212 is masked to prevent the N-type semiconductor region 212 from being implanted with N-type doped ions, so that the ion doping concentration of the N-type doped region 211 is greater than that of the N-type semiconductor region 212.

Optionally, before the N-type heavily doped ion implantation process is performed on the semiconductor layer, the method may further include:

a P-type lightly doped ion implantation process is performed on the active layer 602 of the P-type transistor to adjust the threshold voltage of the active layer 602.

The dopant ions in the P-type lightly doped ion implantation process may include, but are not limited to, boron ions.

S24, preparing a gate insulating layer on one side of the active layer and the semiconductor layer of the P-type transistor, which is away from the substrate.

Specifically, as shown in fig. 21, a gate insulating layer 23 is prepared on the side of the active layer 602 and the semiconductor layer 21 facing away from the substrate 20, and the gate insulating layer 23 is used for insulation.

The gate insulating layer 23 may include a first gate insulating layer (not shown) and a second gate insulating layer (not shown) stacked, where the first gate insulating layer is located on a side of the second gate insulating layer near the semiconductor layer 21.

Specifically, when the gate insulating layer 23 is prepared on the side of the semiconductor layer 21 facing away from the substrate 20, a first gate insulating layer may be prepared on the side of the semiconductor layer 21 facing away from the substrate 20, and then a second gate insulating layer may be prepared on the side of the first gate insulating layer facing away from the semiconductor layer 21.

The first gate insulating layer may be a silicon oxide layer, and the second gate insulating layer may be a silicon nitride layer, so that the adhesion performance between the semiconductor layer 21 and the gate insulating layer 23 can be improved while ensuring good electrical insulation of the gate insulating layer 23, and film peeling is avoided, but the invention is not limited thereto.

And S25, preparing a gate material layer on one side of the gate insulating layer, which is away from the substrate, and patterning the gate material layer to form a gate layer of the P-type transistor and a gate layer of the semiconductor structure, wherein the gate layer of the semiconductor structure covers the N-type semiconductor region along the thickness direction of the semiconductor layer.

Specifically, as shown in fig. 21, a gate material layer 220 is prepared on a side of the gate insulating layer 23 facing away from the substrate 2, and the gate material layer 220 may be patterned by exposing, developing, etching, and the like to form a gate layer 603 of a P-type transistor and a gate layer 22 of a semiconductor structure.

In this embodiment, the gate layer 603 of the P-type transistor and the gate layer 22 of the semiconductor structure are formed in the same process, so that the manufacturing time can be shortened and the manufacturing cost can be reduced.

S26, carrying out a P-type heavy doping ion implantation process on the active layer of the P-type transistor and the semiconductor layer of the semiconductor structure so as to form a heavy doping region on the active layer of the P-type transistor, and forming a P-type doping region on the semiconductor layer, wherein the N-type semiconductor region is positioned between the N-type doping region and the P-type doping region.

Specifically, as shown in fig. 21, a partial region of the active layer 602 and a partial region of the semiconductor layer 21 of the P-type transistor may be P-type ion doped by a heavily doped ion implantation process to form a heavily doped region 71 on the active layer 602, and a P-type doped region 213 on the semiconductor layer 21, thereby forming a P-type transistor T0 and a semiconductor structure 32.

The heavily doped region 71 on the active layer 602 and the P-type doped region 213 of the semiconductor layer 21 are formed in the same heavily doped ion implantation process, so that the preparation time can be shortened and the preparation cost can be reduced.

In the P-type heavily doped ion implantation process described above, as shown in fig. 21, the active layer 602 and the semiconductor layer 21 of the P-type transistor may be doped with P-type ions using the gate layer 603 of the transistor 60 and the gate layer 22 of the semiconductor structure 32 as a blocking mask, and at this time, the region covered by the gate layer 603 of the transistor 60 is not implanted with P-type ions, thereby forming the channel region 73 of the active layer 602 between the two heavily doped regions 71. The channel region 73 and the gate layer 603 may be formed to be aligned automatically, and similarly, the P-type doped region 213 and the gate layer 22 may be formed to be aligned automatically on at least one side, so that alignment accuracy is ensured.

Alternatively, the P-type ion doped dopant ions may include boron ions, but are not limited thereto.

It should be noted that the order of forming the N-type doped region 211 and the P-type doped region 213 by the heavily doped ion implantation process is not limited to the above embodiment, and the embodiment of the present invention is not limited thereto.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. The semiconductor structure is characterized by comprising a substrate, a semiconductor layer and a gate layer, wherein the semiconductor layer and the gate layer are positioned on one side of the substrate, and the gate layer and the semiconductor layer are insulated;

2. The semiconductor structure of claim 1, wherein,

The material of the semiconductor layer includes polysilicon.

3. The semiconductor structure of claim 1, wherein,

The doping ions of the N-type doping region comprise one of phosphorus ions, nitrogen ions and arsenic ions;

The doping ions of the P-type doping region comprise one of boron ions, indium ions and aluminum ions.

4. The semiconductor structure of claim 1, wherein,

And along the direction that the N-type doped region points to the P-type doped region, the length of the N-type semiconductor region is smaller than or equal to that of the N-type doped region, and the length of the N-type semiconductor region is smaller than or equal to that of the P-type doped region.

5. The semiconductor structure of claim 1, wherein,

And the length of the N-type semiconductor region is L1 along the direction that the N-type doped region points to the P-type doped region, wherein L1 is more than or equal to 3 mu m and less than or equal to 5 mu m.

6. The semiconductor structure of claim 1, wherein,

The semiconductor structure further includes a gate insulating layer between the semiconductor layer and the gate layer;

The gate insulating layer includes at least one of a silicon nitride layer and a silicon oxide layer.

7. The semiconductor structure of claim 1, wherein,

The gate layer is located on a side of the semiconductor layer facing away from the substrate base plate.

8. The semiconductor structure of claim 1, wherein,

The gate layer is positioned on one side of the semiconductor layer close to the substrate base plate.

9. A method of fabricating a semiconductor structure, comprising:

preparing an N-type semiconductor material layer on one side of a substrate;

preparing a grid layer on one side of the substrate;

Or alternatively

After forming the semiconductor layer, further comprising:

10. A detection substrate, characterized by comprising a detection unit;

the detection unit comprising the semiconductor structure of any one of claims 1-8.

11. The detecting substrate according to claim 10, wherein,

The detection unit further comprises a first capacitor;

the first capacitor is positioned on one side of the semiconductor layer of the semiconductor structure, which is away from the substrate base plate, and the first polar plate of the first capacitor is electrically connected with the gate layer of the semiconductor structure;

the second electrode plate of the first capacitor is positioned at one side of the first electrode plate of the first capacitor, which is away from the substrate.

12. The detecting substrate according to claim 10, wherein,

The gate layer of the semiconductor structure is positioned on one side of the semiconductor layer away from the substrate base plate.

13. The detecting substrate according to claim 10, wherein,

The gate layer of the semiconductor structure is positioned on one side of the semiconductor layer close to the substrate base plate.

14. The detection substrate according to any one of claims 10 to 13, wherein,

The detection unit further comprises a transistor and a driving electrode;

The driving electrode is positioned on one side of the transistor, which is away from the substrate, and the source electrode layer and the drain electrode layer of the transistor are electrically connected with the driving electrode.

15. The test substrate of claim 14, wherein,

The active layer of the transistor and the semiconductor layer of the semiconductor structure are located in the same film layer.

16. The test substrate of claim 14, wherein,

The gate layer of the transistor and the gate layer of the semiconductor structure are located in the same film layer.

17. The test substrate of claim 14, wherein,

The detection unit further comprises a first capacitor, the first capacitor is located on one side, away from the substrate, of the semiconductor structure, a first polar plate of the first capacitor is electrically connected with the grid layer of the semiconductor structure, and a second polar plate of the first capacitor is located on one side, away from the substrate, of the first polar plate of the first capacitor;

The first polar plate of the first capacitor and the source-drain electrode layer of the transistor are positioned on the same film layer;

the second polar plate of the first capacitor and the driving electrode are positioned on the same film layer.

18. The test substrate of claim 14, wherein,

The detection unit further comprises a shading layer, wherein the shading layer is positioned on one side, close to the substrate, of the active layer of the transistor;

the light shielding layer and the active layer at least partially overlap in a thickness direction of the substrate base plate;

The grid electrode layer and the shading layer of the semiconductor structure are positioned on the same film layer.

19. The test substrate of claim 14, wherein,

The detection unit further comprises a second capacitor, wherein a first polar plate of the second capacitor is electrically connected with the driving electrode, and a second polar plate of the second capacitor is electrically connected with the common voltage signal line.

20. A test device comprising a test substrate according to any one of claims 10 to 19.

21. A method of manufacturing a detection substrate, the detection substrate comprising a semiconductor structure and a transistor, the transistor comprising a P-type transistor, the method comprising:

preparing an N-type semiconductor material layer on one side of a substrate;