CN118039638A - Semiconductor device layout structure - Google Patents
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Abstract
The invention provides a semiconductor device layout structure, which comprises: the semiconductor device comprises a semiconductor substrate, a first P-type well region and two N-type well regions, wherein the first P-type well region is positioned in the semiconductor substrate, the first P-type well region comprises a first P-type sub-well region and two second P-type sub-well regions, the two second P-type sub-well regions are respectively connected with two ends of the first P-type sub-well region along the length direction of the first P-type sub-well region, and the widths of the two second P-type sub-well regions are larger than those of the first P-type sub-well region; the two N-type well regions are both positioned in the semiconductor substrate, are symmetrically arranged at two sides of the first P-type well region along the width direction of the first P-type well region, and each N-type well region, the first P-type sub-well region and the second P-type sub-well region are all provided with gaps. The invention improves the area ratio of the first P-type well region between the two N-type well regions, can reduce the mismatch coefficient of the semiconductor device and improves the mismatch phenomenon of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a layout structure of a semiconductor device.
Background
In a semiconductor device manufacturing process, design values may not be the same as final physical implementation values due to process uncertainties. The parameter value deviation of the semiconductor devices of the same size in the manufacturing process is called relative deviation, the degree of mismatching of the semiconductor devices can be reduced by the relative deviation through reasonable circuit design and layout, and the general mismatching refers to the relative deviation among the semiconductor devices of the same size, so that the electrical parameter mismatching of the semiconductor devices, namely the matching performance is reduced. How well the semiconductor devices of the same size are matched with each other can be shown by the mismatch coefficient of the devices, and the larger the mismatch coefficient is, the larger the difference of the semiconductor devices of the same size on a wafer is, so that the product yield is affected. In order to reduce the mismatch coefficient of the same-size semiconductor devices as much as possible, circuit design and layout are required according to a certain matching principle.
Disclosure of Invention
The invention aims to provide a layout structure of a semiconductor device, which improves the area occupation ratio of a first P-type well region between two N-type well regions, can reduce the mismatch coefficient of the semiconductor device and improves the mismatch phenomenon of the semiconductor device.
In order to achieve the above object, the present invention provides a layout structure of a semiconductor device, including:
A semiconductor substrate;
The first P-type well region is positioned in the semiconductor substrate, the first P-type well region comprises a first P-type sub-well region and two second P-type sub-well regions, the two second P-type sub-well regions are respectively connected with two ends of the first P-type sub-well region along the length direction of the first P-type sub-well region, and the widths of the two second P-type sub-well regions are larger than the width of the first P-type sub-well region;
the two N-type well regions are both positioned in the semiconductor substrate, the two N-type well regions are symmetrically arranged on two sides of the first P-type well region along the width direction of the first P-type well region, and each N-type well region, the first P-type sub-well region and the second P-type sub-well region are all provided with gaps.
Optionally, the lengths of the two N-type well regions and the first P-type well region are the same, and two ends of the two N-type well regions and the two ends of the first P-type well region are aligned along the length direction of the first P-type well region.
Optionally, the gap between each N-type well region and the first P-type sub-well region is the same, and the gap between each N-type well region and the second P-type sub-well region is the same.
Optionally, a gap between the N-type well region and the first P-type sub-well region is larger than a gap between the N-type well region and the second P-type sub-well region.
Optionally, the gap between the N-type well region and the second P-type sub-well region is a first gap, and the value of the first gap is equal to half of the minimum design distance between the two N-type well regions.
Optionally, the semiconductor device further includes a first active region located in the semiconductor substrate, at least part of the first active region is located between two N-type well regions, and part of the first P-type sub-well region is located in the first active region, and the length of the first active region is smaller than that of the first P-type sub-well region.
Optionally, each of the second P-type sub-well regions has a gap with the first active region, and each of the second P-type sub-well regions has the same gap with the first active region.
Optionally, a gap between the second P-type sub-well region and the first active region is a second gap, and a value of the second gap is 0.2 [ mu ] m to 0.5 [ mu ] m.
Optionally, gaps between the N-type well region and the first P-type sub-well region and between the N-type well region and the second P-type sub-well region are the semiconductor substrate.
Optionally, the method further comprises:
a gate pattern on the semiconductor substrate and covering the first active region and a portion of the N-type well region;
two second active regions respectively located in the two N-type well regions at two sides of the gate pattern;
The second P-type well region is positioned in the semiconductor substrate and surrounds the two N-type well regions and the first P-type well region;
and the third active region is positioned in the second P-type well region and surrounds the two N-type well regions and the first P-type well region.
The layout structure of the semiconductor device provided by the invention comprises the following components: the semiconductor device comprises a semiconductor substrate, a first P-type well region and two N-type well regions, wherein the first P-type well region is positioned in the semiconductor substrate, the first P-type well region comprises a first P-type sub-well region and two second P-type sub-well regions, the two second P-type sub-well regions are respectively connected with two ends of the first P-type sub-well region along the length direction of the first P-type sub-well region, and the widths of the two second P-type sub-well regions are larger than those of the first P-type sub-well region; the two N-type well regions are both positioned in the semiconductor substrate, are symmetrically arranged at two sides of the first P-type well region along the width direction of the first P-type well region, and each N-type well region, the first P-type sub-well region and the second P-type sub-well region are all provided with gaps. The invention has the unexpected effects that the first P-type well region comprises a first P-type sub-well region and two second P-type sub-well regions by arranging the specific morphology of the first P-type well region, the widths of the two second P-type sub-well regions are larger than the widths of the first P-type sub-well region, and under the condition that the electric performance of the device is not influenced as much as possible, the area of the first P-type well region between the two N-type well regions is increased by expanding the widths of the two second P-type sub-well regions, which is equivalent to increasing the area ratio of the first P-type well region between the two N-type well regions, the mismatch coefficient of the semiconductor device can be reduced, and the mismatch phenomenon of the semiconductor device is improved.
Drawings
Fig. 1 is a schematic diagram of a layout structure of a semiconductor device.
Fig. 2 is a fitting relation diagram of a dimension coefficient and a standard deviation of an opening voltage corresponding to a layout structure of a semiconductor device.
Fig. 3 is a schematic diagram of a layout structure of a semiconductor device according to an embodiment of the present invention.
Wherein reference numerals of fig. 1 are:
100-a semiconductor substrate; 200-P type well region; 300-N type well region; 400-active area.
The reference numerals of fig. 2 are:
10-a semiconductor substrate; 21-a first P-type well region; 211-a first P-type sub-well region; 212-a second P-type sub-well region; 22-a second P-type well region; a 30-N type well region; 41-a first active region; 42-a second active region; 43-a third active region; 50-gate pattern.
Detailed Description
Fig. 1 is a schematic diagram of a layout structure of a semiconductor device. Referring to fig. 1, the present application provides a layout structure of a semiconductor device, which includes a semiconductor substrate 100, a P-type well region 200, two N-type well regions 300 and an active region 400, wherein for convenience, a gate pattern is not shown in the schematic diagram and other structures are not labeled, the layout structure of the semiconductor device in fig. 1 is schematically a layout structure of an NMOS transistor, and a wafer has a plurality of NMOS transistors thereon. The P-type well region 200, the two N-type well regions 300 and the active region 400 are all located in the semiconductor substrate 100, the P-type well region 200 is in a strip shape, the two N-type well regions 300 are symmetrically disposed at two sides of the P-type well region 200, and the semiconductor substrate 100 is located between the P-type well region 200 and the two N-type well regions 300. The active region 400 is located in the semiconductor substrate 100, at least a portion of the active region 400 is located between two N-type well regions 300, the active region 400 may be extended to be located in two N-type well regions 300, the distance between the two N-type well regions 300 is D1, and the length of the active region 400 along the length direction (Y direction) of the P-type well region 200 is D2. The area of the P-type well region 200 is S1, the area between the two N-type well regions 300 forms a rectangle (as shown by the dashed box in fig. 1), the rectangular area is S2, and the area ratio of the P-type well region 200 between the two N-type well regions 300 is S1: s2 (i.e., the area ratio of the region between the P-type well region 200 and the two N-type well regions 300).
The distance D1 between the two N-type well regions 300 and the length D2 of the active region 400 along the length direction of the P-type well region 200 are both within a design distance range, the design distance range of the distance D1 between the two N-type well regions 300 including a minimum design distance D1 min and a maximum design distance D1 max, and the design distance range of the length D2 of the active region 400 along the length direction of the P-type well region 200 including a minimum design distance D2 min and a maximum design distance D2 max.
Fig. 2 is a fitting relation diagram of a dimension coefficient and a standard deviation of an opening voltage corresponding to a layout structure of a semiconductor device. Referring to fig. 2, fig. 2 shows fitting relationships between size coefficients and standard deviations of on voltages corresponding to three sets of different design pitches, which are a first set, a second set and a third set, respectively, wherein an abscissa in fig. 2 is a size coefficient, an ordinate is a standard deviation of on voltages, and formulas of the size coefficients and the standard deviations of the on voltages are as follows:
；
Wherein, The dimension coefficient, σ, is the standard deviation of the turn-on voltage, which is the standard deviation of the turn-on voltage of two semiconductor devices of the same size on the same wafer (two NMOS transistors of the same size on a wafer), and K is the slope.
Table 1 is a slope correlation table for three sets of design pitches. Referring to table 1, the first set of design pitches is D1 min and 2D2 max、D2max、2D2min and D2 min, the second set of design pitches is 2D1 min and 2D2 max、D2max、2D2min and D2 min, the third set of design pitches is D1 max and 2D2 max、D2max、2D2min and D2 min, and 2D1 min<D1max,2D2min<D2max, K1 is the slope corresponding to the first set of design pitches, K2 is the slope corresponding to the second set of design pitches, K3 is the slope corresponding to the third set of design pitches, and the slope corresponding to the above-mentioned design pitches is the fitting approximation slope. As can be seen from fig. 2, the fitting relationship between the size coefficient corresponding to the first set of design pitches and the standard deviation of the turn-on voltage tends to be more on a line, which indicates that the semiconductor device manufactured by using the first set of design pitches has better uniformity, and the reason for the uniformity is that the minimum design pitch D1 min between the two N-type well regions 300 is adopted, and the slope K1 corresponding to the first set of design pitches is the minimum, and the smaller the pitch D1 between the two N-type well regions 300 is, the smaller the corresponding slope is, the better the uniformity of the semiconductor device is, the slope is equivalent to the mismatch coefficient, that is, the better the matching is, and the smaller the mismatch coefficient is. In contrast, as the slope K2 corresponding to the second set of design pitches and the slope K3 corresponding to the third set of design pitches become larger gradually, the pitch D1 between the two N-type well regions 300 becomes larger gradually, that is, the larger the slope is, the larger the mismatch coefficient is, the larger the variability of the same-size semiconductor devices on the wafer is, which affects the product yield.
TABLE 1 slope correlation Table for three sets of design pitches
| Slope of | 2D2max | D2max | 2D2min | D2min |
| D1max | K3 | K3 | K3 | K3 |
| 2D1min | K2 | K2 | K2 | K2 |
| D1min | K1 | K1 | K1 | K1 |
However, the design pitch is often fixed during the fabrication of the semiconductor device, and most of the cases do not select the minimum design pitch D1 min between two N-type well regions 300, which results in an increase in the mismatch coefficient of the semiconductor device with an increase in the pitch D1 between two N-type well regions 300.
Table 2 shows the area ratio of the P-type well region between two N-type well regions corresponding to the three sets of design pitches. Referring to table 2, the area ratio of the P-well region between the two N-well regions is the area ratio of the P-well region 200 to the region between the two N-well regions 300, the first set of design pitches are D1 min and 2D2 max、D2max、2D2min and D2 min, the second set of design pitches are 2D1 min and 2D2 max、D2max、2D2min and D2 min, the third set of design pitches are D1 max and 2D2 max、D2max、2D2min and D2 min, and X represents a base number, such as 2, 4, 6, etc. If X is 2, 4, and 6 respectively, the area ratio of the P-type well region between the two N-type well regions corresponding to the first set of design pitches in table 2 is 8%, 16%, and 24%, the area ratio of the P-type well region between the two N-type well regions corresponding to the second set of design pitches is 4%, 8%, and 12%, the area ratio of the P-type well region between the two N-type well regions corresponding to the third set of design pitches is 2%, 4%, and 6%, respectively, it can be seen that as the pitch D1 between the two N-type well regions 300 increases, the area ratio of the P-type well region between the two N-type well regions decreases, and as the pitch D1 between the two N-type well regions 300 increases, the mismatch coefficient of the semiconductor device increases, and the area ratio of the P-type well region between the two N-type well regions decreases as the pitch D1 between the two N-type well regions increases, as shown in table 1. Therefore, it can be derived that as the area ratio of the P-type well region between the two N-type well regions decreases, the mismatch coefficient of the semiconductor device increases.
TABLE 2 area ratio of P-well region between two N-well regions corresponding to three groups of design pitches
| Area ratio (%) | 2D2max | D2max | 2D2min | D2min |
| D1max | 1X | 1X | 1X | 1X |
| 2D1min | 2X | 2X | 2X | 2X |
| D1min | 4X | 4X | 4X | 4X |
Therefore, the present invention provides a semiconductor device layout structure, comprising: the semiconductor device comprises a semiconductor substrate, a first P-type well region and two N-type well regions, wherein the first P-type well region is positioned in the semiconductor substrate, the first P-type well region comprises a first P-type sub-well region and two second P-type sub-well regions, the two second P-type sub-well regions are respectively connected with two ends of the first P-type sub-well region along the length direction of the first P-type sub-well region, and the widths of the two second P-type sub-well regions are larger than those of the first P-type sub-well region; the two N-type well regions are both positioned in the semiconductor substrate, are symmetrically arranged at two sides of the first P-type well region along the width direction of the first P-type well region, and each N-type well region, the first P-type sub-well region and the second P-type sub-well region are all provided with gaps. Under the condition that the electric performance of the device is not affected as much as possible, the invention increases the area of the first P-type well region between the two N-type well regions by enlarging the widths of the two second P-type sub-well regions, which is equivalent to increasing the area ratio of the first P-type well region between the two N-type well regions, can reduce the mismatch coefficient of the semiconductor device and improve the mismatch phenomenon of the semiconductor device.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be understood that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like indicate orientations or positional relationships based on those shown in the drawings, or those conventionally put in place when the product of the application is used, or those conventionally understood by those skilled in the art, merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
Furthermore, relational terms such as "first" and "second," and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or device comprising the element. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
Fig. 3 is a schematic diagram of a layout structure of a semiconductor device according to the present embodiment. Referring to fig. 3, the present invention is directed to a layout structure of a semiconductor device, including: the semiconductor substrate 10, the first P-type well region 21, the two N-type well regions 30, the first active region 41, and the two second active regions 42.
The first P-type well region 21 is located in the semiconductor substrate 10, where the first P-type well region 21 includes a first P-type sub-well region 211 and two second P-type sub-well regions 212, and the two second P-type sub-well regions 212 are respectively connected to two ends of the first P-type sub-well region 211 along the length direction (Y direction) of the first P-type sub-well region 211, specifically, the center positions of the two second P-type sub-well regions 212 near one side of the first P-type sub-well region 211 are respectively connected to two ends of the first P-type sub-well region 211. The widths of the two second P-type sub-well regions 212 (the dimensions of the second P-type sub-well regions 212 along the X-direction) are the same and are both larger than the width of the first P-type sub-well region 211 (the dimensions of the first P-type sub-well region 211 along the X-direction). In this embodiment, the first P-type well region 21 is configured in a specific pattern (similar to an i-shape), and in a general configuration, the first P-type well region should be in a strip shape with a fixed area, in this embodiment, the first P-type well region 21 includes a first P-type sub-well region 211 and two second P-type sub-well regions 212, and the widths of the two second P-type sub-well regions 212 are both larger than the width of the first P-type sub-well region 211, so that the areas of the two second P-type sub-well regions 212 are enlarged, i.e. the area of the first P-type well region 21 is increased. Because the position of the first P-type sub-well region 211 corresponds to the channel of the semiconductor device, under the condition that the electrical performance of the semiconductor device is not affected, the opening voltage of the semiconductor device is kept unchanged, the area of the first P-type sub-well region 211 is not easy to expand, so that the first P-type well region 21 is divided into the first P-type sub-well region 211 and two second P-type sub-well regions 212, the two second P-type sub-well regions 212 are positioned at two ends of the first P-type sub-well region 211, the channel of the semiconductor device is avoided, the area of the two second P-type sub-well regions 212 is expanded, the area of the first P-type well region 21 is increased, and doping conditions such as doping concentration of the first P-type well region 21 can not be changed.
The two N-type well regions 30 are located in the semiconductor substrate 10, the two N-type well regions 30 are symmetrically disposed at two sides of the first P-type well region 21 along the width direction (X direction) of the first P-type well region 21, and each N-type well region 30 has a gap with the first P-type sub-well region 211 and the second P-type sub-well region 212. The lengths of the two N-type well regions 30 and the first P-type well region 21 (the dimensions of the N-type well region 30 and the first P-type well region 21 in the Y direction) are the same, and both ends of the two N-type well regions 30 and the first P-type well region 21 are aligned in the length direction of the first P-type well region 21. In this embodiment, the dimensions of the two N-type well regions 30 along the X-direction and the Y-direction are the same, the shapes of the two N-type well regions 30 are preferably rectangular, and the region between the two corresponding N-type well regions 30 forms a rectangle; the spacing W between the two N-type well regions 30 is within a design spacing range including a minimum design spacing W min and a maximum design spacing W max, the minimum design spacing W min and the maximum design spacing W max are typically limit values, which are not taken in actual layout design.
In this embodiment, the gap between each N-type well region 30 and the first P-type sub-well region 211 is the same, and the gap between each N-type well region 30 and the second P-type sub-well region 212 is the same, and the gap between each N-type well region 30 and the first P-type sub-well region 211 is larger than the gap between each N-type well region 30 and the second P-type sub-well region 212. In this embodiment, the gap between the N-type well region 30 and the second P-type sub-well region 212 is the first gap d1, and the value of the first gap d1 is preferably equal to half of the minimum design spacing W min between the two N-type well regions 30, which is not limited thereto; for example, assuming that the minimum design pitch W min is 1 μm and the maximum design pitch W max is 8 μm, the value of the first gap d1 is 0.5 μm, and the pitch W between the two N-type well regions 30 in the actual layout design is greater than the minimum design pitch W min.
The first active region 41 is located in the semiconductor substrate 10, at least a portion of the first active region 41 is located between the two N-type well regions 30, a portion of the first active region 41 may be located in the two N-type well regions 30 in an extending manner, and a portion of the first P-type sub-well region 211 is located in the first active region 41 (in fig. 1, transparency is provided for filling of the first active region 41 for convenience in illustrating the relationship between the first active region 41 and the N-type well regions 30 and the first P-type sub-well region 211). In the present embodiment, the length L of the first active region 41 is smaller than the length of the first P-type sub-well region 211 (the dimensions of the first active region 41 and the first P-type sub-well region 211 along the Y direction). In this embodiment, each of the second P-type sub-well regions 212 has a gap with the first active region 41, and each of the second P-type sub-well regions 212 has the same gap with the first active region 41. Specifically, the gap between the second P-type sub-well region 212 and the first active region 41 is a second gap d2, and the value of the second gap d2 is 0.2 μm to 0.5 μm, preferably 0.3 μm, which is not limited thereto.
In this embodiment, the gaps between the N-type well region 30 and the first and second P-type sub-well regions 211 and 212 are the semiconductor substrate 10, i.e., the first and second gaps d1 and d2 are the semiconductor substrate 10, and no well region and no active region are formed at the positions of the first and second gaps d1 and d 2. The first active region 41 serves as a channel region of the semiconductor device, and by providing the second gap d2, the area of the two second P-type sub-well regions 212 is ensured to be enlarged, and meanwhile, the influence on the turn-on voltage of the semiconductor device is avoided, namely, the electric performance of the device is ensured not to be influenced as much as possible.
Further, the semiconductor device further includes a gate pattern 50 (only indicated by rectangular boxes in fig. 1 for convenience of illustration), and the gate pattern 50 is located on the semiconductor substrate 10 and covers the first active region 41 and a portion of the N-type well region 30, and also covers a portion of the first P-type well region 21 (covers the first P-type sub-well region 211 and a portion of the second P-type sub-well region 212). The two second active regions 42 are respectively located in the two N-type well regions 30 at both sides of the gate pattern 50 and have a gap with the gate pattern 50.
Further, the semiconductor device further includes a second P-type well region 22, the second P-type well region 22 is located in the semiconductor substrate 10, and the second P-type well region 22 surrounds the two N-type well regions 30 and the first P-type well region 21 in a zigzag shape.
Further, the semiconductor device further includes a third active region 43, the third active region 43 is located in the second P-type well region 22, and the third active region 43 surrounds the two N-type well regions 30 and the first P-type well region 21 in a zigzag shape, and the third active region 43 has a gap with the two N-type well regions 30 and the first P-type well region 21. The first active region 41, the second active region 42 and the third active region 43 in this embodiment have the same conductivity type and are all N-type.
In this embodiment, the semiconductor device is an NMOS transistor, specifically a high-voltage FD NMOS transistor. Under the condition that the set distance W between the two N-type well regions 30 and the length L of the first active region 41 (the two dimensions determine the size of the channel region of the semiconductor device), the specific morphology of the first P-type well region 21 is set, so that the first P-type well region 21 comprises a first P-type sub-well region 211 and two second P-type sub-well regions 212, the widths of the two second P-type sub-well regions 212 are larger than the width of the first P-type sub-well region 211, and the area of the first P-type well region 21 between the two N-type well regions 30 is increased by enlarging the widths of the two second P-type sub-well regions 212 under the condition that the electric performance of the device is not influenced as much as possible. If the area of the first P-type well region 21 between the two N-type well regions 30 is S1, the area of the region between the two N-type well regions 30 is S2, and the area S1 of the first P-type well region 21 between the two N-type well regions 30 is increased without changing the area S2 of the region between the two N-type well regions 30 (i.e., without increasing the area ratio of the first P-type well region 21 between the two N-type well regions 30, the area S2 of the region between the two N-type well regions 30 is reduced, and the area S2 of the region between the two N-type well regions 30 is related to the channel region of the semiconductor device, so that the electrical performance of the semiconductor device is not affected, the area S2 of the region between the two N-type well regions 30 is not easily changed, the area S1 of the first P-type well region 21 between the two N-type well regions 30 is increased, which is equivalent to increasing the area S1 of the first P-type well region 21 between the two N-type well regions 30, and the mismatch coefficient of the semiconductor device can be reduced.
In summary, the layout structure of the semiconductor device provided by the invention comprises: the semiconductor device comprises a semiconductor substrate, a first P-type well region and two N-type well regions, wherein the first P-type well region is positioned in the semiconductor substrate, the first P-type well region comprises a first P-type sub-well region and two second P-type sub-well regions, the two second P-type sub-well regions are respectively connected with two ends of the first P-type sub-well region along the length direction of the first P-type sub-well region, and the widths of the two second P-type sub-well regions are larger than those of the first P-type sub-well region; the two N-type well regions are both positioned in the semiconductor substrate, are symmetrically arranged at two sides of the first P-type well region along the width direction of the first P-type well region, and each N-type well region, the first P-type sub-well region and the second P-type sub-well region are all provided with gaps. The invention has the unexpected effects that the first P-type well region comprises a first P-type sub-well region and two second P-type sub-well regions by arranging the specific morphology of the first P-type well region, the widths of the two second P-type sub-well regions are larger than the widths of the first P-type sub-well region, and under the condition that the electric performance of the device is not influenced as much as possible, the area of the first P-type well region between the two N-type well regions is increased by expanding the widths of the two second P-type sub-well regions, which is equivalent to increasing the area ratio of the first P-type well region between the two N-type well regions, the mismatch coefficient of the semiconductor device can be reduced, and the mismatch phenomenon of the semiconductor device is improved.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. A semiconductor device layout structure, comprising:
A semiconductor substrate;
The first P-type well region is positioned in the semiconductor substrate, the first P-type well region comprises a first P-type sub-well region and two second P-type sub-well regions, the two second P-type sub-well regions are respectively connected with two ends of the first P-type sub-well region along the length direction of the first P-type sub-well region, and the widths of the two second P-type sub-well regions are larger than the width of the first P-type sub-well region;
the two N-type well regions are both positioned in the semiconductor substrate, the two N-type well regions are symmetrically arranged on two sides of the first P-type well region along the width direction of the first P-type well region, and each N-type well region, the first P-type sub-well region and the second P-type sub-well region are all provided with gaps.
2. The semiconductor device layout structure of claim 1, wherein the two N-type well regions and the first P-type well region have the same length, and both ends of the two N-type well regions and the first P-type well region are aligned along the length direction of the first P-type well region.
3. The semiconductor device layout structure of claim 1 wherein the gap between each of said N-well regions and said first P-type sub-well region is the same and the gap between each of said N-well regions and said second P-type sub-well region is the same.
4. The semiconductor device layout structure of claim 1 wherein a gap between said N-well region and said first P-type sub-well region is greater than a gap between said N-well region and said second P-type sub-well region.
5. The semiconductor device layout structure of claim 4, wherein the gap between the N-type well region and the second P-type sub-well region is a first gap, and the value of the first gap is equal to half of the minimum design spacing between the two N-type well regions.
6. The semiconductor device layout structure of claim 4, further comprising a first active region in the semiconductor substrate, at least a portion of the first active region being located between two of the N-type well regions, and a portion of the first P-type sub-well region being located in the first active region, the first active region having a length less than a length of the first P-type sub-well region.
7. The semiconductor device layout structure of claim 6 wherein each of said second P-type sub-well regions has a gap with said first active region and wherein each of said second P-type sub-well regions has the same gap with said first active region.
8. The semiconductor device layout structure according to claim 7, wherein a gap between the second P-type sub-well region and the first active region is a second gap, and the value of the second gap is 0.2 [ mu ] m to 0.5 [ mu ] m.
9. The semiconductor device layout structure of claim 1, wherein gaps between the N-type well region and the first and second P-type sub-well regions are the semiconductor substrate.
10. A semiconductor device layout structure according to claim 6, further comprising:
a gate pattern on the semiconductor substrate and covering the first active region and a portion of the N-type well region;
two second active regions respectively located in the two N-type well regions at two sides of the gate pattern;
The second P-type well region is positioned in the semiconductor substrate and surrounds the two N-type well regions and the first P-type well region;
and the third active region is positioned in the second P-type well region and surrounds the two N-type well regions and the first P-type well region.
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