CN118039605A

CN118039605A - Semiconductor packaging structure and preparation method thereof

Info

Publication number: CN118039605A
Application number: CN202211376132.5A
Authority: CN
Inventors: 陈军; 王春阳
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-11-04
Filing date: 2022-11-04
Publication date: 2024-05-14
Also published as: WO2024093153A1

Abstract

The present disclosure provides a semiconductor package structure and a method of manufacturing the same, the semiconductor package structure including an interposer, a conductive via, and a capacitor; the interposer comprises a first surface and a second surface which are opposite in the thickness direction, and the conductive through holes and the capacitors are arranged in the interposer at intervals; opposite ends of the conductive through hole extend to the first surface and the second surface respectively; the capacitor comprises a first electrode layer, a capacitor dielectric layer and a second electrode layer which are sequentially laminated; at least part of the first electrode layer is close to the first surface and is electrically led out of the intermediate layer through the first surface by the first conductive structure; at least part of the second electrode layer is close to the second face, and the intermediate layer is electrically led out from the second face through the second conductive structure. The structure of the capacitor in the semiconductor packaging structure can be effectively simplified, the manufacturing difficulty is reduced, and meanwhile, the capacitance is improved.

Description

Semiconductor packaging structure and preparation method thereof

Technical Field

The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor packaging structure and a preparation method thereof.

Background

The semiconductor package is widely used in a semiconductor device or apparatus in which a plurality of semiconductor devices are arranged in a package structure in a vertically stacked or laterally side-by-side manner and a protective effect is formed on the semiconductor devices by the package structure.

The semiconductor package includes a package substrate, a semiconductor device to be packaged, and a package layer. The semiconductor device to be packaged can be a plurality of chips, the chips are stacked or arranged on the packaging substrate side by side, the outside of the chips are packaged through the packaging layer, the chips are prevented from being exposed, and the protection effect on the chips is guaranteed. And a silicon intermediate layer (Si Interposer) is arranged between different chips and used as a metal interconnection structure to realize signal connection between different chips. A through silicon via structure (Through Silicon Vias, TSV) and a deep trench Capacitor (DEEP TRENCH Capacitor, DTC) are disposed in the silicon interposer.

However, the deep trench capacitor in the silicon interposer is complex in structure, difficult to manufacture, and has to be increased in capacitance.

Disclosure of Invention

The semiconductor packaging structure and the preparation method thereof can effectively simplify the structure of the capacitor in the semiconductor packaging structure, reduce the preparation difficulty and improve the capacitance.

In a first aspect, the present disclosure provides a semiconductor package structure comprising an interposer, a conductive via, and a capacitor;

The interposer comprises a first surface and a second surface which are opposite in the thickness direction, and the conductive through holes and the capacitors are arranged in the interposer at intervals;

opposite ends of the conductive through hole extend to the first surface and the second surface respectively; the capacitor comprises a first electrode layer, a capacitor dielectric layer and a second electrode layer which are sequentially laminated; at least part of the first electrode layer is close to the first surface and is electrically led out of the intermediate layer through the first surface by the first conductive structure; at least part of the second electrode layer is close to the second face, and the intermediate layer is electrically led out from the second face through the second conductive structure.

In the above semiconductor package structure, optionally, the capacitor includes a plurality of capacitors, and the plurality of capacitors are arranged in the interposer at intervals.

In the above semiconductor package structure, optionally, an end of the first electrode layer near the first surface, an end of the conductive via near the first surface, and the first surface are flush.

In the above semiconductor package structure, optionally, the semiconductor package further includes a third conductive structure, wherein an end of the conductive via near the first surface is connected to the third conductive structure, and the interposer is electrically led out through the third conductive structure;

the first conductive structure and the third conductive structure are the same material.

In the above semiconductor package structure, optionally, a space is provided between the second electrode layer near the second surface and the second surface, and the second conductive structure is embedded in the interposer between the second surface and the second electrode layer, one end of the second conductive structure is connected to the second electrode layer, and the other end of the second conductive structure is led to the second surface.

In the above semiconductor package structure, optionally, the semiconductor package further includes a fourth conductive structure, the fourth conductive structure is located on the second surface, and the second conductive structure is connected with the fourth conductive structure;

when a plurality of capacitors are arranged, the second electrode layers of the capacitors are connected with the same fourth conductive structure through the second conductive structure; or, the plurality of fourth conductive structures are provided, and the second electrode layers of the plurality of capacitors are connected with different fourth conductive structures through the corresponding second conductive structures.

In the above semiconductor package structure, optionally, the semiconductor package further includes a fifth conductive structure, the fifth conductive structure is located on the second surface, and an end of the conductive via close to the second surface is flush with the second surface and connected to the fifth conductive structure, and the interposer is electrically led out through the fifth conductive structure.

In the above semiconductor package structure, optionally, the interposer includes an interposer body layer and a dielectric layer, the dielectric layer is distributed near a first surface of the interposer, and the interposer body layer is distributed near a second surface of the interposer;

And at least a portion of the dielectric layer is disposed between the conductive via and the interposer body layer; and/or at least a portion of the dielectric layer is distributed between the capacitor and the interposer body layer.

In a second aspect, the present disclosure provides a method for manufacturing a semiconductor package structure, including:

providing an interposer, wherein the interposer comprises a first surface and a second surface which are opposite in the thickness direction;

forming a conductive through hole and a capacitor in the intermediate layer, wherein the conductive through hole and the capacitor are arranged at intervals, opposite ends of the conductive through hole extend to the first surface and the second surface respectively, and the capacitor comprises a first electrode layer, a capacitor medium layer and a second electrode layer which are sequentially stacked; at least part of the first electrode layer is close to the first surface and is electrically led out of the intermediate layer through the first surface by the first conductive structure; at least part of the second electrode layer is close to the second face, and the intermediate layer is electrically led out from the second face through the second conductive structure.

In the above method for manufacturing a semiconductor package structure, optionally, forming the conductive via and the capacitor includes:

forming a conductive via in the interposer;

Forming a capacitor groove in the intermediate layer, wherein the bottom of the capacitor groove and the bottom of the conductive through hole are spaced from the bottom of the intermediate layer, and the space between the bottom of the capacitor groove and the bottom of the intermediate layer is larger than the space between the bottom of the conductive through hole and the bottom of the intermediate layer;

A capacitor is formed in the capacitor trench.

In the above method for manufacturing a semiconductor package structure, optionally, forming a capacitor in the capacitor trench includes:

Forming a second electrode layer, wherein the second electrode layer is positioned in the capacitor groove, and a first groove is formed in the second electrode layer;

Forming a capacitance medium layer, wherein the capacitance medium layer is positioned in the first groove, and a second groove is formed in the capacitance medium layer;

And forming a first electrode layer, wherein the first electrode layer is positioned in the second groove, and the first electrode layer, the capacitance medium layer and the second electrode layer jointly form a capacitance.

In the above method for manufacturing a semiconductor package, optionally, after forming the capacitor, the method further includes:

flattening the top of the conductive via, the top of the capacitor and the top of the interposer so that the top of the conductive via, the top of the capacitor and the top of the interposer are flush, the top of the interposer forming a first face;

and forming a first conductive structure and a third conductive structure, wherein the first conductive structure is connected with the first electrode layer, the third conductive structure is connected with the top of the conductive through hole, and the first conductive structure and the third conductive structure are made of the same material.

In the above method for manufacturing a semiconductor package, optionally, after forming the first conductive structure and the third conductive structure, the method further includes:

Processing the bottom of the interposer to expose the bottom of the conductive via; forming a second surface on the bottom surface of the processed intermediate layer;

forming a fourth groove which is positioned in the intermediate layer at the bottom of the capacitor and exposes the second electrode layer of the capacitor;

Forming a second conductive structure, wherein the second conductive structure is positioned in the fourth groove and is connected with the exposed second electrode layer;

Forming a fourth conductive structure which is positioned at the bottom of the intermediate layer and connected with the second conductive structure;

And forming a fifth conductive structure which is positioned at the bottom of the intermediate layer and is connected with the exposed bottom of the conductive through hole.

In the above method for manufacturing a semiconductor package structure, optionally, a plurality of capacitors are arranged in the interposer at intervals;

the second electrode layers of the capacitors are connected with the same fourth conductive structure through second conductive structures; or, the plurality of fourth conductive structures are provided, and the second electrode layers of the plurality of capacitors are connected with different fourth conductive structures through the corresponding second conductive structures.

In the above method for manufacturing a semiconductor package, optionally, providing the interposer includes:

forming an intermediate body layer;

Forming a dielectric layer on the intermediate body layer, the intermediate body layer and the dielectric layer together forming an intermediate layer, the dielectric layer being distributed adjacent to a first face of the intermediate layer, the intermediate body layer being distributed adjacent to a second face of the intermediate layer;

According to the semiconductor packaging structure and the preparation method thereof, the intermediate layer, the conductive through holes and the capacitors are arranged in the semiconductor packaging structure, the conductive through holes and the capacitors are arranged in the intermediate layer at intervals, and the intermediate layer can achieve a protection effect on the intermediate layer and the capacitors. Through extending the both ends of electrically conductive through-hole respectively to the first face and the second face of intermediate layer, be convenient for connect the component that is located the intermediate layer both sides through electrically conductive through-hole, realize the signal transmission between the different components. The capacitor can effectively inhibit circuit noise of the conductive through hole, and reduce influence of circuit voltage on elements packaged by the semiconductor packaging structure. The first electrode layer and the second electrode layer of the capacitor are respectively close to the first surface and the second surface, and the intermediate layer is led out of the first surface and the second surface through different conductive structures, so that the structure of the capacitor can be effectively simplified, the preparation difficulty is reduced, the capacitance of the capacitor is improved, and the performance of the semiconductor packaging structure is optimized.

The construction of the present disclosure, together with other objects and advantages thereof, will be best understood from the following description of the preferred embodiments when read in connection with the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the disclosure;

fig. 2 is a flow chart illustrating a method for manufacturing a semiconductor package according to an embodiment of the disclosure;

Fig. 3 is a schematic flow chart of forming a conductive via and a capacitor in a method for manufacturing a semiconductor package structure according to an embodiment of the disclosure;

fig. 4 is a schematic flow chart of forming a capacitor according to a method for manufacturing a semiconductor package according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram of a structure for forming an interposer and conductive vias according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of forming a capacitor trench according to an embodiment of the disclosure;

fig. 7 is a schematic structural diagram of forming a second electrode layer and a capacitor dielectric layer according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a structure for forming a conductive material provided by an embodiment of the present disclosure;

fig. 9 is a schematic structural view of forming a conductive via and a capacitor according to an embodiment of the present disclosure;

fig. 10 is a schematic structural view of forming a first conductive structure and a third conductive structure according to an embodiment of the present disclosure;

FIG. 11 is a schematic view of a structure of an end portion of an exposed conductive via near a second face provided by an embodiment of the present disclosure;

Fig. 12 is a schematic structural diagram of forming a second conductive structure according to an embodiment of the disclosure.

Reference numerals illustrate:

100. An interposer; 100a, a first face; 100b, a second face; 101. an intermediate body layer; 102. a dielectric layer; 200. a conductive via; 300. a capacitor; 301. a first electrode layer; 302. a capacitance dielectric layer; 303. a second electrode layer; 304. an extension barrier layer; 400. a first conductive structure; 500. a second conductive structure; 600. a third conductive structure; 700. a fourth conductive structure; 800. a fifth conductive structure; 900. a capacitor trench; 901. a second trench; 903. a first mask layer; 904. a conductive material; 905. a sixth conductive structure; 906. a second mask layer; 907. etching the barrier layer; 908. a dielectric layer.

Detailed Description

In the semiconductor package, a silicon interposer is arranged between different chips, and the silicon interposer is used as a metal interconnection structure to realize signal transmission between the chips. And a plurality of TSVs and DTCs are integrated in the silicon interposer, and two ends of the TSVs are connected to chips on two sides of the silicon interposer, so that the interconnection capability of the silicon interposer to the chips is ensured. As the driving strength of semiconductor devices increases, there is a higher current density and a larger current transient in the devices, resulting in a larger voltage fluctuation in circuits of TSV connection chips in semiconductor packages and affecting the operation performance of the chips. In this regard, the DTC may act as a decoupling capacitor to suppress noise in the circuit of the TSV connected chip, thereby mitigating the effects of voltage fluctuations on the chip.

In the related art, the DTC includes a plurality of stacked electrode layers, and a dielectric layer is disposed between each adjacent two electrode layers. In a semiconductor package, the multiple electrode layers of the DTC are all electrically led out through the same side of the silicon interposer. The electrically led connection points of the multi-layer electrode layers are offset from each other on the same side of the silicon interposer and are located at different depth positions in the semiconductor package, respectively. One side of the silicon intermediate layer is provided with a plurality of conductive posts, the depths of the conductive posts in the semiconductor package are different, the conductive posts are respectively connected to connection points of the conductive layers with different depths, and electric signals of the different conductive layers are led out through the different conductive posts.

In the above structure, the structure of the DTC is complex, and the DTC is prepared by photolithography, so that different photomasks need to be used multiple times, which makes the manufacturing process cost higher. In addition, the depths of the conductive posts electrically led out from the electrode layers based on the DTC are different in the semiconductor package, when the conductive plug holes connected with the electrode layers are formed, the etching depth is difficult to control, the yield is low, and the alignment accuracy requirement of the conductive posts and the electrode layers of the DTC is high, so that the preparation difficulty of the conductive posts is increased. The DTC has a plurality of electrode layers, so that the improvement of the capacitance is limited, and the structure of the DTC also limits the capacitance of the capacitor.

For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings in the preferred embodiments of the present disclosure. In the drawings, the same or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of the present disclosure. The embodiments described below by referring to the drawings are exemplary and intended for the purpose of explaining the present disclosure and are not to be construed as limiting the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure. Embodiments of the present disclosure are described in detail below with reference to the attached drawings.

Fig. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the disclosure. Referring to fig. 1, in a first aspect, the present disclosure provides a semiconductor package structure.

The semiconductor package structure includes an interposer 100, a conductive via 200, and a capacitor 300; the interposer 100 includes a first surface 100a and a second surface 100b opposite to each other in a thickness direction, and the conductive via 200 and the capacitor 300 are disposed in the interposer 100 at intervals.

Opposite ends of the conductive via 200 extend to the first face 100a and the second face 100b, respectively; the capacitor 300 includes a first electrode layer 301, a capacitor dielectric layer 302, and a second electrode layer 303, which are sequentially stacked; at least a portion of the first electrode layer 301 is adjacent to the first side 100a and electrically coupled to the interposer 100 through the first side 100a by the first conductive structure 400; at least a portion of the second electrode layer 303 is adjacent to the second side 100b and electrically exits the interposer 100 through the second side 100b by the second conductive structure 500.

It should be noted that the interposer 100 may provide a structural basis for the conductive via 200 and the capacitor 300, and the interposer 100 may be doped or undoped silicon, or silicon-on-insulator (SOI). The interposer 100 may also be a compound semiconductor of germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, and/or indium arsenide. The thickness direction of the interposer 100 may be the direction shown by X in fig. 1, and the first and second sides 100a and 100b of the interposer 100 opposite in the thickness direction may be the top and bottom sides of the interposer 100 shown in fig. 1.

The conductive vias 200 and the capacitors 300 are spaced apart in the interposer 100, the conductive vias 200 and the capacitors 300 may be spaced apart along a direction perpendicular to the first surface 100a to the second surface 100b, the direction perpendicular to the first surface 100a to the second surface 100b may be a direction shown as Y in fig. 1, and the conductive vias 200 and the capacitors 300 may be spaced apart to avoid electrical interference therebetween. Opposite ends of the conductive via 200 extend to the first surface 100a and the second surface 100b, respectively, and the opposite ends of the conductive via 200 may be electrically connected to elements on opposite sides of the interposer 100, respectively, to implement interconnection of the elements. In some embodiments, the conductive via 200 and the capacitor 300 may be further disposed at intervals along a direction having an included angle smaller than 90 degrees with respect to the Y direction, and the direction of the interval therebetween is not limited in this embodiment.

At least a portion of the first electrode layer 301 of the capacitor 300 in the present disclosure is close to the first face 100a, at least a portion of the second electrode layer 303 is close to the second face 100b, and the capacitor 300 is distributed in the entire interposer 100 along the thickness direction of the interposer 100, so that the depth of the capacitor 300 in the interposer 100 can be effectively increased, thereby helping to increase the capacitance of the capacitor 300.

The first electrode layer 301 adjacent to the first side 100a electrically draws the interposer 100 through the first side 100a by the first conductive structure 400, and the second electrode layer 303 adjacent to the second side 100b electrically draws the interposer 100 through the second side 100b by the second conductive structure 500. In this way, the first conductive structures 400 and the second conductive structures 500 are respectively distributed on two opposite sides of the interposer 100 along the thickness direction, so that mutual interference between the first conductive structures and the second conductive structures can be effectively avoided, and the difficulty in setting the electrical extraction structure of the capacitor 300 is reduced. In addition, since only one electrode layer is distributed on the same side of the interposer 100 in the thickness direction, alignment between the electrode layer and the conductive structure is difficult. The structure of the capacitor 300 can be effectively simplified, the manufacturing difficulty of the capacitor 300 is reduced, and the capacitance of the capacitor 300 is improved.

It should be noted that "electrically led out" in the present disclosure may mean that electrical connection is performed through a conductive structure, so as to realize signal conduction. The electrical extraction interposer is to extract signals from the interposer or transfer signals to the interposer through a conductive structure.

Specifically, the interposer 100 includes an interposer body layer 101 and a dielectric layer 102, the dielectric layer 102 being distributed proximate to the first side 100a of the interposer 100, the interposer body layer 101 being distributed proximate to the second side 100b of the interposer 100. The intermediate body layer 101 may be a semiconductor material, such as silicon, germanium, or silicon germanium, and the dielectric layer 102 may be an electrically insulating material, such as silicon oxide, germanium oxide, silicon oxynitride, or silicon germanium oxide. The dielectric layer 102 is disposed near the first side 100a of the interposer 100, and the side of the dielectric layer 102 away from the interposer body layer 101 is the first side 100a of the interposer 100. The interposer body layer 101 is disposed near the second side 100b of the interposer 100, and the side of the interposer body layer 101 away from the dielectric layer 102 is the second side 100b of the interposer 100.

In some embodiments, at least a portion of dielectric layer 102 is distributed between conductive vias 200 and interposer body layer 101. At least a portion of the dielectric layer 102 is distributed between the capacitor 300 and the interposer body layer 101. It should be noted that, based on the interposer body layer 101 being made of a semiconductor material, the dielectric layer 102 distributed between the interposer body layer 101 and the conductive via 200 can effectively avoid the problem of electrical conduction between the interposer body layer 101 and the conductive via 200, and ensure the stability of signal transmission inside the conductive via 200. Similarly, the dielectric layer 102 distributed between the interposer body layer 101 and the capacitor 300 can prevent the two from electrical conduction, so as to ensure the storage stability of the electrical signal in the capacitor 300.

In the semiconductor package structure of the present disclosure, the capacitor 300 includes a plurality of capacitors 300 arranged at intervals. The plurality of capacitors 300 can effectively improve the capacitance in the semiconductor package structure, thereby suppressing noise in the connection circuit of the conductive via 200 by using the capacitors 300 and ensuring the packaging effect of the semiconductor package structure. The number of capacitors 300 may be equal to the number of conductive vias 200, with one capacitor 300 being disposed corresponding to one conductive via 200. In other embodiments, the number of capacitors 300 may be greater than the number of conductive vias 200 or less than the number of conductive vias 200, which is not limited by the present disclosure. In some embodiments, the plurality of capacitors 300 may be spaced apart in a direction perpendicular to the first face 100a to the second face 100 b.

In the capacitor 300, the second electrode layer 303 has a cylindrical structure, the capacitor dielectric layer 302 is located on the inner wall of the cylindrical second electrode layer 303 and encloses a cylindrical region, and the first electrode layer 301 is filled in the cylindrical region; a diffusion barrier layer is further provided between the first electrode layer 301 and the capacitive dielectric layer 302.

The bottom of the second electrode layer 303 of the cylindrical structure is located near the second surface 100b, and is electrically led out through the second conductive structure 500. The first electrode layer 301 is filled in a cylindrical region surrounded by the capacitive dielectric layer 302, and the first electrode layer 301 near the position of the nozzle is near the first surface 100a and is electrically led out through the first conductive structure 400. Based on the fact that the capacitors 300 are distributed in the entire interposer 100 along the thickness direction of the interposer 100 in the present disclosure, the depth of the capacitors 300 is large, and the second electrode layer 303 with the cylindrical structure can effectively improve the structural stability of the capacitors 300, so that the problem that the capacitors 300 collapse or incline in the process is avoided. In addition, the second electrode layer 303 with the cylindrical structure can effectively increase the area of the second electrode layer 303, and correspondingly, the corresponding area of the second electrode layer 303 and the first electrode layer 301 can also be increased, so that the capacitance can be improved.

The material of the first electrode layer 301 may be a metal material including copper, and the material of the capacitance dielectric layer 302 may be a high dielectric constant material. The high dielectric constant material may include, but is not limited to, silicon dioxide, silicon carbide, aluminum oxide, aluminum pentoxide, yttrium oxide, hafnium silicate oxide, hafnium dioxide, zirconium dioxide, strontium carbonate, and zirconium silicate oxide. The material of the second electrode layer 303 may be a metal material including tungsten.

The diffusion barrier layer between the first electrode layer 301 and the capacitance medium layer 302 can effectively avoid the expansion of the metal material of the first electrode layer 301, improve the adhesion of the first electrode layer 301 in the cylindrical region of the capacitance medium layer 302, and ensure the structural stability of the capacitance 300. Taking copper as an example of the material of the first electrode layer 301, the material of the diffusion barrier layer may be thallium. The first electrode layer 301 may be formed by an electroplating process, and a seed layer of copper may be deposited first in the barrel region of the capacitive dielectric layer 302, followed by electroplating to form the complete first electrode layer 301.

Referring to fig. 1, the first electrode layer 301 is flush with one end near the first face 100a, one end of the conductive via 200 near the first face 100a, and the first face 100 a. Compared to the related art, the depth of the electrode layer of the capacitor 300 in the semiconductor package structure is different, so that the depth of the conductive pillars needs to be set to be different, and the difficulty of setting the conductive pillars is greater. The end of the first electrode layer 301 close to the first surface 100a is set to be flush with the first surface 100a, so that the setting difficulty of the first conductive structure 400 can be effectively reduced. And, the end of the conductive via 200 near the first surface 100a is also disposed flush with the first surface 100a, so as to facilitate the provision of an electrical lead-out structure of the conductive via 200.

In some embodiments, there are a plurality of second conductive structures 500 connected to the same capacitor 300, and the plurality of second conductive structures 500 are arranged at intervals. In this way, the electrical extraction efficiency of the second electrode layer 303 of the capacitor 300 can be improved, and when a part of the second conductive structures 500 is damaged, the remaining second conductive structures 500 can achieve the purpose of electrical extraction, so that the plurality of second conductive structures 500 can ensure the stability of electrical extraction of the second electrode layer 303. In fig. 1, 3 second conductive structures 500 corresponding to one capacitor 300 are shown, and 2, 4 or more second conductive structures 500 may be used, which is not limited in the present disclosure. In some embodiments, the plurality of second conductive structures 500 may be spaced apart in a direction perpendicular to the first to second faces 100a to 100 b.

In other embodiments, the first conductive structures 400 may be disposed in plural numbers, and the plural first conductive structures 400 may be arranged at intervals along the direction perpendicular to the first surface 100a to the second surface 100b, so as to improve the electrical extraction efficiency and stability of the first electrode layer 301.

The semiconductor package structure of the present disclosure further includes a third conductive structure 600, one end of the conductive via 200 near the first face 100a is connected to the third conductive structure 600, and the interposer 100 is electrically led out through the third conductive structure 600; the first conductive structure 400 and the third conductive structure 600 are the same material.

The third conductive structure 600 is used to electrically connect the conductive via 200 and the element located on the first surface 100a side of the interposer 100. Because the end of the conductive via 200 near the first surface 100a of the interposer 100 is flush with the first surface 100a, the conductive via can be prepared in the same layer as the first conductive structure 400 of the capacitor 300, and the conductive via and the first conductive structure are made of the same material, so that the preparation difficulty of the semiconductor package structure is reduced.

Referring to fig. 1, a first side 100a of the interposer 100 is provided with a plurality of dielectric layers 908 and an etching stopper layer 907, and the etching stopper layer 907 is located between adjacent dielectric layers 908. Both the first conductive structure 400 and the third conductive structure 600 may be formed by etching and deposition in the multi-layer dielectric layer 908. One of the etching barrier layers 907 is disposed on the first surface 100a of the interposer 100, and the etching barrier layer 907 can effectively protect the structure of the interposer 100 from affecting the first surface 100a of the interposer 100 during etching.

Specifically, a space is provided between the second electrode layer 303 near the second surface 100b and the second surface 100b, the second conductive structure 500 is embedded in the interposer 100 between the second surface 100b and the second electrode layer 303, one end of the second conductive structure 500 is connected to the second electrode layer 303, and the other end of the second conductive structure 500 is led to the second surface 100b.

It should be noted that, the second electrode layer 303 near the second surface 100b may have a spacing between the second surface 100b and 5-10 μm, and the specific value of the spacing is not limited in this disclosure. In the process of manufacturing the semiconductor package structure, the spacing may prevent the second electrode layer 303 from being directly exposed outside the interposer 100, thereby reducing the stability of the capacitor 300. The second conductive structures 500 are embedded in the interposer 100 between the second surface 100b and the second electrode layer 303, and the interposer 100 can be used to protect the second conductive structures 500, so as to avoid the problem of electrical interference between different second conductive structures 500 or between the second conductive structures 500 and the conductive vias 200. The second conductive structure 500 may be a via having a conductive function.

The semiconductor package structure of the present disclosure further includes a fourth conductive structure 700, the fourth conductive structure 700 being located on the second face 100b, the second conductive structure 500 being connected with the fourth conductive structure 700. The fourth conductive structure 700 may be a redistribution layer (Redistribution Layer), and the fourth conductive structure 700 is used to electrically conduct signals from the second electrode layer 303 out of the interposer 100 and to the devices on the second side 100b of the interposer 100.

When there are a plurality of capacitors 300, the fourth conductive structure 700 may have the following two arrangements:

As an implementation manner, the second electrode layers 303 of the plurality of capacitors 300 are all connected to the same fourth conductive structure 700 through the second conductive structure 500. In this way, the electrical signals of the second electrode layers 303 of the capacitors 300 are led out through the same fourth conductive structure 700, so that the difficulty in setting the electrical leads of the capacitors 300 is reduced. In addition, the fourth conductive structure 700 can control the writing of the electrical signals of the second electrode layers 303 of the plurality of capacitors 300, thereby reducing the control difficulty of the semiconductor packaging structure. Both capacitors 300 shown in fig. 1 are electrically drawn through the same fourth conductive structure 700.

In some embodiments, the end of the portion of the conductive via 200 near the second face 100b may also be electrically connected to a fourth conductive structure 700, electrically led out through the fourth conductive structure 700.

As another implementation manner, there are a plurality of fourth conductive structures 700, and the second electrode layers 303 of the plurality of capacitors 300 are connected to different fourth conductive structures 700 through corresponding second conductive structures 500. The second electrode layers 303 of different capacitors 300 are electrically led out through different fourth conductive structures 700, so that the capacitors 300 can be controlled independently, and various control requirements of the semiconductor package structure can be met.

The semiconductor package structure of the present disclosure further includes a fifth conductive structure 800, the fifth conductive structure 800 is located on the second surface 100b, one end of the conductive via 200 near the second surface 100b is flush with the second surface 100b, and is connected to the fifth conductive structure 800, and the interposer 100 is electrically led out through the fifth conductive structure 800.

It should be noted that, the fifth conductive structure 800 may be a bump (μbump) or a micro bump (μbump) located on the second surface 100b of the interposer 100, and the end of the conductive via 200 near the second surface 100b is flush with the second surface 100b and connected to the fifth conductive structure 800, so as to facilitate the electrical signal extraction, while avoiding the influence on the capacitor 300 or other conductive vias 200 adjacent to the conductive via 200.

With continued reference to fig. 1, to meet different connection requirements of the semiconductor package structure, a sixth conductive structure 905 may be further disposed, where the sixth conductive structure 905 is located on one side of the first surface 100a of the interposer 100, and the sixth conductive structure 905 may be electrically connected to the third conductive structure 600 through a via disposed in the dielectric layer 908. The sixth conductive structure 905 may have one or more layers, and when the sixth conductive structure 905 has multiple layers, it may be distributed in the dielectric layers 908 of different layers. The sixth conductive structure 905 may be further electrically connected to other external components through vias.

A second masking layer 906 is shown in fig. 1, a trench is formed through the second masking layer 906 on a side of the sixth conductive structure 905 remote from the interposer 100, after which a via may be formed by depositing a conductive material 904 in the trench to facilitate electrical connection of the sixth conductive structure 905 to other external elements.

Fig. 2 is a schematic flow chart of a method for manufacturing a semiconductor package structure provided by an embodiment of the present disclosure, fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor package structure provided by an embodiment of the present disclosure, forming a conductive via and a capacitor, fig. 4 is a schematic flow chart of a method for manufacturing a semiconductor package structure provided by an embodiment of the present disclosure, fig. 5 is a schematic flow chart of an interposer and a conductive via formed by an embodiment of the present disclosure, fig. 6 is a schematic flow chart of a trench formed by an embodiment of the present disclosure, fig. 7 is a schematic flow chart of a second electrode layer and a capacitor dielectric layer formed by an embodiment of the present disclosure, fig. 8 is a schematic flow chart of a conductive material formed by an embodiment of the present disclosure, fig. 9 is a schematic flow chart of a first conductive via and a third conductive via formed by an embodiment of the present disclosure, fig. 11 is a schematic flow chart of an exposed conductive via near an end of a second surface formed by an embodiment of the present disclosure, and fig. 12 is a schematic flow chart of a second conductive via formed by an embodiment of the present disclosure.

In a second aspect, referring to fig. 2, the present disclosure provides a method for manufacturing a semiconductor package structure, including:

s100: an interposer is provided, the interposer including first and second faces opposite in a thickness direction.

Specifically, providing the interposer 100 may include: forming an interposer body layer 101; dielectric layer 102 is formed, dielectric layer 102 is located on interposer body layer 101, interposer body layer 101 and dielectric layer 102 together form interposer 100, dielectric layer 102 is distributed proximate to first side 100a of interposer 100, and interposer body layer 101 is distributed proximate to second side 100b of interposer 100.

Note that, the interposer body layer 101 and the dielectric layer 102 may be formed by deposition. The deposition thickness of the interposer body layer 101 and the dielectric layer 102 may be adjusted according to the depth of the conductive vias 200 and the capacitors 300, which is not limited by the present disclosure.

S200: forming a conductive through hole and a capacitor in the intermediate layer, wherein the conductive through hole and the capacitor are arranged at intervals, opposite ends of the conductive through hole extend to the first surface and the second surface respectively, and the capacitor comprises a first electrode layer, a capacitor medium layer and a second electrode layer which are sequentially stacked; at least part of the first electrode layer is close to the first surface and is electrically led out of the intermediate layer through the first surface by the first conductive structure; at least part of the second electrode layer is close to the second face, and the intermediate layer is electrically led out from the second face through the second conductive structure.

Specifically, forming the conductive via 200 and the capacitor 300 includes:

S201: conductive vias are formed in the interposer. The conductive via 200 may be formed by means of mask etching and deposition. A mask layer (not shown) is formed on the interposer 100, and a trench is formed in the interposer 100 by etching at a position corresponding to the formed conductive via 200 through a mask opening of the mask layer. Conductive material 904 is deposited in the trenches to form conductive vias 200. The conductive material 904 may be a metallic material including copper, tungsten.

S202: and forming a capacitor groove in the intermediate layer, wherein the bottom of the capacitor groove and the bottom of the conductive through hole are spaced from the bottom of the intermediate layer, and the spacing between the bottom of the capacitor groove and the bottom of the intermediate layer is larger than the spacing between the bottom of the conductive through hole and the bottom of the intermediate layer.

Referring to fig. 5 and 6, the formation of the capacitor trench 900 may be formed by mask etching, that is, the first mask layer 903 is formed on the interposer 100, and the opening of the first mask layer 903 corresponds to the location of the formed capacitor trench 900, and the capacitor trench 900 is formed in the interposer 100 by etching.

The depth of the capacitor trench 900 is smaller than the depth of the conductive via 200, so that a space between the bottom of the capacitor trench 900 and the bottom of the interposer 100 is ensured to be larger than a space between the bottom of the conductive via 200 and the bottom of the interposer 100. In this way, in the subsequent processes of the fourth conductive structure 700 and the fifth conductive structure 800, the bottom of the capacitor 300 is prevented from being exposed, so as to ensure the structural stability of the capacitor 300 in the whole semiconductor package process.

In some embodiments, the capacitor trench 900 may be formed simultaneously with the trench of the conductive via 200, which may effectively simplify the process. Specific steps may be to form the conductive via 200 and the capacitor 300, including:

a first trench and a second trench 901 are formed in the interposer 100, the second trench 901 having a depth smaller than the depth of the first trench. A mask layer having two mask openings is selected, and the two mask openings correspond to the positions of the formed conductive via 200 and the capacitor 300, respectively, and the intermediate layer 100 is etched along the mask layer to form the first trench and the second trench 901.

Thereafter, a conductive material 904 is formed in the first trench, the first trench containing the conductive material 904 forming a conductive via 200; the capacitor 300 is formed in the second trench 901.

In some embodiments, after forming the trench of conductive via 200, prior to depositing conductive material 904 in conductive via 200, further comprising: an insulating material is deposited in the trenches of the conductive vias 200, which may be the same material as the dielectric layer 102, such that at least a portion of the dielectric layer 102 is distributed between the conductive vias 200 and the interposer body layer 101. In this way, electrical isolation between the conductive via 200 and the interposer body layer 101 can be ensured, and the semiconductor performance of the interposer body layer 101 is prevented from affecting signal transmission of the conductive via 200.

In some embodiments, after forming the capacitor trench 900, before forming the capacitor 300 in the capacitor trench 900, further comprising: an insulating material is deposited in the capacitor trench 900, which may be the same material as the dielectric layer 102, such that at least a portion of the dielectric layer 102 is distributed between the capacitor 300 and the interposer body layer 101. Thus, the electrical isolation between the capacitor 300 and the interposer body layer 101 can be ensured, and the semiconductor performance of the interposer body layer 101 is prevented from affecting the signal storage of the capacitor 300.

The capacitor 900 and the conductive via 200 may have a plurality of trenches, so that the capacitor 300 and the conductive via 200 may be manufactured in a plurality. The plurality of capacitors 300 and the plurality of conductive vias 200 are spaced apart in the interposer 100 in a direction perpendicular to the first side 100a to the second side 100 b. Thus, the signal transmission function of the semiconductor packaging structure can be realized, and meanwhile, noise in the circuit of the conductive through hole 200 in the semiconductor packaging structure is restrained, so that the packaging effect is optimized.

S203: a capacitor is formed in the capacitor trench. Specifically, forming the capacitor 300 in the capacitor trench includes:

S2031: and forming a second electrode layer, wherein the second electrode layer is positioned in the capacitor groove, and a first groove is formed in the second electrode layer.

S2032: and forming a capacitance dielectric layer, wherein the capacitance dielectric layer is positioned in the first groove, and a second groove is formed in the capacitance dielectric layer.

It should be noted that, referring to fig. 7, the second electrode layer 303 and the capacitor dielectric layer 302 may be formed by deposition, and have a certain thickness, but do not fill the capacitor trench 900. The materials of the two are described in the above embodiments, and are not described here again.

S2033: and forming a first electrode layer, wherein the first electrode layer is positioned in the second groove, and the first electrode layer, the capacitance medium layer and the second electrode layer jointly form a capacitance. Referring to fig. 8, the first electrode layer 301 may be formed by deposition to fill the second trench 901 formed by the capacitor dielectric layer 302.

Specifically, after forming the capacitor, the method further comprises:

S204: the top of the conductive via, the top of the capacitor, and the top of the interposer are planarized such that the top of the conductive via, the top of the capacitor, and the top of the interposer are flush, the top of the interposer forming the first side. Referring to fig. 9, the planarization process may be performed by a CMP (CHEMICAL MECHANICAL Polishing) process, and the capacitor 300 and the interposer 100, which are higher than the top surface of the conductive via 200, are processed along the top of the conductive via 200, so that the top surface of the conductive via 200, the top surface of the capacitor 300, and the top surface of the interposer 100 are flush. In this way, losses to the conductive via 200 and the capacitor 300 during the process may also be reduced.

S205: and forming a first conductive structure and a third conductive structure, wherein the first conductive structure is connected with the first electrode layer, the third conductive structure is connected with the top of the conductive through hole, and the first conductive structure and the third conductive structure are made of the same material.

It should be noted that, because the top surface of the conductive via 200 is flush with the top surface of the capacitor 300, the first conductive structure 400 may be formed in the same process to electrically lead out the first conductive layer of the capacitor 300 near the first surface 100a, and the third conductive structure 600 may be formed to electrically lead out the end of the conductive via 200 near the first surface 100a, thereby simplifying the process of the semiconductor package structure.

Referring to fig. 10, after forming the first conductive structure 400 and the third conductive structure 600, forming a multi-layer dielectric layer 908 may further include forming a barrier etch layer between two adjacent dielectric layers 908, where one barrier etch layer is located on the first side 100a (i.e., the top side) of the interposer 100. One or more layers of sixth conductive structures 905 are formed in the multi-layer dielectric layer 908 by etching and deposition, and signals of the first conductive structure 400 and the third conductive structure 600 are transmitted to elements outside the semiconductor package structure through the sixth conductive structures 905, which may be a subsequent process BEOL (Back End of Line) after forming the conductive vias 200 and the capacitors 300.

Specifically, after forming the first conductive structure 400 and the third conductive structure 600, the method further includes:

s206: processing the bottom of the interposer to expose the bottom of the conductive via; the bottom surface of the processed interposer forms a second surface. Referring to fig. 11, the Backside via leakage process BVR (Backside VIA REVEAL) may be performed by a CMP process. Because the depth of the capacitor 300 is smaller than the depth of the conductive via 200, the distance between the capacitor 300 and the bottom surface of the interposer 100 is greater than the distance between the conductive via 200 and the bottom surface of the interposer 100, and thus this step can only expose the bottom of the conductive via 200, and not the bottom of the capacitor 300.

S207: a fourth trench is formed in the interposer at the bottom of the capacitor and exposes the second electrode layer of the capacitor. Referring to fig. 12, the fourth trench may be formed by etching.

S208: and forming a second conductive structure which is positioned in the fourth groove and connected with the exposed second electrode layer. The plurality of fourth trenches may be arranged at intervals, and the second conductive structures 500 are disposed in each fourth trench. The fourth grooves may correspond to one capacitor 300 and be connected to the second electrode layer 303 thereof, which may improve the electrical extraction efficiency and stability of the capacitor 300. The interposer 100 at the bottom of the capacitor 300 can protect the second conductive layer from electrical interference with the adjacent conductive via 200. In some embodiments, the direction in which the plurality of fourth grooves are spaced apart may be a direction perpendicular to the first face 100a to the second face 100 b.

S209: and forming a fourth conductive structure which is positioned at the bottom of the intermediate layer and connected with the second conductive structure.

S210: and forming a fifth conductive structure which is positioned at the bottom of the intermediate layer and is connected with the exposed bottom of the conductive through hole. As shown in connection with fig. 1 and 12, both the fourth conductive structure 700 and the fifth conductive structure 800 may be prepared by deposition, the fourth conductive structure 700 may be a redistribution layer, and the fifth conductive structure 800 may be a bump.

In a third aspect, the present disclosure provides a semiconductor device including a first element, a second element, and the above-described semiconductor package structure, the first element and the second element being located on opposite sides of the interposer 100 of the semiconductor package structure in a thickness direction, respectively, and being interconnected by the semiconductor package structure.

The first and second elements in the present disclosure may be chips, circuits, or Memory structures that may include, but are not limited to, dynamic random access Memory (Dynamic Random Access Memory, abbreviated DRAM), static random access Memory (Static Random Access Memory, abbreviated SRAM), flash Memory, electrically erasable programmable read-Only Memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ-Only Memory, EEPROM), phase-change random access Memory (PHASE CHANGE Random Access Memory, PRAM), or magnetoresistive random access Memory (Magnetoresistive Random Access Memory, MRAM). The non-memory device may be a logic device (e.g., a microprocessor, digital signal processor, or microcontroller) or a device similar thereto.

In describing embodiments of the present disclosure, it should be understood that the terms "mounted," "connected," and "coupled" are to be construed broadly, unless otherwise indicated and defined, and may be connected in either a fixed manner, or indirectly, through intermediaries, or may be in communication with each other between two elements or an interaction relationship between the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like refer to an orientation or positional relationship based on that shown in the drawings, merely to facilitate description of the disclosure and simplify description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the disclosure. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless specifically stated otherwise.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the disclosure described herein may be capable of operation in sequences other than those illustrated or described herein, for example. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor packaging structure is characterized by comprising an interposer, a conductive through hole and a capacitor;

Opposite ends of the conductive through hole extend to the first face and the second face respectively; the capacitor comprises a first electrode layer, a capacitor dielectric layer and a second electrode layer which are sequentially stacked; at least part of the first electrode layer is close to the first surface, and the intermediate layer is electrically led out from the first surface through a first conductive structure; at least part of the second electrode layer is close to the second face, and the interposer is electrically led out from the second face through a second conductive structure.

2. The semiconductor package according to claim 1, wherein the capacitor comprises a plurality of capacitors, and the plurality of capacitors are arranged in the interposer at intervals.

3. The semiconductor package according to claim 1, wherein an end of the first electrode layer adjacent to the first face, an end of the conductive via adjacent to the first face, and the first face are flush.

4. A semiconductor package according to any one of claims 1-3, further comprising a third conductive structure, an end of the conductive via adjacent to the first face being connected to the third conductive structure and electrically leading out of the interposer through the third conductive structure;

5. A semiconductor package according to any one of claims 1 to 3, wherein the second electrode layer adjacent to the second face has a space therebetween, the second conductive structure is embedded in the interposer between the second face and the second electrode layer, one end of the second conductive structure is connected to the second electrode layer, and the other end of the second conductive structure is led to the second face.

6. A semiconductor package according to any one of claims 1-3, further comprising a fourth conductive structure located on the second side, the second conductive structure being connected to the fourth conductive structure;

when a plurality of capacitors are arranged, the second electrode layers of the capacitors are connected with the same fourth conductive structure through the second conductive structure; or, the second electrode layers of the capacitors are connected with different fourth conductive structures through the corresponding second conductive structures.

7. A semiconductor package according to any one of claims 1-3, further comprising a fifth conductive structure located on the second side, an end of the conductive via adjacent to the second side being flush with the second side and connected to the fifth conductive structure and electrically leading out of the interposer through the fifth conductive structure.

8. A semiconductor package according to any one of claims 1-3, wherein the interposer comprises an interposer body layer and a dielectric layer, the dielectric layer being disposed adjacent a first side of the interposer, the interposer body layer being disposed adjacent a second side of the interposer;

and, at least a portion of the dielectric layer is disposed between the conductive via and the interposer body layer; and/or at least part of the dielectric layer is distributed between the capacitor and the interposer body layer.

9. A method of fabricating a semiconductor package, comprising:

providing an interposer comprising first and second faces opposite in a thickness direction;

Forming a conductive through hole and a capacitor in the intermediate layer, wherein the conductive through hole and the capacitor are arranged at intervals, opposite ends of the conductive through hole extend to the first surface and the second surface respectively, and the capacitor comprises a first electrode layer, a capacitor medium layer and a second electrode layer which are sequentially stacked; at least part of the first electrode layer is close to the first surface, and the intermediate layer is electrically led out from the first surface through a first conductive structure; at least part of the second electrode layer is close to the second face, and the interposer is electrically led out from the second face through a second conductive structure.

10. The method of manufacturing a semiconductor package according to claim 9, wherein forming the conductive via and the capacitor comprises:

forming the conductive via in the interposer;

Forming a capacitor groove in the intermediate layer, wherein the bottom of the capacitor groove and the bottom of the conductive through hole are respectively provided with a distance from the bottom of the intermediate layer, and the distance between the bottom of the capacitor groove and the bottom of the intermediate layer is larger than the distance between the bottom of the conductive through hole and the bottom of the intermediate layer;

and forming the capacitor in the capacitor groove.

11. The method of manufacturing a semiconductor package according to claim 10, wherein forming the capacitor in the capacitor trench comprises:

And forming a first electrode layer, wherein the first electrode layer is positioned in the second groove, and the first electrode layer, the capacitance medium layer and the second electrode layer jointly form the capacitance.

12. The method of manufacturing a semiconductor package according to claim 11, further comprising, after forming the capacitor:

planarizing the top of the conductive via, the top of the capacitor, and the top of the interposer such that the top of the conductive via, the top of the capacitor, and the top of the interposer are level, the top of the interposer forming the first face;

13. The method of manufacturing a semiconductor package according to claim 12, further comprising, after forming the first conductive structure and the third conductive structure:

Processing the bottom of the interposer to expose the bottom of the conductive via; forming the second surface on the bottom surface of the processed intermediate layer;

forming a fourth trench in the interposer at the bottom of the capacitor and exposing the second electrode layer of the capacitor;

forming a fourth conductive structure, wherein the fourth conductive structure is positioned at the bottom of the intermediate layer and is connected with the second conductive structure;

and forming a fifth conductive structure, wherein the fifth conductive structure is positioned at the bottom of the intermediate layer and is connected with the exposed bottom of the conductive through hole.

14. The method of manufacturing a semiconductor package according to claim 13, wherein a plurality of the capacitors are arranged in the interposer at intervals;

The second electrode layers of the capacitors are connected with the same fourth conductive structure through the second conductive structure; or, the second electrode layers of the capacitors are connected with different fourth conductive structures through the corresponding second conductive structures.

15. The method of any one of claims 9-14, wherein providing the interposer comprises:

forming an intermediate body layer;

Forming a dielectric layer on the interposer body layer, the interposer body layer and the dielectric layer together forming the interposer, the dielectric layer being distributed adjacent to a first side of the interposer, the interposer body layer being distributed adjacent to a second side of the interposer;