CN114256200A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN114256200A CN114256200A CN202111515666.7A CN202111515666A CN114256200A CN 114256200 A CN114256200 A CN 114256200A CN 202111515666 A CN202111515666 A CN 202111515666A CN 114256200 A CN114256200 A CN 114256200A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 238000000034 method Methods 0.000 title claims description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 164
- 239000002184 metal Substances 0.000 claims abstract description 164
- 239000003990 capacitor Substances 0.000 claims abstract description 149
- 239000010410 layer Substances 0.000 claims description 312
- 239000000758 substrate Substances 0.000 claims description 43
- 239000011229 interlayer Substances 0.000 claims description 30
- 238000000137 annealing Methods 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 239000000243 solution Substances 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 238000003860 storage Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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Abstract
The application provides a semiconductor device and a preparation method thereof, relates to the technical field of semiconductors, and is used for solving the technical problems of large integral size and high cost of a chip; the first dielectric layer has at least one trench, the first capacitor structure includes an upper electrode, and the trench exposes at least a portion of the upper electrode; the groove is internally provided with at least two metal layers and at least one second dielectric layer, the metal layers and the second dielectric layers are sequentially and alternately arranged along the depth direction of the groove, and an upper electrode of the first capacitor structure is connected with the metal layer at the bottommost layer in the groove; at least two metal layers and at least one second dielectric layer form at least one second capacitor structure, and the second capacitor structure is connected with the first capacitor structure in parallel. The capacitor of the semiconductor device can be increased, the whole size of the chip is reduced, and cost is reduced.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
CMOS is an abbreviation of Complementary Metal Oxide Semiconductor (CMOS), which refers to a technology for manufacturing large-scale integrated circuit chips or chips manufactured by the technology, and is a readable and writable accessible chip on a computer motherboard, mainly used for storing data.
In the related art, in order to increase the storage capacity of a chip, after a CMOS device of a semiconductor substrate is usually fabricated, a plurality of capacitors such as a Metal-insulator-Metal (MIM) capacitor, a MOS capacitor, and a PIP capacitor are fabricated on the CMOS device, and the plurality of capacitors are arranged on the chip substrate at intervals in a horizontal direction to increase the capacitance of the chip.
However, the above structure leads to an increase in the overall structure of the chip and an increase in cost.
Disclosure of Invention
In view of the above problems, embodiments of the present application provide a semiconductor device and a method for manufacturing the same, which can increase the capacitance of a chip, reduce the overall size of the chip, and thereby reduce the cost.
In order to achieve the above object, the embodiments of the present application provide the following technical solutions:
in a first aspect, an embodiment of the present application provides a semiconductor device, including: the capacitor comprises a substrate, a first capacitor structure arranged on the substrate and a first dielectric layer arranged on the first capacitor structure; the first dielectric layer is provided with at least one groove, the first capacitor structure comprises an upper electrode, and at least part of the upper electrode is exposed out of the groove; the groove is internally provided with at least two metal layers and at least one second dielectric layer, the metal layers and the second dielectric layers are sequentially and alternately arranged along the depth direction of the groove, and an upper electrode of the first capacitor structure is connected with the metal layer at the bottommost layer in the groove; at least two metal layers and at least one second dielectric layer form at least one second capacitor structure, and the second capacitor structure is connected with the first capacitor structure in parallel.
As an optional implementation manner, the first capacitor structure further includes a lower electrode and an interlayer dielectric layer, and the interlayer dielectric layer is disposed between the lower electrode and the upper electrode; the at least two metal layers comprise first metal layers and second metal layers which are alternately arranged from the bottom to the top of the groove in sequence, each first metal layer is interconnected and electrically connected with the upper electrode, and each second metal layer is interconnected and electrically connected with the lower electrode.
As an alternative embodiment, the semiconductor device further comprises a plurality of conductive vias, each of the first metal layers is interconnected by a conductive via and electrically connected to the upper electrode, and each of the second metal layers is interconnected by a conductive via and electrically connected to the lower electrode; and one metal layer is correspondingly connected with one conductive through hole.
As an alternative implementation, each of the conductive vias includes a via and a metal plug filled in the via, and a barrier layer is further disposed between the metal plug and a wall of the via.
In an alternative embodiment, the surface of the lower electrode facing the interlayer dielectric layer has a plurality of first protrusions and first recesses arranged at intervals.
As an alternative embodiment, the lower surface of the upper electrode has a second protrusion and a second recess at positions corresponding to the first recess and the first protrusion, the second recess matches the shape and size of the first protrusion, and the second protrusion matches the shape and size of the first recess.
Compared with the related art, the semiconductor device provided by the embodiment of the application has at least the following advantages:
the semiconductor device provided by the embodiment of the application comprises a substrate, a first capacitor structure arranged on the substrate and a first dielectric layer arranged on the first capacitor structure, at least one groove is arranged on the first medium layer, at least two metal layers and at least one second medium layer are formed in the groove, the metal layers and the second medium layers are sequentially and alternately arranged along the depth direction of the groove, thus, any two adjacent metal layers in the groove and the second dielectric layer between the two adjacent metal layers can jointly form a second capacitor structure, so that at least one second capacitor structure can be formed in the trench, and the trench exposes at least part of the upper electrode in the first capacitor structure, so that the metal layer at the bottommost layer in the groove is connected with the upper electrode exposed out of the groove, and the second capacitor structure and the first capacitor structure are connected in parallel, thereby realizing the purpose of increasing the capacitance; in addition, the at least one second capacitor structure and the first capacitor structure are arranged in a stacking mode along the depth direction of the groove, and the second capacitor structure is embedded in the groove of the first dielectric layer, so that the increase of the whole size of the chip can be avoided, and the cost is reduced.
In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:
providing a substrate;
forming a first capacitor structure on the substrate, the first capacitor structure comprising an upper electrode;
forming a first dielectric layer on the first capacitor structure;
removing part of the first dielectric layer to form at least one groove, wherein the groove exposes the upper electrode of the first capacitor structure;
and forming metal layers and second dielectric layers which are alternately arranged in sequence in the groove, wherein the number of the metal layers is at least two, the number of the second dielectric layers is at least one, and the metal layer at the bottommost layer in the groove is connected with the upper electrode.
As an optional implementation manner, forming the first capacitor structure on the substrate specifically includes:
forming a lower electrode on the substrate;
forming a first mask layer on the lower electrode, and patterning the first mask layer;
removing part of the lower electrode according to the patterned first mask layer, and forming a plurality of first bulges and first depressions which are arranged at intervals on the surface of the lower electrode;
forming an interlayer dielectric layer on the patterned lower electrode;
and forming an upper electrode on the interlayer dielectric layer.
As an optional implementation manner, forming an interlayer dielectric layer on the patterned lower electrode specifically includes:
and annealing the lower electrode at a preset temperature to form an oxide film of the lower electrode on the surface of the lower electrode, wherein the oxide film forms the interlayer dielectric layer.
As an optional implementation manner, removing a portion of the first dielectric layer to form at least one trench, where the trench exposes the upper electrode of the first capacitor structure, specifically including:
forming a second mask layer on the first dielectric layer;
patterning the second mask layer;
and removing part of the first dielectric layer according to the patterned second mask layer to form at least one groove.
The preparation method of the semiconductor device provided by the embodiment of the application has the same beneficial effects as the semiconductor device, and is not repeated herein.
In addition to the technical problems solved by the embodiments of the present application, the technical features constituting the technical solutions, and the advantages brought by the technical features of the technical solutions described above, other technical problems solved by the semiconductor device and the manufacturing method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and advantages brought by the technical features will be further described in detail in the detailed description.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure;
fig. 3 is a process flow diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Reference numerals:
100-a semiconductor device; 110-a substrate; 120-a first capacitive structure;
121-a lower electrode; 1211-a first projection;
122-interlayer dielectric layer; 123-an upper electrode;
130-a first dielectric layer; 131-a trench; 140-a second capacitive structure; 141-a metal layer;
141 a-first metal layer; 141 b-a second metal layer; 142-a second dielectric layer;
150-conductive vias; 151-a barrier layer; 153-metal plugs; 160-conductive layer.
Detailed Description
Before describing the embodiments of the present application, in order to facilitate understanding of the technical solutions of the present application, the basic concepts and terms related to the embodiments of the present application are explained as follows:
the semiconductor fabrication industry is primarily concerned with growing devices, e.g., Complementary Metal Oxide Semiconductor (CMOS) devices, on a wafer (wafer) device side of a silicon substrate. Generally, a double-well CMOS process is adopted to simultaneously manufacture a P-type channel metal oxide semiconductor field effect transistor with a conducting channel as a cavity and an N-type channel with a conducting channel as an electron on a silicon substrate, and the specific steps are as follows: firstly, doping different regions in a silicon substrate to form an N-type silicon substrate taking electrons as majority carriers and a P-type silicon substrate taking holes as majority carriers respectively, then manufacturing shallow trench isolation between the N-type silicon substrate and the P-type silicon substrate, then forming a hole-type doped diffusion region (P-well) and an electron-type doped diffusion region (N-well) on two sides of the shallow trench isolation respectively by using an ion injection method, then sequentially manufacturing a laminated grid consisting of a grid dielectric medium and a metal grid on wafer device surfaces at the positions of the P-well and the N-well respectively, and finally manufacturing a source electrode and a drain electrode in the P-well and the N-well respectively, wherein the source electrode and the drain electrode are positioned on two sides of the laminated grid, forming an N-type channel in the P-well, and forming a P-type channel in the N-well to obtain the CMOS device.
After the CMOS device of the semiconductor substrate is manufactured, a plurality of capacitors such as MIM capacitors, MOS capacitors, PIP capacitors and the like are manufactured on the shallow trench isolation region of the CMOS device, and usually, the plurality of capacitors are arranged at intervals in the horizontal direction on the surface of the CMOS device, and the capacitors are connected in parallel to increase the capacitance of the chip, thereby increasing the storage capacity of the chip, and the number of the specific capacitors is determined according to the size of the storage capacity of the specific product.
However, the larger the number of capacitors integrated on a CMOS device, the larger the area of the semiconductor substrate occupied by the projection on the semiconductor substrate, and accordingly, the larger the overall size of the semiconductor substrate, resulting in a large overall size of the chip, and the larger the size, the more the consumable material, the higher the cost.
To this end, the embodiment of the present application provides a semiconductor device and a method for manufacturing the same, including a substrate, a first capacitor structure disposed on the substrate, and a first dielectric layer disposed on the first capacitor structure, wherein at least one trench is disposed on the first dielectric layer, and at least two metal layers and at least one second dielectric layer are formed in the trench, and the metal layers and the second dielectric layers are sequentially and alternately disposed along a depth direction of the trench, so that any two adjacent metal layers in the trench and the second dielectric layer between the two adjacent metal layers can jointly form a second capacitor structure, thereby forming at least one second capacitor structure in the trench, and the trench exposes at least a portion of an upper electrode in the first capacitor structure, so that the metal layer at the bottom layer in the trench is connected to the exposed upper electrode in the trench, so that the second capacitor structure and the first capacitor structure are connected in parallel, thereby realizing the purpose of increasing the capacitance; in addition, the at least one second capacitor structure and the first capacitor structure are arranged in a stacking mode along the depth direction of the groove, and the second capacitor structure is embedded in the groove of the first dielectric layer, so that the increase of the whole size of the chip can be avoided, and the cost is reduced.
In order to make the aforementioned objects, features and advantages of the embodiments of the present application more comprehensible, embodiments of the present application are described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Example one
Fig. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application; fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure.
Referring to fig. 1, a semiconductor device 100 provided in an embodiment of the present application includes: a substrate 110, a first capacitor structure 120 disposed on the substrate 110, and a first dielectric layer 130 disposed on the first capacitor structure 120.
The substrate 110 may be made of a semiconductor material, and the semiconductor material may be one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound.
The first capacitor structure 120 may include, but is not limited to, a MIM capacitor structure, and the first capacitor structure 120 includes a lower electrode 121, an interlayer dielectric layer 122, and an upper electrode 123; it is understood that the lower electrode 121 refers to an electrode formed on the substrate 110, the upper electrode 123 is an electrode away from the substrate 110, and the interlayer dielectric layer 122 is sandwiched between the lower electrode 121 and the upper electrode 123, wherein both the lower electrode 121 and the upper electrode 123 are made of a conductive material, for example, a conductive material such as aluminum (Al); the interlayer dielectric layer 122 is made of an insulating material, such as alumina.
The first dielectric layer 130 has at least one trench 131, and it is understood that there may be one trench 131 on the first dielectric layer 130, or there may be two or more trenches 131 arranged at intervals, wherein each trench 131 exposes at least a portion of the upper electrode 123 of the first capacitor structure 120.
In addition, at least two metal layers 141 and at least one second dielectric layer 142 are disposed in the trench 131, the metal layers 141 and the second dielectric layers 142 are sequentially and alternately disposed along the depth direction of the trench 131, for example, the metal layers 141, the second dielectric layers 142, and the like are sequentially and alternately stacked and disposed from bottom to top along the depth direction of the trench 131, wherein the metal layer 141 is disposed at the bottommost layer of the trench 131, and the trench 131 exposes the upper electrode 123 of the first capacitor structure 120, so that the metal layer 141 at the bottommost layer in the trench 131 is in contact with the upper electrode 123 of the first capacitor structure 120 exposed by the trench 131.
It is understood that any two adjacent metal layers 141 and the second dielectric layer 142 between two adjacent metal layers may jointly form a second capacitor structure 140, so that at least two metal layers 141 and at least one second dielectric layer 142 may form one second capacitor structure 140 or a plurality of second capacitor structures 140, and the second capacitor structure 140 and the first capacitor structure 120 are connected in parallel; when the number of the second capacitor structures 140 is multiple, the multiple second capacitor structures 140 and the first capacitor structure 120 are all connected in parallel, so that a larger capacitor can be formed, and the storage capacity of the chip can be improved.
Since the second capacitor structures 140 are formed to be integrated in the trenches 131, the integration density of the capacitors can be increased, and thus, the capacitors can be increased while avoiding an increase in the overall size of the chip, thereby avoiding an increase in the chip cost.
It should be noted that two adjacent metal layers 141 refer to two metal layers 141 that are closest to each other, for example, at least two metal layers 141 include a first metal layer a, a second metal layer B, and a third metal layer C, and it is understood that a second dielectric layer 142 is disposed between the first metal layer a and the second metal layer B, and a second dielectric layer 142 is also disposed between the second metal layer B and the third metal layer C, so that the first metal layer a and the second metal layer B are adjacent metal layers, and the second metal layer B and the third metal layer C are also adjacent metal layers, and thus, the first metal layer a, the second metal layer B, and the second dielectric layer 142 located between the first metal layer a and the second metal layer B form a second capacitor structure 140 together; of course, the second metal layer B, the third metal layer C, and the second dielectric layer 142 located between the second metal layer B and the third metal layer C can also form a second capacitor structure 140, and thus, the metal layer 141 can be the upper electrode 123 of one second capacitor structure 140, and can also be the lower electrode 121 of another second capacitor.
In addition, in addition to the second capacitor structure 140 formed by the metal layer 141 and the dielectric layer along the depth direction of the trench 131, the second capacitor structure 140 can also be formed by two adjacent metal layers 141 on the sidewall of the trench 131 and the dielectric layer located between the two adjacent metal layers 141, so that the capacitance of the chip can be further increased, and the storage capacity of the chip can be increased.
The metal layer 141 in the trench 131 is made of a conductive material, and the second dielectric layer 142 is made of an insulating material.
Therefore, in the above scheme, at least one trench 131 is formed on the first dielectric layer 130, at least two metal layers 141 and at least one second dielectric layer 142 are formed in the trench 131, and the metal layers 141 and the second dielectric layers 142 are sequentially and alternately arranged along the depth direction of the trench 131, so that any two adjacent metal layers 141 in the trench 131 and the second dielectric layer 142 between two adjacent metal layers 141 can jointly form one second capacitor structure 140, so that at least one second capacitor structure 140 can be formed in the trench 131, and the trench 131 exposes at least part of the upper electrode 123 in the first capacitor structure 120, so that the metal layer 141 at the bottommost layer in the trench 131 is connected with the upper electrode 123 exposed in the trench 131, so that the second capacitor structure 140 and the first capacitor structure 120 are connected in parallel, thereby increasing the capacitance; in addition, since at least one second capacitor structure 140 and the first capacitor structure 120 are stacked along the depth direction of the trench 131, and the second capacitor structure 140 is embedded in the trench 131 of the first dielectric layer 130, the increase of the overall size of the chip can be avoided, thereby reducing the cost.
In one embodiment, the at least two metal layers 141 may include a first metal layer 141a and a second metal layer 141b alternately arranged in sequence from the bottom to the top of the trench 131, and it is understood that the first metal layer 141a may be an odd number layer, and the second metal layer 141b may be an even number layer, for example, the first metal layer 141a is 1, 3, 5, and 7 … layers, and the second metal layer 141b is 2, 4, 6, and 8 … layers, and a second dielectric layer 142 is disposed between the adjacent first metal layer 141a and the adjacent second metal layer 141b, that is, the metal layer 141 and the second dielectric layer 142 in the trench 131 are arranged from the bottom to the bottom of the trench 131: the first metal layer 141a, the second dielectric layer 142, the second metal layer 141b, the second dielectric layer 142, the first metal layer 141a, the second dielectric layer 142, the second metal layer 141b, and the like, such that the adjacent first metal layer 141a, the second metal layer 141b, and the second dielectric layer 142 between the first metal layer 141a and the second metal layer 141b together form a second capacitor structure 140.
It can be understood that the first metal layers 141a are connected to each other and to the upper electrode 123 of the first capacitor structure 120, and the second metal layers 141b are connected to each other and to the lower electrode 121 of the first capacitor structure 120, so that the second capacitor structures 140 formed in the trenches 131 are connected in parallel to each other and to the first capacitor structure 120, and thus the capacitance of the chip is increased, and the storage capacity of the chip is increased.
As an alternative embodiment, the semiconductor device 100 further includes a plurality of conductive vias 150, each of the first metal layers 141a is interconnected and electrically connected to the upper electrode 123 of the first capacitor structure 120 by a respective one of the conductive vias 150, and each of the second metal layers 141b is also interconnected and electrically connected to the lower electrode 121 of the first capacitor structure 120 by a respective one of the conductive vias 150, it being understood that one of the metal layers 141 is correspondingly connected to one of the conductive vias 150.
That is, each first metal layer 141a is electrically connected to each first metal layer 141a through the conductive via 150, and each first metal layer 141a is electrically connected to the upper electrode 123 of the first capacitor structure 120 through the conductive via 150; the second metal layers 141b are electrically connected to each other through the conductive vias 150, and the second metal layers 141b are electrically connected to the lower electrode 121 of the first capacitor structure 120 through the conductive vias 150, so that the second capacitor structures 140 are connected in parallel to the first capacitor structure 120, thereby increasing the capacitance of the chip, reducing the overall size of the chip, and reducing the cost.
It is understood that the conductive via 150 includes a via disposed on the first dielectric layer 130 and a metal plug 153 filled in the via, wherein the metal plug 153 is made of a conductive material, for example, the metal plug 153 may be made of tungsten (W); in addition, a barrier layer 151 is further disposed between the wall of the through hole and the metal plug 153, for example, the barrier layer 151 may be a titanium nitride layer to prevent diffusion of metal to the surroundings.
It should be noted that the conductive via 150 is electrically connected to the metal layers 141 at a planar position, that is, each metal layer 141 and the upper electrode 123 and the lower electrode 121 of the first capacitor structure 120 are respectively led out from the upper surface of the semiconductor device 100 through the corresponding conductive via 150, and a conductive layer 160 is disposed on the surface, and the first metal layers 141a in the trench 131 are interconnected and electrically connected to the upper electrode 123 of the first capacitor structure 120 through the conductive layer 160, and the second metal layers 141b in the trench 131 are interconnected and electrically connected to the lower electrode 121 of the first capacitor structure 120, so that the second capacitor structures 140 and the first capacitor structure 120 formed in the trench 131 are connected in parallel, thereby increasing the capacitance of the semiconductor device 100, reducing the overall size of the chip, and reducing the cost.
In addition, as shown in fig. 2, the surface of the lower electrode 121 of the first capacitor structure 120 facing the interlayer dielectric layer 122 may have a plurality of first protrusions 1211 and first recesses arranged at intervals, so that the surface area of the lower electrode 121 may be increased, thereby increasing the capacitance of the first capacitor structure 120.
When the surface of the lower electrode 121 of the first capacitor structure 120 has a plurality of first protrusions 1211 and a plurality of first recesses, the first protrusions 1211 may have the same shape and size, or may have different shapes and sizes, for example, the first protrusions 1211 may be a crystal grain formed on the surface of the lower electrode 121, such as a truncated pyramid, a truncated cone, a pyramid, or a column; of course, the sizes of the first recesses may be the same or different, and this embodiment is not limited in particular.
Alternatively, protrusions and depressions may be formed on the surface of the upper electrode 123 facing the lower electrode 121 to increase the surface area of the upper electrode 123, thereby increasing the capacitance of the first capacitor structure 120.
Illustratively, the surface of the lower electrode 121 facing the interlayer dielectric layer 122 is provided with a plurality of first protrusions 1211 and first recesses, and the surface of the upper electrode 123 facing the lower electrode 121 is provided with a plurality of second protrusions and second recesses, so that the capacitance of the first capacitor structure 120 can be further increased.
It should be noted that the second recess and the second protrusion on the upper electrode 123 correspond to the first protrusion 1211 and the first recess on the lower electrode 121, that is, the second recess corresponds to the first protrusion 1211, the second protrusion corresponds to the first recess, the shape and size of the second recess match the shape and size of the first protrusion 1211, and the shape and size of the second protrusion matches the shape and size of the first recess.
Example two
Fig. 3 is a process flow diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in fig. 3, an embodiment of the present application further provides a method for manufacturing a semiconductor device, and it can be understood that the method for manufacturing a semiconductor device provided in the embodiment of the present application is used for manufacturing the semiconductor device of the first embodiment, and the method for manufacturing a semiconductor device specifically includes the following steps:
step S101: a substrate is provided.
Step S102: a first capacitor structure is formed on the substrate, the first capacitor structure including an upper electrode.
Step S103: a first dielectric layer is formed over the first capacitor structure.
Step S104: and removing part of the first dielectric layer to form at least one groove, wherein the groove exposes the upper electrode of the first capacitor structure.
Step S105: and forming metal layers and second dielectric layers which are alternately arranged in sequence in the groove, wherein the number of the metal layers is at least two, the number of the second dielectric layers is at least one, and the metal layer at the bottommost layer in the groove is connected with the upper electrode 123.
In the embodiment of the present application, as shown in fig. 1, at least one trench 131 is formed on the first dielectric layer 130 by removing a portion of the first dielectric layer 130, the trench 131 exposes the upper electrode 123 of the first capacitor structure 120, and a metal layer 141 is formed in the trench 131 by deposition or the like, the metal layer 141 is partially connected to the upper electrode 123 of the first capacitor structure 120 by contact, a second dielectric layer 142 is formed on the metal layer 141 by deposition, a metal layer 141 is further formed on the second dielectric layer 142, at least two metal layers 141 and at least one second dielectric layer 142 are sequentially formed, where the metal layers 141 and the second dielectric layers 142 are alternately arranged, so that any two adjacent metal layers 141 in the trench 131 and the second dielectric layer 142 between two adjacent metal layers 141 can jointly form a second capacitor structure 140, so that at least one second capacitor structure 140 can be formed in the trench 131, the second capacitor structure 140 and the first capacitor structure 120 are connected in parallel, so that the purpose of increasing the capacitance is achieved; in addition, since at least one second capacitor structure 140 and the first capacitor structure 120 are stacked along the depth direction of the trench 131, and the second capacitor structure 140 is embedded in the trench 131 of the first dielectric layer 130, the increase of the overall size of the chip can be avoided, thereby reducing the cost.
In the embodiment of the present application, the specific steps of forming the first capacitor structure 120 on the substrate 110 include:
first, the lower electrode 121 is formed on the substrate 110.
In the present embodiment, the substrate 110 may be a silicon substrate 110, and a layer of metallic aluminum may be deposited on the surface of the silicon substrate 110 by an atomic layer deposition process. Of course, other metal conductive layers may also be deposited on the silicon substrate 110.
Next, a first mask layer is formed on the lower electrode 121, and the first mask layer is patterned.
The first mask layer may be a photoresist and the photoresist layer is patterned.
According to the patterned first mask layer, a portion of the lower electrode 121 is removed, and a plurality of first protrusions 1211 and first recesses are formed on a surface of the lower electrode 121 at intervals, as shown in fig. 2.
Part of the metal aluminum can be removed by wet etching to form an uneven surface on the surface of the metal aluminum, and then the surface of the metal aluminum layer can be crystallized by annealing at a preset temperature to form large-grained aluminum crystals, so that the unevenness of the surface of the metal aluminum layer can be larger, and a plurality of first protrusions 1211 and first recesses are formed on the surface of the metal aluminum layer to form the lower electrode 121 of the first capacitor structure 120, so that the capacitance of the first capacitor structure 120 can be increased to increase the storage capacity of the chip.
An interlayer dielectric layer 122 is formed on the patterned lower electrode 121.
In this embodiment, a dense aluminum oxide film may be formed on the surface of the lower electrode 121 by annealing at a predetermined temperature, and the aluminum oxide film forms the interlayer dielectric layer 122, and of course, the interlayer dielectric layer 122 may also be made of other materials formed by other methods, which is not limited in this embodiment.
Since the surface of the lower electrode 121 facing the interlayer dielectric layer 122 is an uneven surface, and the interlayer dielectric layer 122 is an aluminum oxide layer formed on the lower electrode 121 by annealing at a predetermined temperature, the interlayer dielectric layer 122 also forms an uneven structure matching the first protrusion 1211 and the first recess on the lower electrode 121.
It is understood that, in the above-mentioned scheme, annealing at a predetermined temperature refers to annealing at 700 ℃ to 1200 ℃, for example, annealing at 700 ℃, 800 ℃, 900 ℃, 1000 ℃, 1050 ℃, 1100 ℃, 1200 ℃ and the like may be performed, and is determined according to actual requirements, and the embodiments of the present application are not limited thereto.
Finally, an upper electrode 123 is formed on the interlayer dielectric layer 122.
It is understood that after the interlayer dielectric layer 122 with the uneven surface is formed on the lower electrode 121, the upper electrode 123 may be formed on the interlayer dielectric layer 122 by deposition, so that at least the surface of the upper electrode 123 facing the interlayer dielectric layer 122 is also the uneven surface, thereby increasing the area of the surface of the upper electrode 123 facing the interlayer dielectric layer 122, and further increasing the capacitance of the first capacitor structure 120.
After the upper electrode 123 of the first capacitor structure 120 is formed, a first dielectric layer 130 is deposited on the upper electrode 123 of the first capacitor structure 120, and the surface of the first dielectric layer 130 is planarized, for example, the surface of the first dielectric layer 130 can be planarized by Chemical Mechanical Polishing (CMP), and then a second mask layer is formed on the first dielectric layer 130, the second mask layer is patterned, a portion of the first dielectric layer 130 is removed according to the patterned second mask layer, at least one trench 131 is formed, and the trench 131 exposes the upper electrode 123 of the first capacitor structure 120.
Then, a metal layer 141 and a second dielectric layer 142 are sequentially deposited in the trench 131 to form a stacked structure in which the metal layer 141 and the second dielectric layer 142 are alternately disposed.
On the basis of the above embodiment, a third mask layer may be formed on the top metal layer 141, and the third mask layer is patterned, then each metal layer 141 is etched by a gas of etching metal such as hydrogen chloride or hydrogen bromide, each second dielectric layer 142 is etched by a carbon fluoride-based etching gas, so that each metal layer 141 is exposed, it can be understood that the region where the bottom metal layer 141 is exposed is on the outermost side of the upper surface of the trench 131, and sequentially approaches to the central region of the upper surface of the trench 131, then the third dielectric layer is deposited and planarized, then a plurality of through holes are formed by etching according to the above pattern, each through hole respectively stops on the corresponding metal layer 141 and the upper and lower electrodes 121 of the first capacitor structure 120, then the diffusion barrier layer 151 and the metal plug 153 (e.g. metal tungsten) are deposited in each through hole, the barrier layer 151 and the metal plug 153 form the conductive through hole 150, therefore, each metal layer 141 and the upper electrode 123 and the lower electrode 121 of the first capacitor structure 120 are respectively led out on the upper surface of the semiconductor device 100 through the corresponding conductive through hole 150, a conductive layer 160 is deposited on the surface, the conductive layer 160 is patterned, the first metal layers 141a in the trench 131 are interconnected and electrically connected with the upper electrode 123 of the first capacitor structure 120, the second metal layers 141b in the trench 131 are interconnected and electrically connected with the lower electrode 121 of the first capacitor structure 120, and the second capacitor structures 140 and the first capacitor structure 120 formed in the trench 131 are connected in parallel, so that the capacitance of the semiconductor device 100 is increased, the overall size of a chip is reduced, and the cost is reduced.
It is understood that the first dielectric layer 130, the second dielectric layer 142 and the third dielectric layer can be made of insulating materials, such as aluminum oxide, silicon nitride, etc.
The embodiments or implementation modes in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
In the description herein, references to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A semiconductor device, comprising: the capacitor comprises a substrate, a first capacitor structure arranged on the substrate and a first dielectric layer arranged on the first capacitor structure; the first dielectric layer is provided with at least one groove, the first capacitor structure comprises an upper electrode, and at least part of the upper electrode is exposed out of the groove;
the groove is internally provided with at least two metal layers and at least one second dielectric layer, the metal layers and the second dielectric layers are sequentially and alternately arranged along the depth direction of the groove, and an upper electrode of the first capacitor structure is connected with the metal layer at the bottommost layer in the groove;
at least two metal layers and at least one second dielectric layer form at least one second capacitor structure, and the second capacitor structure is connected with the first capacitor structure in parallel.
2. The semiconductor device according to claim 1, wherein the first capacitance structure further comprises a lower electrode and an interlayer dielectric layer disposed between the lower electrode and the upper electrode;
the at least two metal layers comprise first metal layers and second metal layers which are alternately arranged from the bottom to the top of the groove in sequence, each first metal layer is interconnected and electrically connected with the upper electrode, and each second metal layer is interconnected and electrically connected with the lower electrode.
3. The semiconductor device of claim 2, further comprising a plurality of conductive vias, each of the first metal layers being interconnected by the conductive vias and electrically connected to the upper electrode, each of the second metal layers being interconnected by the conductive vias and electrically connected to the lower electrode; and one metal layer is correspondingly connected with one conductive through hole.
4. The semiconductor device according to claim 3, wherein each conductive via comprises a via and a metal plug filled in the via, and a barrier layer is further disposed between the metal plug and a wall of the via.
5. The semiconductor device according to any one of claims 2 to 4, wherein a surface of the lower electrode facing the interlayer dielectric layer has a plurality of first protrusions and first recesses arranged at intervals.
6. The semiconductor device according to claim 5, wherein a lower surface of the upper electrode has a second protrusion and a second recess at positions corresponding to the first recess and the first protrusion, the second recess matching a shape and a size of the first protrusion, and the second protrusion matching a shape and a size of the first recess.
7. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first capacitor structure on the substrate, the first capacitor structure comprising an upper electrode;
forming a first dielectric layer on the first capacitor structure;
removing part of the first dielectric layer to form at least one groove, wherein the groove exposes the upper electrode of the first capacitor structure;
and forming metal layers and second dielectric layers which are alternately arranged in sequence in the groove, wherein the number of the metal layers is at least two, the number of the second dielectric layers is at least one, and the metal layer at the bottommost layer in the groove is connected with the upper electrode.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the forming of the first capacitor structure on the substrate specifically includes:
forming the lower electrode on the substrate;
forming a first mask layer on the lower electrode, and patterning the first mask layer;
removing part of the lower electrode according to the patterned first mask layer, and forming a plurality of first bulges and first depressions which are arranged at intervals on the surface of the lower electrode;
forming an interlayer dielectric layer on the patterned lower electrode;
and forming an upper electrode on the interlayer dielectric layer.
9. The method of claim 8, wherein forming an interlayer dielectric layer on the patterned lower electrode comprises:
and annealing the lower electrode at a preset temperature to form an oxide film of the lower electrode on the surface of the lower electrode, wherein the oxide film forms the interlayer dielectric layer.
10. The method for manufacturing a semiconductor device according to claim 7, wherein removing a portion of the first dielectric layer to form at least one trench, the trench exposing the upper electrode of the first capacitor structure, specifically comprises:
forming a second mask layer on the first dielectric layer;
patterning the second mask layer;
and removing part of the first dielectric layer according to the patterned second mask layer to form at least one groove.
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| CN202111515666.7A CN114256200A (en) | 2021-12-13 | 2021-12-13 | Semiconductor device and method for manufacturing the same |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115472590A (en) * | 2022-09-16 | 2022-12-13 | 西安紫光国芯半导体有限公司 | Chip and electronic device |
| CN117059621A (en) * | 2023-10-08 | 2023-11-14 | 荣耀终端有限公司 | Chip, preparation method thereof and electronic equipment |
| WO2024093153A1 (en) * | 2022-11-04 | 2024-05-10 | 长鑫存储技术有限公司 | Semiconductor package structure and manufacturing method therefor |
| WO2024169193A1 (en) * | 2023-02-14 | 2024-08-22 | 华为技术有限公司 | Capacitor, storage array, memory, and electronic device |
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2021
- 2021-12-13 CN CN202111515666.7A patent/CN114256200A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115472590A (en) * | 2022-09-16 | 2022-12-13 | 西安紫光国芯半导体有限公司 | Chip and electronic device |
| WO2024093153A1 (en) * | 2022-11-04 | 2024-05-10 | 长鑫存储技术有限公司 | Semiconductor package structure and manufacturing method therefor |
| WO2024169193A1 (en) * | 2023-02-14 | 2024-08-22 | 华为技术有限公司 | Capacitor, storage array, memory, and electronic device |
| CN117059621A (en) * | 2023-10-08 | 2023-11-14 | 荣耀终端有限公司 | Chip, preparation method thereof and electronic equipment |
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