CN106340488A - Preparation method of copper interconnection structure - Google Patents
Preparation method of copper interconnection structure Download PDFInfo
- Publication number
- CN106340488A CN106340488A CN201611089586.9A CN201611089586A CN106340488A CN 106340488 A CN106340488 A CN 106340488A CN 201611089586 A CN201611089586 A CN 201611089586A CN 106340488 A CN106340488 A CN 106340488A
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- Prior art keywords
- metal level
- cobalt metal
- hole
- preparation
- interconnection structure
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Abstract
The invention provides a preparation method of a copper interconnection structure. The preparation method comprises the steps that a semiconductor substrate is provided, wherein the surface of the semiconductor substrate is provided with a low-k dielectric layer and copper interconnection wires located in the low-k dielectric layer; a first cobalt metal layer is formed on the copper interconnection wires; an interlayer medium layer is formed on the first cobalt metal layer and the low-k dielectric layer; the interlayer medium layer is etched to form a through hole exposing the first cobalt metal layer and a groove which is located over the through hole and communicated with the through hole; a second cobalt metal layer is formed on the bottom wall of the through hole; blocking layers are formed in the through hole and formed on the bottom wall and the side wall of the groove, and the metal layers are filled up. According to the preparation method of the copper interconnection structure, the adhesive force between the blocking layers and the copper interconnection wires can be enhanced, then the connection property of the copper interconnection structure is improved, and the electron migration capability is improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, more particularly, to a kind of preparation side of copper interconnection structure
Method.
Background technology
With the development of semiconductor technology, the integrated level of VLSI chip has been up to several hundred million or even tens
The scale of hundred million devices, multiple layer metal interconnection technique more than two-layer widely uses.Metal interconnecting layer includes metal interconnection structure
(metal interconnection structure includes metal interconnecting wires and metal plug) and interlayer dielectric layer (inter-layer dielectric,
ild).The manufacture method of metal interconnecting layer is typically included in interlayer dielectric layer manufacture groove (trench) and through hole (via), then
Deposited metal in above-mentioned groove and through hole, the metal of deposition forms described metal interconnection structure.Because copper has preferable conduction
Property filling capacity, generally select copper as metal interconnecting wires material, from silicon oxide as inter-level dielectric layer material.
In prior art, during groove and through hole deposited metal, first in side wall and the diapire shape of groove and through hole
Become barrier layer, refill copper metal, barrier layer prevents copper metal layer from spreading in interlayer dielectric layer.However, barrier layer and lower floor
Copper metal line be difficult to bond well, impact copper interconnection structure in electron transfer performance.
Content of the invention
It is an object of the invention to provide the preparation method of copper interconnection structure, solve barrier layer and copper metal in prior art
Between bond bad impact electron transfer technical problem.
For solving above-mentioned technical problem, the present invention provides a kind of preparation method of metal gates, comprising:
There is provided Semiconductor substrate, described semiconductor substrate surface has low k dielectric and is located in described low k dielectric
Copper interconnecting line；
First cobalt metal level is formed on described copper interconnecting line；
Interlayer dielectric layer is formed on described first cobalt metal level and described low k dielectric；
Etch described interlayer dielectric layer, form the through hole exposing described first cobalt metal level and be located on described through hole and
The groove connecting with described through hole；
Form the second cobalt metal level in the diapire of described through hole；
Form barrier layer in the diapire of described through hole and described groove and side wall, and fill out in described through hole and described groove
Fill copper metal layer.
Optionally, form described through hole and the step of described groove include:
The photoresistance of hard mask layer and patterning is formed on described interlayer dielectric layer；
Hard mask layer described in the photoresistance of described patterning as mask etching and described interlayer dielectric layer, expose described
One cobalt metal level, forms described through hole；
Remove the photoresistance of described patterning, the photoresistance of another patterning is formed on described hard mask layer；
Interlayer dielectric layer described in the photoresistance of this another patterning as mask etching, forms described groove；
Remove the photoresistance of this another patterning.
Optionally, also include: etch at least part of first cobalt metal level.
Optionally, described second cobalt metal level is formed in the diapire of described through hole using physical gas-phase deposition, described
The thickness of the second cobalt metal level is
Optionally, also include: be etched back to the described hard mask layer around described groove using wet-etching technology.
Optionally, the width being etched back to described hard mask layer is
Optionally, also include: the 3rd cobalt metal level is formed on described metal level.
Optionally, the thickness of described 3rd cobalt metal level is
Optionally, described first cobalt metal level selects ratio with the deposition in described low-k dielectric layer on described copper interconnecting line
More than 20.
Optionally, the material on described barrier layer is titanium nitride, and the thickness on described barrier layer is
Compared with prior art, in the preparation method of copper interconnection structure that the present invention provides, copper interconnecting line forms the
One cobalt metal level, after etching through hole and groove, forms the second cobalt metal level in the diapire of through hole, the second cobalt metal level can be repaiied
Again due to etching the damage of the first cobalt metal level causing so that barrier layer can form good bonding with cobalt metal level, from
And improve the switching performance between copper interconnecting line and copper metal layer, improve electron transfer capabilities.
Brief description
Fig. 1 is the flow chart of copper interconnection structure preparation method in one embodiment of the invention；
Fig. 2 is the structural representation forming copper interconnecting line in one embodiment of the invention；
Fig. 3 is the structural representation forming the first cobalt metal level in one embodiment of the invention；
Fig. 4 is the structural representation forming through hole and groove in one embodiment of the invention；
Fig. 5 is the structural representation forming the second cobalt metal level in one embodiment of the invention；
Fig. 6 is the structural representation forming barrier layer and copper metal layer in one embodiment of the invention；
Fig. 7 is the structural representation forming the 3rd cobalt metal level in one embodiment of the invention.
Specific embodiment
Preparation method below in conjunction with the copper interconnection structure to the present invention for the schematic diagram is described in more detail, wherein table
Show the preferred embodiments of the present invention it should be appreciated that those skilled in the art can change invention described herein, and still
Realize the advantageous effects of the present invention.Therefore, description below be appreciated that widely known for those skilled in the art, and
It is not intended as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
It is necessary to make a large amount of implementation details to realize the specific objective of developer in sending out, such as according to relevant system or relevant business
Limit, another embodiment is changed into by an embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only routine work to those skilled in the art.
Referring to the drawings the present invention more particularly described below by way of example in the following passage.Will according to following explanation and right
Seek book, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is all in the form of very simplification and all using non-
Accurately ratio, only in order to purpose that is convenient, lucidly aiding in illustrating the embodiment of the present invention.
The core concept of the present invention is, forms the first cobalt metal level on copper interconnecting line, after etching through hole and groove,
Form the second cobalt metal level in the diapire of through hole, the second cobalt metal level can be repaired due to etching the first cobalt metal level causing
Damage so that barrier layer can form good bonding with cobalt metal level, thus improving between copper interconnecting line and copper metal layer
Switching performance, improves electron transfer capabilities.
Preparation method below in conjunction with the copper interconnection structure to the present invention for the accompanying drawing is described in detail, and Fig. 1 ties for copper-connection
The flow chart of body plan Preparation Method, Fig. 2～Fig. 7 is the corresponding structural representation of each step, specifically, the preparation side of copper interconnection structure
Method comprises the steps:
First, execution step s1, with reference to shown in Fig. 2, provides Semiconductor substrate 100, described Semiconductor substrate 100 can be
The substrat structures known in those skilled in the art such as silicon substrate, germanium silicon substrate, carbon silicon substrate, soi substrate.And, described half
Conductor substrate 100 surface has the copper interconnecting line 120 that low k dielectric 110 is located in described low k dielectric 110.It should be understood that
It is to could be formed with device architecture (not shown), such as amplifier, D/A converter, mould in Semiconductor substrate 100
Intend process circuit and/or digital processing circuit, interface circuit etc., the method forming these device architectures can be all cmos work
Skill.Wherein, copper interconnecting line more than 120 device architecture is electrically connected with, for example, can pass through connector (not shown) and device architecture
It is electrically connected with, its specific structure needs to be determined according to practical situation.
Then, execution step s2, with reference to shown in Fig. 3, forms the first cobalt metal level 131 on described copper interconnecting line 120, the
One cobalt metal level 131 is used for improving the bonding force of copper interconnecting line 120 and barrier layer.In the present embodiment, due to the low k dielectric adopting
Layer be ultra-low k dielectric layer, for example, k be 0.8～1.5 so that described first cobalt metal level 131 on described copper interconnecting line 120 with
Deposition in described low-k dielectric layer 110 selects ratio more than 20, thus cobalt metal is only on copper interconnecting line 120, and is not situated between in low k
Deposit on matter layer, and in this step, do not need to be formed mask in low-k dielectric layer.
Execution step s3, with continued reference to shown in Fig. 3, on described first cobalt metal level 131 and described low k dielectric 110
Form interlayer dielectric layer 140, in the present embodiment, described interlayer dielectric layer can be formed using chemical vapor deposition method, described
Interlayer dielectric layer 140 is silica material.
Afterwards, execution step s4, with reference to shown in Fig. 4, etches described interlayer dielectric layer 140, is formed and expose described first
The through hole 151 of cobalt metal level 131 and the groove 152 being located on described through hole 151 and connecting with described through hole 151.In the present invention,
Described through hole 151 and described groove 152 are formed using dual damascene process, specifically include following steps:
First, the photoresistance of hard mask layer and patterning is formed on described interlayer dielectric layer 140；
Then, described in the photoresistance of described patterning as mask etching, hard mask layer and described interlayer dielectric layer, expose
Described first cobalt metal level 131, forms described through hole 151.In the present invention, through hole is formed using dry etch process, and should
Etch step can also include etching at least part of first cobalt metal level, and exposes at least part of copper interconnecting line 120, leads to
There is etching injury in one cobalt metal level 131.
Secondly, remove the photoresistance of described patterning, the photoresistance of another patterning is formed on described hard mask layer；
Again, interlayer dielectric layer 140 described in the photoresistance of this another patterning as mask etching, forms described groove 152；
Afterwards, remove the photoresistance of this another patterning.
Certainly, in the other embodiment of the present invention, can also adopt and be formed by other methods described through hole and described groove, this
Invention not limits to this.Additionally, after etching forms through hole 151 and groove 152, for the ease of the filling of subsequent metal, this
The described hard mask layer that can also be etched back to around described groove 152 using wet-etching technology in embodiment, increases groove 152
The opening at top, and, be etched back to the width of described hard mask layer and be
Execution step s5, with reference to shown in Fig. 5, forms the using physical gas-phase deposition in the diapire of described through hole 151
Two cobalt metal levels 132, and the thickness of described second cobalt metal level 132 isIt should be noted that the second cobalt metal level 132
The damage due to etching the first cobalt metal level 131 causing can be repaired.
Again, execution step s6, with reference to shown in Fig. 6, in the diapire of described through hole 151 and side wall and described groove 152
Diapire and side wall form barrier layer 160, and fill copper metal layer 170 in described through hole and described groove.In the present embodiment, institute
The material stating barrier layer 160 is titanium nitride, and the thickness on described barrier layer 160 isIn the present embodiment, barrier layer 160
Good bonding can be formed with 132 phase of the second cobalt metal level the first cobalt metal level 131, thus improving copper interconnecting line 120 and copper
Switching performance between metal level 170, improves electron transfer capabilities.
With reference to shown in Fig. 7, in order to further improve the switching performance of copper interconnection structure in the present invention, in the present embodiment
Also include: the 3rd cobalt metal level 133 is formed on described metal level 170, the thickness of described 3rd cobalt metal level 133 isImprove the switching performance between copper metal layer 170 and upper strata copper interconnection structure, improve the ability of electron transfer.
In sum, the present invention provides a kind of preparation method of copper interconnection structure, forms the first cobalt gold on copper interconnecting line
Belong to layer, after etching through hole and groove, through hole diapire formed the second cobalt metal level, the second cobalt metal level can repair due to
The damage etching the first cobalt metal level causing is so that barrier layer can form good bonding with cobalt metal level, thus improving
Switching performance between copper interconnecting line and copper metal layer, improves electron transfer capabilities.
Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprise these changes and modification.
Claims (10)
1. a kind of preparation method of copper interconnection structure is it is characterised in that include:
There is provided Semiconductor substrate, the copper that described semiconductor substrate surface has low k dielectric and is located in described low k dielectric is mutual
Line；
First cobalt metal level is formed on described copper interconnecting line；
Interlayer dielectric layer is formed on described first cobalt metal level and described low k dielectric；
Etch described interlayer dielectric layer, form the through hole exposing described first cobalt metal level and be located on described through hole and with institute
State the groove of through hole connection；
Form the second cobalt metal level in the diapire of described through hole；
Form barrier layer in the diapire of described through hole and described groove and side wall, and fill copper in described through hole and described groove
Metal level.
2. the preparation method of copper interconnection structure as claimed in claim 1 is it is characterised in that form described through hole and described groove
Step include:
The photoresistance of hard mask layer and patterning is formed on described interlayer dielectric layer；
Hard mask layer described in the photoresistance of described patterning as mask etching and described interlayer dielectric layer, expose described first cobalt
Metal level, forms described through hole；
Remove the photoresistance of described patterning, the photoresistance of another patterning is formed on described hard mask layer；
Interlayer dielectric layer described in the photoresistance of this another patterning as mask etching, forms described groove；
Remove the photoresistance of this another patterning.
3. the preparation method of copper interconnection structure as claimed in claim 2 is it is characterised in that also include: etching at least part of the
One cobalt metal level.
4. the preparation method of copper interconnection structure as claimed in claim 1 or 2 is it is characterised in that adopt physical vapour deposition (PVD) work
Skill forms described second cobalt metal level in the diapire of described through hole, and the thickness of described second cobalt metal level is
5. the preparation method of copper interconnection structure as claimed in claim 2 is it is characterised in that also include: using wet etching work
Skill is etched back to the described hard mask layer around described groove.
6. the preparation method of copper interconnection structure as claimed in claim 5 is it is characterised in that be etched back to the width of described hard mask layer
Spend and be
7. the preparation method of copper interconnection structure as claimed in claim 1 is it is characterised in that also include: on described metal level
Form the 3rd cobalt metal level.
8. the preparation method of copper interconnection structure as claimed in claim 7 is it is characterised in that the thickness of described 3rd cobalt metal level
For
9. the preparation method of copper interconnection structure as claimed in claim 1 is it is characterised in that described first cobalt metal level is described
Ratio is selected more than 20 with the deposition in described low-k dielectric layer on copper interconnecting line.
10. the preparation method of copper interconnection structure as claimed in claim 1 is it is characterised in that the material on described barrier layer is nitrogen
Change titanium, the thickness on described barrier layer is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611089586.9A CN106340488A (en) | 2016-11-30 | 2016-11-30 | Preparation method of copper interconnection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611089586.9A CN106340488A (en) | 2016-11-30 | 2016-11-30 | Preparation method of copper interconnection structure |
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| CN106340488A true CN106340488A (en) | 2017-01-18 |
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| CN201611089586.9A Pending CN106340488A (en) | 2016-11-30 | 2016-11-30 | Preparation method of copper interconnection structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050245100A1 (en) * | 2004-04-30 | 2005-11-03 | Taiwan Semiconductor Manufacturing Co. | Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects |
| CN102859662A (en) * | 2009-10-23 | 2013-01-02 | 哈佛大学校长及研究员协会 | Self-aligned barrier and capping layers for interconnects |
| CN105552023A (en) * | 2016-02-26 | 2016-05-04 | 上海华力微电子有限公司 | Method for improving deposition selectivity of cobalt barrier layer |
-
2016
- 2016-11-30 CN CN201611089586.9A patent/CN106340488A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050245100A1 (en) * | 2004-04-30 | 2005-11-03 | Taiwan Semiconductor Manufacturing Co. | Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects |
| CN102859662A (en) * | 2009-10-23 | 2013-01-02 | 哈佛大学校长及研究员协会 | Self-aligned barrier and capping layers for interconnects |
| CN105552023A (en) * | 2016-02-26 | 2016-05-04 | 上海华力微电子有限公司 | Method for improving deposition selectivity of cobalt barrier layer |
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Application publication date: 20170118 |