CN118035149A - Configuration method, device, equipment and storage medium of PCIe topology - Google Patents

Abstract

The application provides a configuration method, a device, equipment and a storage medium of PCIe topology, which are applied to a server, wherein a CPU and a PCIe exchange chip are arranged on the server, and relate to the technical field of computers. The cable connection mode between the CPU and the PCIe exchange chip is obtained by responding to the power-on instruction, and the cable connection mode is determined and connected according to the application scene; determining a target topology mode matched with the cable connection mode; and configuring PCIe topology based on the target topology mode. According to the application, the target topology mode matched with the cable connection mode is determined through the cable connection mode between the CPU and the PCIe exchange chip, and then the PCIe topology is configured in a targeted manner according to the target topology mode, so that effective connection lines are prevented from being selected from the pre-laid connection lines of the PCIe topology, and the technical cost and the complexity of the hardware design of the server are reduced.

Description

Configuration method, device, equipment and storage medium of PCIe topology

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a storage medium for configuring PCIe topology.

Background

The server mainly comprises a central processing unit (Central Procession Unit, CPU for short), a memory, a hard disk, an Input/Output (I/O) expansion card and the like, and is matched with basic hardware such as a main board, a power supply, a case, a fan and the like to provide information service; a self-contained management system, such as a baseboard management controller (Baseboard Management Controller, BMC for short), is used for device daily management. In some cases, a peripheral component interconnect express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, abbreviated as PCIe) slot is provided on a motherboard of a server, a PCIe card may be inserted into the PCIe slot, and a PCIe device, such as a graphics processor (Graphics Processing Unit, abbreviated as GPU), may be connected to the PCIe card, where a connection relationship between the PCIe device and a CPU provided on the motherboard forms a PCIe topology, and PCIe topologies corresponding to different application scenarios may be different.

In the related art, when designing hardware of a server, usually, as many connection lines as possible are laid out in advance to form a PCIe topology capable of corresponding to multiple application scenarios, so when in application, according to requirements of a specific application scenario, an effective connection line is selected from the laid out connection lines of the PCIe topology through the BMC, thereby completing configuration of the PCIe topology corresponding to the specific application scenario.

However, the inventor researches and discovers that the method needs to lay out a large number of connecting wires in advance and select effective connecting wires from the large number of connecting wires, which increases technical cost and makes the hardware design of the server complex.

Disclosure of Invention

The application provides a configuration method, a device, equipment and a storage medium of PCIe topology, which are used for solving the problems of high cost and complex hardware design.

In a first aspect, the present application provides a method for configuring PCIe topology, applied to a server, where a CPU and a PCIe switching chip are disposed on the server, the method for configuring PCIe topology includes: responding to the power-on instruction, acquiring a cable connection mode between the CPU and the PCIe exchange chip, wherein the cable connection mode is determined and connected according to an application scene; determining a target topology mode matched with the cable connection mode; and configuring PCIe topology based on the target topology mode.

In a possible implementation manner, the CPU and the PCIe switch chip are both provided with a target interface, where the target interface includes a complex programmable logic device (Complex Programmable Logic Device, abbreviated as CPLD) interface and/or a field programmable gate array (Field Programmable GATE ARRAY, abbreviated as FPGA) interface, to obtain a cable connection manner between the CPU and the PCIe switch chip, and the method includes: reading a cable identification of cable connection between the CPU and the PCIe exchange chip through the target interface, wherein the cable identification is defined by a hardware pull-up resistor arranged on an uplink multichannel input/output connector of the PCIe exchange chip; correspondingly, determining the target topology pattern matching the cable connection mode includes:

and determining a target topology mode matched with the read cable identification based on the corresponding relation between the preset cable identification and the topology mode.

In a possible implementation manner, the configuration method further includes: if the corresponding relation between the preset cable identification and the topology mode is not matched with the target topology mode, sending alarm information to the BMC, wherein the alarm information is used for indicating that the corresponding relation between the preset cable identification and the topology mode is not matched with the target topology mode, and the BMC is used for recording logs corresponding to the alarm information.

In a possible implementation manner, the corresponding relation between the preset cable identification and the topology mode is stored in the CPU and/or PCIe exchange chip; and/or, the corresponding relation between the preset cable identification and the topology mode is updateable.

In a possible implementation manner, the PCIe topology is configured based on the target topology mode, including: and carrying out power-on initialization configuration on firmware of related hardware based on the target topology mode, wherein the power-on initialization configuration comprises configuration of PCIe topology.

In one possible implementation, the server includes a GPU.

In a second aspect, the present application provides a PCIe topology configuration device, applied to a server, where a CPU and a PCIe switching chip are disposed on the server, the configuration device includes:

The acquisition module is used for responding to the power-on instruction, acquiring a cable connection mode between the CPU and the PCIe exchange chip, wherein the cable connection mode is determined and connected according to an application scene;

the determining module is used for determining a target topology mode matched with the cable connection mode;

And the configuration module is used for configuring the PCIe topology based on the target topology mode.

In one possible implementation, the obtaining module is specifically configured to: and reading a cable identification of cable connection between the CPU and the PCIe exchange chip through the target interface, wherein the cable identification is defined by a hardware pull-up resistor arranged on an uplink multichannel input/output connector of the PCIe exchange chip. Correspondingly, the determining module is specifically configured to: and determining a target topology mode matched with the read cable identification based on the corresponding relation between the preset cable identification and the topology mode.

In a possible implementation manner, the configuration device further comprises an alarm module, and the alarm module is specifically configured to: if the corresponding relation between the preset cable identification and the topology mode is not matched with the target topology mode, sending alarm information to the BMC, wherein the alarm information is used for indicating that the corresponding relation between the preset cable identification and the topology mode is not matched with the target topology mode, and the BMC is used for recording logs corresponding to the alarm information.

In a possible implementation manner, the corresponding relation between the preset cable identification and the topology mode is stored in the CPU and/or PCIe exchange chip; and/or, the corresponding relation between the preset cable identification and the topology mode is updateable.

In a possible implementation manner, the configuration module is specifically configured to: and carrying out power-on initialization configuration on firmware of related hardware based on the target topology mode, wherein the power-on initialization configuration comprises configuration of PCIe topology.

In one possible implementation, the server includes a GPU.

In a third aspect, the present application provides an electronic device comprising: a processor, a memory communicatively coupled to the processor;

The memory stores computer-executable instructions;

the processor executes the memory-stored computer-executable instructions to implement the method of configuring a PCIe topology of any one of the first aspects.

In a fourth aspect, the present application provides a computer-readable storage medium having stored therein computer-executable instructions that, when executed, are configured to implement the method for configuring a PCIe topology of any one of the first aspects.

In a fifth aspect, the present application provides a computer program product comprising a computer program which, when executed, is adapted to implement the method for configuring a PCIe topology of any one of the first aspects.

The configuration method, the device, the equipment and the storage medium of the PCIe topology are applied to a server, and a CPU and a PCIe exchange chip are arranged on the server, and the cable connection mode between the CPU and the PCIe exchange chip is obtained mainly by responding to a power-on instruction and is determined and connected according to an application scene; determining a target topology mode matched with the cable connection mode; and configuring PCIe topology based on the target topology mode. According to the application, the target topology mode matched with the cable connection mode is determined through the cable connection mode between the CPU and the PCIe exchange chip, and then the PCIe topology is configured in a targeted manner according to the target topology mode, so that effective connection lines are prevented from being selected from the pre-laid connection lines of the PCIe topology, and the technical cost and the complexity of the hardware design of the server are reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a flow chart illustrating a configuration of a PCIe topology according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a general structure according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a balanced mode-dual uplink structure according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a balanced mode-single uplink structure according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a cascade mode according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a cable identification of a cable connection according to an embodiment of the present application;

FIG. 7 is a flowchart illustrating a method for configuring a PCIe topology according to another embodiment of the present application;

FIG. 8 is a schematic diagram of a configuration device of PCIe topology according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

In the related art, the configuration of PCIe topology is implemented, and the topology mode may be further perceived by modifying a platform controller set general purpose input/Output (Platform Controller Hub General Purpose Input/Output, abbreviated as PCH GPIO) to adapt to different topologies, or by detecting an I2C connection mode by using the BMC. However, the above technique has the following problems: wires in topology mode require additional I2C devices if redundancy and redundant designs occur, but this results in increased costs.

Aiming at the problems, the application uses the Cable wire connection mode between PCIe GPU and PCIE SWITCH exchange chip to directly determine the topology mode through Cable identification (Cable Identification, abbreviated as Cable ID), thereby enabling all Firmware (FW), including Basic Input/Output System (BIOS), BMC, PCIe exchange chip and the like to directly sense the current topology structure for corresponding processing, and is directly convenient.

By way of example, the present application provides a method for configuring PCIe topology that can be used in a variety of situations, such as in workstations and servers, for connecting various servers to meet the needs of professional applications.

The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

Fig. 1 is a flowchart illustrating a PCIe topology configuration according to an embodiment of the present application. The configuration method of the PCIe topology is applied to a server, and the server is provided with a CPU and a PCIe exchange chip. As shown in fig. 1, the method for configuring the PCIe topology includes:

s101, responding to a power-on instruction, acquiring a cable connection mode between the CPU and the PCIe exchange chip, wherein the cable connection mode is determined and connected according to an application scene.

Before the system is powered on, a user should determine an application scene first, and then determine a cable connection mode between the CPU and the PCIe exchange chip according to the determined application scene. Different application scenarios correspond to different cable connection modes, for example, when in a data center, two uplink interfaces of the PCIe switching chip need to be connected between CPUs respectively.

Further, the server uses the target interfaces set on the CPU and the PCIe switch chip to read the cable connection manner between the CPU and the PCIe switch chip, because the determined cable connection manner between the CPU and the PCIe switch chip may be stored in the target interfaces set on the CPU and the PCIe switch chip.

S102, determining a target topology mode matched with the cable connection mode.

After the cable connection mode between the CPU and the PCIe exchange chip is read, a target topology mode matched with the cable connection mode needs to be determined according to the cable connection mode. In other words, the topology mode needs to be determined according to the cable connection modes of the CPU and the PCIe switching chip, where different cable connection modes correspond to different target topology modes.

Alternatively, the topology modes may include a general mode, a balanced mode, and a cascade mode. By way of example, the following specifically exemplifies Cable connection modes in specific modes in connection with fig. 2,3, 4 and 5: as shown in fig. 2, the general mode: both PCIe switch chips are connected to CPU0, while CPU1 is not connected to PCIe switch chip; as shown in fig. 3, balanced mode-dual uplink: each PCIe exchange chip respectively connects two Upstream uplink interfaces to CPU0 and CPU1; as shown in fig. 4, balanced mode-single uplink: two PCIe exchange chips are respectively connected with the CPU0 and the CPU1 through an Upstream single uplink interface; as shown in fig. 5, the cascade mode: PCIe switch chip 1 is connected to CPU0, PCIe switch chip 0 is cascaded with PCIe switch chip 1.

S103, configuring PCIe topology based on the target topology mode.

The configuration of PCIe topology based on the target topology mode refers to power-on initialization configuration of firmware of related hardware, for example, power-on initialization configuration of a Basic Input/Output System (BIOS), a BMC, and a PCIe switch chip respectively, where the BIOS performs power-on initialization configuration of a CPU, the BMC performs power-on initialization configuration of an I2C, and the PCIe switch chip performs power-on initialization configuration of an uplink interface and a downlink interface.

According to the embodiment of the application, the target topology mode matched with the cable connection mode is determined through the cable connection mode between the CPU and the PCIe exchange chip, and then the PCIe topology is configured in a targeted manner according to the target topology mode, so that effective connection lines are prevented from being selected from the pre-laid connection lines of the PCIe topology, and the technical cost and the complexity of the hardware design of the server are reduced.

On the basis of the implementation, the CPU and the PCIe exchange chip are provided with target interfaces, the target interfaces comprise CPLD interfaces and/or FPGA interfaces, and the cable connection mode between the CPU and the PCIe exchange chip is obtained, and the method comprises the following steps: reading a cable identification of cable connection between the CPU and the PCIe exchange chip through the target interface, wherein the cable identification is defined by a hardware pull-up resistor arranged on an uplink multichannel input/output connector of the PCIe exchange chip; correspondingly, determining the target topology pattern matching the cable connection mode includes: and determining a target topology mode matched with the read cable identification based on the corresponding relation between the preset cable identification and the topology mode.

In this embodiment, it is understood that the cable identification of the cable connection between the CPU and PCIe switch chip may be stored at the CPLD interface and/or the FPGA interface. If the cable identification of the cable connection between the CPU and the PCIe exchange chip is stored in the CPLD interface, the cable identification of the cable connection between the CPU and the PCIe exchange chip is required to be read from the CPLD interface; if the cable identification of the cable connection between the CPU and the PCIe exchange chip is stored in the FPGA interface, the cable identification of the cable connection between the CPU and the PCIe exchange chip needs to be read from the FPGA interface. The Cable identifier of the Cable connection is defined by a hardware pull-up resistor set by a Multi-channel input/output (MCIO) connector on the switch chip, specifically, as shown in fig. 6, fig. 6 is a schematic structural diagram of the Cable identifier of the Cable connection provided in an embodiment of the present application, where a in fig. 6 is a schematic structural diagram of the CPU Cable ID on the motherboard side set up to be pulled up to the CPLD, and b in fig. 6 is a schematic structural diagram of the CPLD on the switch chip side set up to be pulled up to the switch chip side.

Correspondingly, determining the target topology pattern matching the cable connection mode includes: and matching and checking the cable identification of the cable connection between the CPU and the PCIe exchange chip read from the target interface with the preset corresponding relation between the cable identification and the topology mode. If the matching verification is passed, the read cable identification is considered to be matched with the target topology pattern. The corresponding relation between the preset cable identification and the topology mode can be set according to the user demand, and the application is not limited to the corresponding relation.

For example, the hardware Cable identifier (Cable Identification Hardware, abbreviated as Cable ID HW) is composed of 3 pins (pin), where the CPLD and software are represented by 3 bits (bit), and at most 8 different connection modes can be supported, and the information can be obtained on the motherboard side, so as to determine an uplink connection mode of a PCIe Switch (Switch) chip, and then bind the Cable ID Cable identifier with a topology mode of the PCIe Switch chip. For example, specific binding conditions are shown in table 1, and table 1 is a binding condition of a cable identifier and a topology mode of a switching chip provided by an embodiment of the present application.

TABLE 1

In table 1, different cable identifications represent different meanings, such as: "001" in the cascade mode represents that the PE0 ports of CPU0 are connected by 1 cable.

And matching the read cable identification of the cable connection between the CPU and the PCIe exchange chip according to the cable identification value pair mode in the table 1, wherein the cable identification value pair mode is determined through CPLD and/or FPGA logic definition. Further, if the topology mode needs to be more complex, a connection interface of a CPU segment and a PCIe exchange chip end needs to be added, and configuration of CPLD and/or corresponding IO of FPGA corresponding to the newly added Cable ID is added. Similarly, other topology modes needing to be expanded can be realized by increasing the binding condition of the cable identification and the topology mode of the exchange chip.

According to the embodiment of the application, the target topology mode matched with the read cable identification is determined based on the corresponding relation between the preset cable identification and the topology mode, so that effective connection lines among a large number of connection lines are avoided, and the cost is reduced.

Based on the above embodiment, the method for configuring PCIe topology further includes: if the corresponding relation between the preset cable identification and the topology mode is not matched with the target topology mode, sending alarm information to the BMC, wherein the alarm information is used for indicating that the corresponding relation between the preset cable identification and the topology mode is not matched with the target topology mode, and the BMC is used for recording logs corresponding to the alarm information.

In this embodiment, it may be understood that if the cable identifier read by the CPLD and/or the FPGA does not match the corresponding relationship based on the preset cable identifier and the topology mode, that is, the topology mode that does not match the target, an alarm message may be sent to the BMC to alert that the topology mode that does not match the target. The BMC receives the alarm information, records the alarm information into a corresponding system log, and informs the user of the related alarm information, wherein the informing mode can be set according to the user requirement, for example, the related alarm information is displayed on a display interface of the server.

According to the embodiment of the application, when the target topology mode is not matched, the alarm information is sent to the BMC, and the BMC records the related alarm information, so that the cause of the successful unmatched result can be checked.

Further, the corresponding relation between the preset cable identification and the topology mode is stored in the CPU and/or the PCIe exchange chip.

In some embodiments, the correspondence of the preset cable identification and topology pattern as described above is updateable. In this embodiment, it may be understood that the corresponding relationship of the preset cable identification topology mode is updateable, and may be set according to the user requirement, for example, if the topology mode is desired to be more complex, a connection interface of the CPU and PCIe switching chip end needs to be added, and a corresponding IO configuration of the CPLD and/or FPGA corresponding to the cable identification is added.

According to the embodiment of the application, the topology mode can be expanded by updating the corresponding relation between the preset cable identification and the topology mode.

Based on the above embodiment, the configuring of the PCIe topology based on the target topology mode in S103 includes: and carrying out power-on initialization configuration on firmware of related hardware based on the target topology mode, wherein the power-on initialization configuration comprises configuration of PCIe topology.

In this embodiment, power-on initialization configuration is performed on firmware of related hardware, for example, power-on initialization configuration is performed on a Basic Input/Output System (BIOS), a BMC, and a PCIe switch chip, respectively, where power-on initialization configuration of a CPU is performed on the BIOS, power-on initialization configuration of an I2C is performed on the BMC, and power-on initialization configuration of an uplink interface and a downlink interface is performed on the PCIe switch chip.

The embodiment of the application can reduce the error rate when configuring the PCIe topology by configuring the PCIe topology based on the target topology mode.

On the basis of the above embodiment, the above server includes a GPU.

In this embodiment, it is understood that in the method of configuring PCIe topology, the GPU typically plays the role of one end device, i.e., as one branch of PCIe topology mode, it is connected to the root port or connected to the root port through a switch chip.

Further, the GPU is capable of high speed data communication with the CPU and motherboard via the PCIe interface. In other words, it can be considered that the embodiment of the application accelerates the configuration method of the PCIe topology through the graphics processor, and can improve the efficiency of the configuration method.

In the following, taking a firmware method of PCIe GPU topology as an example, explaining how to use the configuration method of PCIe topology provided by the embodiment of the present application, the implementation steps refer to fig. 7, and fig. 7 is a schematic flow chart of the configuration method of PCIe topology provided by another embodiment of the present application. As shown in fig. 7, the implementation steps are as follows: before power-on, the cables are connected according to the corresponding switching modes by replacing the cables, and after power-on, BIOS, BMC, PCIe exchange chips acquire the topology mode through a unified CPLD and/or FPGA interface, so that each firmware can perform unified configuration selection.

In summary, the core idea of the embodiment of the application is that by using the connection mode of the Cable between CPU PCIe Root Port and the upstream interface of the PCIe switching chip (including between PCIe switching chips), the corresponding relation between the Cable ID value of the Cable and each topology is formed, and each firmware can process various topology configurations by using the same Image according to the Cable ID.

Further, the core idea provided by the embodiment of the application can be also understood as that the topology structure is directly determined by using the connection mode of the Cable line between CPU PCIe Root Port and the PCIe switching chips (including between PCIe switching chips), so that all FWs including BIOS, BMC, PCIe switching chips and the like directly sense the current topology structure to perform corresponding processing, and the method is direct and convenient, and does not need redundant Cable lines.

Furthermore, the configuration method of PCIe topology provided by the embodiment of the application can be applied to PCIe GPU Server for topology change, so that the firmware can adapt to various topologies without replacing the firmware.

The following are examples of the apparatus of the present application that may be used to perform the method embodiments of the present application. For details not disclosed in the embodiments of the apparatus of the present application, please refer to the embodiments of the method of the present application.

Fig. 8 is a schematic structural diagram of a PCIe topology configuration device according to an embodiment of the present application. As shown in fig. 8, the PCIe topology configuration apparatus 800 includes:

The obtaining module 801 is configured to respond to the power-on instruction, obtain a cable connection mode between the CPU and the PCIe switching chip, where the cable connection mode is determined and connected according to an application scenario;

A determining module 802, configured to determine a target topology mode that matches a cable connection mode;

a configuration module 803, configured to perform PCIe topology configuration based on the target topology mode.

In a possible implementation manner, the obtaining module 801 is specifically configured to: and reading a cable identification of cable connection between the CPU and the PCIe exchange chip through the target interface, wherein the cable identification is defined by a hardware pull-up resistor arranged on an uplink multichannel input/output connector of the PCIe exchange chip. Correspondingly, the determining module 802 is specifically configured to: and determining a target topology mode matched with the read cable identification based on the corresponding relation between the preset cable identification and the topology mode.

In a possible embodiment, the configuration device further comprises an alarm module (not shown), in particular for: if the corresponding relation between the preset cable identification and the topology mode is not matched with the target topology mode, sending alarm information to the BMC, wherein the alarm information is used for indicating that the corresponding relation between the preset cable identification and the topology mode is not matched with the target topology mode, and the BMC is used for recording logs corresponding to the alarm information.

In a possible implementation manner, the corresponding relation between the preset cable identification and the topology mode is stored in the CPU and/or PCIe exchange chip; and/or, the corresponding relation between the preset cable identification and the topology mode is updateable.

In a possible implementation manner, the configuration module 803 is specifically configured to: and carrying out power-on initialization configuration on firmware of related hardware based on the target topology mode, wherein the power-on initialization configuration comprises configuration of PCIe topology.

In one possible implementation, the server includes a GPU.

The PCIe topology configuration device provided by the embodiment of the present application may execute the technical solution shown in the foregoing method embodiment, and its implementation principle and beneficial effects are similar, and will not be described in detail.

It should be noted that, it should be understood that the division of the modules of the above apparatus is merely a division of a logic function, and may be fully or partially integrated into a physical entity or may be physically separated. And these modules may all be implemented in software in the form of calls by the processing element; or can be realized in hardware; the method can also be realized in a form of calling software by a processing element, and the method can be realized in a form of hardware by a part of modules. For example, the processing module may be a processing element that is set up separately, may be implemented in a chip of the above-mentioned apparatus, or may be stored in a memory of the above-mentioned apparatus in the form of program codes, and the functions of the above-mentioned processing module may be called and executed by a processing element of the above-mentioned apparatus. The implementation of the other modules is similar. In addition, all or part of the modules can be integrated together or can be independently implemented. The processing element here may be an integrated circuit with signal processing capabilities. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in a software form.

For example, the modules above may be one or more integrated circuits configured to implement the methods above, such as: one or more Application SPECIFIC INTEGRATED Circuits (ASIC), or one or more microprocessors (DIGITAL SIGNAL Processor DSP), or one or more field programmable gate arrays (Field Programmable GATE ARRAY FPGA), etc. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a System-On-a-Chip (SOC).

Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 9, an electronic device 900 provided by an embodiment of the present application may include: a processor 901, and a memory 902 communicatively coupled to the processor, wherein:

The memory stores computer-executable instructions;

The processor executes the computer-executable instructions stored in the memory to implement the methods described in the foregoing method embodiments.

It is to be appreciated that the Processor 901 may be a central processing unit (Central Processing Unit, CPU) or other general purpose Processor, digital signal Processor (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution. The memory 902 may include a high-speed random access memory (Random Access Memory, abbreviated as RAM), and may further include a non-volatile memory NVM (non-volatile memory), such as at least one magnetic disk memory, and may also be a U-disk, a removable hard disk, a read-only memory, a magnetic disk, or an optical disk.

Optionally, the electronic device 900 may also include a communication interface 903. In a specific implementation, if the communication interface 903, the memory 902, and the processor 901 are implemented independently, the communication interface 903, the memory 902, and the processor 901 may be connected to each other through buses and perform communication with each other. The bus may be an industry standard architecture (Industry Standard Architecture, ISA) bus, an external device interconnect (PERIPHERAL COMPONENT, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. Buses may be divided into address buses, data buses, control buses, etc., but do not represent only one bus or one type of bus.

Alternatively, in a specific implementation, if the communication interface 903, the memory 902, and the processor 901 are integrated on a chip, the communication interface 903, the memory 902, and the processor 901 may complete communication through internal interfaces.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer-executable instructions that, when executed, are configured to implement the method described in any of the foregoing embodiments.

It is understood that the computer readable storage medium may be implemented by any type or combination of volatile or non-volatile Memory devices, such as static random access Memory (Static Random Access Memory, SRAM for short), electrically erasable programmable Read-Only Memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY, EEPROM for short), erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM for short), programmable Read-Only Memory (Programmable Read Only Memory, PROM for short), read Only Memory (ROM for short), magnetic Memory, flash Memory, magnetic disk, or optical disk. A readable storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.

An exemplary computer readable storage medium is coupled to the processor such the processor can read information from, and write information to, the computer readable storage medium. In the alternative, the computer-readable storage medium may be integral to the processor. The processor and the computer readable storage medium may reside in an ASIC. The processor and the computer-readable storage medium may also reside as discrete components in an electronic device.

The integrated modules, which are implemented in the form of software functional modules, may be stored in a computer readable storage medium. The software functional modules described above are stored in a computer-readable storage medium and include instructions for causing an electronic device (which may be a personal computer, a server, or a network device, etc.) or a processor to perform some of the steps of the methods described in the various embodiments of the application.

Embodiments of the present application also provide a computer program product comprising a computer program which, when executed, implements the method described in any of the previous embodiments.

It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are alternative embodiments, and that the acts and modules referred to are not necessarily required for the present application.

It should be further noted that, although the steps in the flowchart are sequentially shown as indicated by arrows, the steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the sub-steps or stages are performed is not necessarily sequential, and may be performed in turn or alternately with at least a portion of the sub-steps or stages of other steps or other steps.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments. The technical features of the above embodiments may be combined in any way, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the description

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. The configuration method of PCIe topology is characterized by being applied to a server, wherein a central processing unit CPU and a peripheral component interconnect express (PCI express) standard PCIe switching chip are arranged on the server, and the configuration method comprises the following steps:

Responding to the power-on instruction, acquiring a cable connection mode between the CPU and the PCIe exchange chip, wherein the cable connection mode is determined and connected according to an application scene;

determining a target topology mode matched with the cable connection mode;

And configuring PCIe topology based on the target topology mode.

2. The configuration method according to claim 1, wherein the CPU and the PCIe switch chip are both provided with a target interface, the target interface includes a complex programmable logic device CPLD interface and/or a field programmable gate array FPGA interface, and the obtaining a cable connection manner between the CPU and the PCIe switch chip includes:

Reading a cable identification of cable connection between a CPU and a PCIe exchange chip through the target interface, wherein the cable identification is defined by a hardware pull-up resistor arranged by an uplink multi-channel input/output connector of the PCIe exchange chip;

Correspondingly, the determining the target topology mode matched with the cable connection mode comprises the following steps:

and determining a target topology mode matched with the read cable identification based on the corresponding relation between the preset cable identification and the topology mode.

3. The configuration method according to claim 2, characterized by further comprising:

if the corresponding relation between the preset cable identification and the topology mode is not matched with the target topology mode, sending alarm information to a Baseboard Management Controller (BMC), wherein the alarm information is used for indicating that the topology mode is not matched with the BMC, and the BMC is used for recording a log corresponding to the alarm information.

4. The configuration method according to claim 3, wherein the preset correspondence between cable identifications and topology patterns is stored in the CPU and/or the PCIe switching chip;

And/or, the corresponding relation between the preset cable identification and the topology mode is updateable.

5. The configuration method according to any one of claims 1 to 4, characterized in that the configuring of PCIe topology based on the target topology mode includes:

And carrying out power-on initialization configuration on firmware of related hardware based on the target topology mode, wherein the power-on initialization configuration comprises configuration of PCIe topology.

6. The configuration method according to any one of claims 1 to 4, characterized in that the server comprises a graphics processor GPU.

7. The configuration device of PCIe topology is characterized in that the configuration device is applied to a server, a CPU and a PCIe exchange chip are arranged on the server, and the configuration device comprises:

The response module is used for responding to the power-on instruction, acquiring a cable connection mode between the CPU and the PCIe exchange chip, wherein the cable connection mode is determined and connected according to an application scene;

The determining module is used for determining a target topology mode matched with the cable connection mode;

and the configuration module is used for configuring PCIe topology based on the target topology mode.

8. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor;

The memory stores computer-executable instructions;

The processor executes computer-executable instructions stored in the memory to implement the method of any one of claims 1 to 6.

9. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to carry out the method of any one of claims 1 to 6.

10. A computer program product comprising a computer program which, when executed by a processor, implements the method of any of claims 1-6.