CN118069562A

CN118069562A - Method, device, equipment and storage medium for managing hard disk backboard of double-node server

Info

Publication number: CN118069562A
Application number: CN202410136089.8A
Authority: CN
Inventors: 胡安沙
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2024-01-31
Filing date: 2024-01-31
Publication date: 2024-05-24

Abstract

The application relates to a method, a device, equipment and a storage medium for managing a hard disk backboard of a double-node server, wherein the method comprises the following steps: two nodes of the double-node server are connected with a back plate connector through the Y-shaped cable, the first node and the second node of the double-node server are respectively connected with two ends of the Y-shaped cable, the back plate connector is connected with a single end of the Y-shaped cable, and the back plate connector is connected with a plurality of hard disks; the method comprises the steps that a backboard programmable logic device receives preset configuration information in a Y-shaped cable, the configuration information represents hard disk information corresponding to a node, and the node comprises a first node and a second node; obtaining a preset mapping table, wherein the mapping table comprises a mapping relation between hard disk information and a backboard virtual interface address; and determining a backboard virtual interface address corresponding to the node according to the mapping table and the configuration information, and executing hard disk backboard management operation based on the backboard virtual interface address. The application can realize the hard disk backboard management of the double-node server without adding too many additional sideband signals.

Description

Method, device, equipment and storage medium for managing hard disk backboard of double-node server

Technical Field

The present application relates to the field of server technologies, and in particular, to a method, an apparatus, a device, and a storage medium for managing a hard disk backplane of a dual-node server.

Background

Currently, with the continuous development of computer technology, servers have become an integral part of modern enterprises. However, the conventional single point failure problem has plagued the enterprise because once a server fails, the entire system is affected, and thus current servers improve the reliability and performance of the system by setting up two or more independent nodes. The dual-node motherboard server adopts two independent nodes, and each node has independent resources such as a processor, a memory, a storage and the like. When one node fails, the other node can rapidly take over the workload, and the normal operation of the service is ensured. Meanwhile, the dual-node server also has a load balancing function, and can distribute requests to different nodes according to service requirements, so that the overall processing capacity is improved.

In order to enable the hard disk of the dual-node motherboard server to be equally distributed to the CPU (central processing unit ) of each node, the hard disk backplane may generate a situation that one NVME (Non-Volatile Memory express, non-volatile memory host controller interface specification) hard disk is derived from node 1 and the other NVME hard disk is derived from node 2, at this time, both nodes are required to transmit VPP (Virtual Point Protocol, virtual interface protocol) management signals to the hard disk backplane, so that the existing VPP management signals are doubled, and additional sideband signal connectors are required to be added. Because of the limited number of pins of the connector MCIO (Mini Cool Edge IO, a high-speed cable plug assembly) connected to the hard disk back plate, no spare pins are available at present, so that management such as VPP lighting is performed under the current number of pins.

Therefore, how to implement VPP management of the hard disk under CPU Balance without adding too many additional sideband signals is a technical problem to be solved.

Disclosure of Invention

Based on the above, the application provides a method, a device, equipment and a storage medium for managing a hard disk backboard of a dual-node server, so as to solve the problems in the prior art.

In a first aspect, a method for managing a hard disk backboard of a dual-node server is provided, the method comprising:

connecting two nodes of a double-node server with a back plate connector through a Y-shaped cable, wherein a first node and a second node of the double-node server are respectively connected with two ends of the Y-shaped cable, the back plate connector is connected with a single end of the Y-shaped cable, and the back plate connector is connected with a plurality of hard disks;

the backboard programmable logic device receives preset configuration information in the Y-shaped cable, the configuration information represents hard disk information corresponding to the node, and the node comprises the first node and the second node;

obtaining a preset mapping table, wherein the mapping table comprises a mapping relation between the hard disk information and a backboard virtual interface address;

and determining the backboard virtual interface address corresponding to the node according to the mapping table and the configuration information, and executing hard disk backboard management operation based on the backboard virtual interface address.

According to one implementation manner of the embodiment of the present application, the connecting two nodes of the dual-node server with one backplane connector through the Y-type cable includes:

the MCIO X signals transmitted by the mainboard connectors of each node of the double-node server are distributed to be X4 signals;

x4 signals transmitted by two nodes of the dual node server are connected to one backplane MCIO X connector by a Y-type cable connection.

According to one implementation manner of the embodiment of the present application, before the back-plane programmable logic device receives the preset configuration information in the Y-type cable, the method further includes:

and setting address signals on the backboard through cable internal resistor pull-up and resistor pull-down, and representing the configuration information through the address signals.

and a dial switch is arranged on the backboard, a dial signal is arranged according to the combination relation of the high level and the low level of the dial switch, and the configuration information is represented by the dial signal.

According to an implementation manner of the embodiment of the present application, the executing the hard disk backplane management operation based on the backplane virtual interface address includes:

the backboard programmable logic device analyzes the backboard virtual interface address to obtain a corresponding virtual interface lighting signal;

and executing lighting operation based on the virtual interface lighting signal.

According to one implementation manner of the embodiment of the present application, the receiving, by the back panel programmable logic device, preset configuration information in the Y-type cable includes:

and the backboard programmable logic device receives preset configuration information in the Y-shaped cable, and determines first hard disk information corresponding to the first node and second hard disk information corresponding to the second node according to the configuration information.

According to an implementation manner of the embodiment of the present application, the determining, according to the mapping table and the configuration information, the backplane virtual interface address corresponding to the node includes:

Acquiring target hard disk information and a target node port corresponding to the target hard disk information according to the configuration information;

acquiring a target backboard virtual interface address corresponding to the target hard disk information according to the mapping table;

And determining a target backboard virtual interface address corresponding to the target node port.

In a second aspect, there is provided a dual node server hard disk backplane management apparatus, the apparatus comprising:

A connection unit: the two nodes of the double-node server are connected with one backboard connector through the Y-shaped cable, wherein the first node and the second node of the double-node server are respectively connected with two ends of the Y-shaped cable, the backboard connector is connected with a single end of the Y-shaped cable, and the backboard connector is connected with a plurality of hard disks;

Configuration unit: the back panel programmable logic device is used for receiving preset configuration information in the Y-shaped cable, the configuration information represents hard disk information corresponding to the nodes, and the nodes comprise the first node and the second node;

mapping unit: the mapping table is used for obtaining a preset mapping table, and the mapping table comprises a mapping relation between the hard disk information and the backboard virtual interface address;

Management unit: and the hard disk back panel management operation is executed based on the back panel virtual interface address.

In a third aspect, there is provided a computer device comprising:

at least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores computer instructions executable by the at least one processor to enable the at least one processor to perform the method as referred to in the first aspect above.

In a fourth aspect, there is provided a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method referred to in the first aspect above.

According to the technical content provided by the embodiment of the application, two nodes of the double-node server are connected with one backboard connector through the Y-shaped cable, the backboard programmable logic device receives preset configuration information in the Y-shaped cable, further obtains a preset mapping table, determines the backboard virtual interface address corresponding to the node according to the mapping table and the configuration information, and executes hard disk backboard management operation based on the backboard virtual interface address. Under the condition that the virtual interface protocol related signal wires are not added, a certain configuration information and a mapping rule are set, so that the back plate programmable logic device can identify the configuration information of the current dual-node server, the corresponding relation between the virtual interface addresses of the related node back plates is mapped automatically, and the purpose of hard disk back plate management of the dual-node server is achieved under the condition that too many additional sideband signals are not added.

Drawings

FIG. 1 is a flow chart of a method for managing a hard disk backplane of a dual node server according to one embodiment;

FIG. 2 is a schematic diagram of a method for managing a hard disk backplane of a dual node server according to the prior art;

FIG. 3 is a schematic diagram of a method for dual node server hard disk backplane management in one embodiment;

FIG. 4 is a schematic diagram illustrating one configuration of a method for managing a hard disk backplane of a dual node server according to one embodiment;

FIG. 5 is a second configuration diagram of a dual node server hard disk backplane management method according to one embodiment;

FIG. 6 is a block diagram of a dual node server hard disk backplane management device in one embodiment;

fig. 7 is a schematic structural diagram of a computer device in one embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

Fig. 1 is a flowchart of a method for managing a hard disk backboard of a dual-node server according to an embodiment of the present application. Fig. 2 is a technical scheme diagram of dual-node server hard disk VPP management in the prior art, as shown in fig. 2, in the prior art, the hard disk VPP management of the current dual-node server or dual-path CPU motherboard is generally controlled by reasonably setting the number of hard disks supported by the hard disk backboard under CPU Balance, for example, the hard disk management can be set as a 4-port backboard or an 8-port backboard, when the CPU Balance is needed, 4 hard disks (X4) can be divided into two CPUs on average, each CPU is connected with two hard disks, so that each CPU can occupy one PCIe X8 port, as shown in fig. 2.

The VPP may be managed by a set of addresses, as shown in table 1. The VPP management related signals include VPP ADDR, VPP I2C and vpp_alert related signals, which occupy a large number of sideband signal pins MCIO, and are mainly transmitted between the MCIO connector and the backplate MCIO connector of the motherboard through MCIO cables, so as to realize operations such as hard disk VPP lighting. However, in order to maximize the number of hard disks supported by the server and to activate the server, a 2-port backplane may be required to be configured in the system, and in this case, in the case of dual-node CPU Balance, each node needs to be connected to a hard disk, and then both nodes need to transmit VPP related signals to the hard disk backplane, so that the VPP related signals are multiplied, and then a sideband connector needs to be additionally added, so that the space of the board is occupied.

TABLE 1

PCIEPort	VPPStrapPin[3:0]
		PE0A/PE0B	0001
PE0C/PE0D	0010
		PE1A/PE1B	0011
PE1C/PE1D	0100
		PE2A/PE2B	0101
PE2C/PE2D	0110
		PE3A/PE3B	0111
PE3C/PE3D	1000
		PE4A/PE4B	1001
PE4C/PE4D	1010

At present, most of the hard disk backplates don't consider the situation of CPU Balance temporarily, because the dual node server, each node is independent, when taking the 2 port backplates as an example, in order to evenly distribute the number of hard disks in the server to each node, the scenes that 2 hard disks are respectively managed by different nodes will occur, meanwhile, the power management and VPP lighting related operations need to be respectively controlled by the respective nodes, especially VPP lighting is limited by the signal number problem of MCIO connector sideband, and two groups of VPP addresses and related management signals cannot be transmitted at MCIO. The MCIO cable sideband has insufficient signal wires, cannot support power supply and related management of two hard disks, and if a mode of realizing CPU Balance is required to be adopted, a separate sideband signal connector needs to be added, so that the space of a hard disk backboard is occupied; if the number of sideband signals is increased, sideband connectors and cables are additionally added, the difficulty of the server case wire arrangement is increased, and the increase of the case cables has a certain influence on the heat dissipation air duct.

As shown in fig. 1, fig. 1 is a method for managing a hard disk back plate of a dual-node server according to an embodiment of the present application, which may include the following steps:

Step 101: and connecting two nodes of the double-node server with one backboard connector through the Y-shaped cable, wherein the first node and the second node of the double-node server are respectively connected with two ends of the Y-shaped cable, the backboard connector is connected with one end of the Y-shaped cable, and the backboard connector is connected with a plurality of hard disks.

Specifically, as shown in fig. 3, in the embodiment of the present application, in the context that the hard disk backplane needs to implement CPU Balance, the problem that signals related to the Balance backplane VPP need to occupy a large number of MCIO cables sideband signal wires is solved at the same time, and two nodes of the dual-node server are connected to one backplane connector by using Y-type cables. As shown in fig. 3, the first node and the second node of the dual-node server are respectively connected with two ends of the Y-type cable, the back board connector is connected with a single end of the Y-type cable, and the back board connector is connected with a plurality of hard disks. The two node main boards MCIO are connected with the backboard MCIO by adopting Y-shaped cable connection, related PCIe signals, PERST, PCIE_CLK and other signals are averagely connected to the backboard, and for PCIe signals, X8 MCIO connectors of each node main board only need to transmit X4 through the Y-shaped cable.

Step 102: the back panel programmable logic device receives preset configuration information in the Y-shaped cable, the configuration information represents hard disk information corresponding to the nodes, and the nodes comprise the first node and the second node.

Specifically, special configuration information is preset in the Y-shaped cable, when the server inserts the special manufacturing cable, the backplate programmable logic device CPLD detects the configuration information, so that it is known from which node the PCIE of the hard disk on the current 2-port backplate comes from, and from which node the PCIE of the hard disk comes respectively. For example, when the back plane programmable logic device recognizes that the configuration information is banlance and configures 1, the mapping relationship of the CPLD is fixed by default, that is, when 1101 is recognized, the CPLD considers that the first hard disk of the PCIE of the 2-port back plane is from the PE2A of the node 1 and the second hard disk is from the PE3A of the node 2, so that only one set of VPP ADDR is set, the CPLD can know where the PCIE of the two hard disks of the current back plane are respectively from, and lighting operation is convenient.

Step 103: and acquiring a preset mapping table, wherein the mapping table comprises a mapping relation between the hard disk information and the backboard virtual interface address.

Specifically, a mapping relation between the hard disk information of each hard disk on the back plate and the virtual interface address of the back plate is written in a preset mapping table in advance, and when the back plate recognizes that the configuration information transmitted by the cable is the Balance configuration, the mapping table is automatically checked, so that mapping between two nodes PCIe port and VPP ADDR is further executed.

Step 104: and determining the backboard virtual interface address corresponding to the node according to the mapping table and the configuration information, and executing hard disk backboard management operation based on the backboard virtual interface address.

Specifically, as shown in fig. 4, when the configuration information backplane programmable logic device identifies that the configuration information is banlance configured 1, the mapping relationship of the CPLD is fixed by default, or if the configuration information is identified 1101, it is determined that the configuration is currently configured 1 by the Balance. At this time, according to the configuration information 1101, the cpld considers that the PCIE first hard disk of the 2-port backplane is from the PE2A of the node 1, and the second hard disk is from the PE3A of the node 2. Searching the mapping relation table to obtain VPP STRAP PIN corresponding to the first hard disk as 0101 and VPP STRAP PIN corresponding to the second hard disk as 0111. Then, VPP STRAP PIN after PE2A mapping of node 1 is 0101 and VPP STRAP PIN after PE3A mapping of node 2 is 0111. Thus, the VPP ADDR of the two hard disks can be mapped by a set of configuration information 1101, and functions such as relevant VPP lighting can be realized.

It can be seen that, in the embodiment of the present application, two nodes of a dual-node server are connected to one backplane connector through a Y-cable, and a backplane programmable logic device receives preset configuration information in the Y-cable, further obtains a preset mapping table, determines the backplane virtual interface address corresponding to the node according to the mapping table and the configuration information, and executes a hard disk backplane management operation based on the backplane virtual interface address. Under the condition that the virtual interface protocol related signal wires are not added, a certain configuration information and a mapping rule are set, so that the back plate programmable logic device can identify the configuration information of the current dual-node server, the corresponding relation between the virtual interface addresses of the related node back plates is mapped automatically, and the purpose of hard disk back plate management of the dual-node server is achieved under the condition that too many additional sideband signals are not added.

In one embodiment of the present application, the connecting two nodes of the dual node server to one backplane connector by the Y-cable in step 101 includes: the MCIO X signals transmitted by the mainboard connectors of each node of the double-node server are distributed to be X4 signals; x4 signals transmitted by two nodes of the dual node server are connected to one backplane MCIO X connector by a Y-type cable connection.

According to the embodiment of the application, the VPP management of the hard disk under the CPU Balance condition is realized under the condition that too many VPP sideband signals are not additionally added, the VPP lighting control of the hard disk under the CPU Balance condition is realized, the VPP lighting of the hard disk under the CPU Balance condition is realized, and the use of sideband signals can be reduced.

In one embodiment of the present application, before the back-plane programmable logic device receives the preset configuration information in the Y-type cable in step 102, the method further includes: and setting address signals on the backboard through cable internal resistor pull-up and resistor pull-down, and representing the configuration information through the address signals.

Specifically, for the configuration information, the configuration information can be set inside the cable, and address signals are set on the back plate through the pull-up of the internal resistance of the cable and the pull-down of the resistance, and the configuration information is represented through the address signals. The pull-up and pull-down of the internal resistance of the cable generally refers to setting a resistance in the cable to achieve a pull-up or pull-down of the signal, a technique common in digital circuit design for ensuring the level state of the signal in the cable. By connecting to a pull-up resistor at a high level, it is ensured that the signal remains at a high level without other inputs. By connecting to a pull-down resistor at a low level, it is ensured that the signal remains at a low level without other inputs. For example, address signals set by cable internal resistance pull-up and resistance pull-down are shown in table 2, address signal 1101 representing Balance configuration 1; address signals 1110 represent Balance configuration 2; address signal 1111 represents Balance configuration 3; address signal 0000 represents Balance configuration 4.

TABLE 2

Configuration of	Address signal is set in cable
		Balance configuration 1	1101
Basance configuration 2	1110
		Balance configuration 3	1111
Balance configuration 4	0000

In one embodiment of the present application, before the back-plane programmable logic device receives the preset configuration information in the Y-type cable in step 102, the method further includes: and a dial switch is arranged on the backboard, a dial signal is arranged according to the combination relation of the high level and the low level of the dial switch, and the configuration information is represented by the dial signal.

Specifically, in order to reduce the cable processing difficulty, on the other hand, the limitation that the VPP ADDR can only be extended by 4 groups of Balance configuration is solved by using the up-and-down pull of the cable, a dial switch is arranged on a back plate, a dial signal is arranged according to the combination relation of the high level and the low level of the dial switch, the configuration information is represented by the dial signal, and the number of the dial switch channels can be selected according to the actual Balance configuration number. As shown in table 3, when the switch is turned to 00, the switch is transferred to the backplane CPLD, and if the CPLD detects 00, it is regarded as the Balance configuration 1, that is, determines PCIE of two hard disks, where the first hard disk is from PE2A of node 1 and the second hard disk is from PE3A of node 2. When the switch is dialed to 01, the switch is transmitted to the backboard CPLD, and if the CPLD detects 01, the switch is regarded as the Balance configuration 2; when the switch is dialed to 10, the switch is transmitted to the backboard CPLD, and if the CPLD detects 10, the switch is regarded as the Balance configuration 3; when the switch dials 11, which is passed to the back plane CPLD, the CPLD detects 11 and considers to be Balance configuration 4.

TABLE 3 Table 3

Configuration of	Dial switch arrangement
		Balance configuration 1	00
Basance configuration 2	01
		Balance configuration 3	10
Balance configuration 4	11

In one embodiment of the application, one end of the dial switch is pulled up to a power supply through a resistor to represent a high level; the other end of the dial switch is grounded through a pull-down resistor and represents low level; two ends of the dial switch are respectively connected with two pins of the backboard programmable logic device; the two pins connected to the backboard programmable logic device are determined to be high level or low level through the dialing of the dial switch, and the high-low level combination of the dial switch is defined according to the configuration information.

The dial switch can also adopt the form of an electronic switch, the electronic switch does not need to actually wave the dial key, and the electronic switch can be controlled to be conducted to a high level or a low level through a control signal.

According to the embodiment of the application, the dial switch is arranged on the backboard, the dial signal is arranged according to the combination relation of the high level and the low level of the dial switch, and the configuration information is represented by the dial signal, so that on one hand, the cable processing difficulty is reduced, and on the other hand, the problem of limited expansion configuration quantity for realizing the setting of the backboard virtual interface address by utilizing the up-down pull in the cable is solved.

In one embodiment of the present application, the performing a hard disk backplane management operation based on the backplane virtual interface address in step 104 includes: the backboard programmable logic device analyzes the backboard virtual interface address to obtain a corresponding virtual interface lighting signal; and executing lighting operation based on the virtual interface lighting signal.

Specifically, for the hard disk backboard, the hard disks on the board come from the same CPU or different CPUs respectively, so conventionally, a VPP ADDR needs to be set to map which CPU the PCIE resource of the current hard disk backboard comes from and which PCIE port of the CPU comes from, and the VPP ADDR is generally implemented by pulling up or pulling down resistors at the motherboard end, then is transmitted to the hard disk backboard through a cable, and then is transmitted to the CPLD of the backboard, and in the CPLD, which port of the CPU the inserted hard disk comes from is judged by setting a mapping relation, so that the lighting of the hard disk can be realized by controlling the CPLD through instructions. For example, an instruction is used to transmit a command for lighting the hard disk of the PE0[7:0] port of the CPU0 to the CPLD, and the indicator lamp of the related hard disk can be accurately lightened through the mapping relation of the VPP address. For the NVME hard disk backboard, the hard disk is provided with three indicator lamps, namely FAULT (error indication), local (in-place indication) and ACTIVE (read-write status indication). And the backboard programmable logic device CPLD analyzes the backboard virtual interface address VPP ADDR to obtain a corresponding virtual interface lighting signal, and then performs lighting operation on the indicator lamp based on the virtual interface lighting signal.

In one embodiment of the present application, the receiving, by the back panel programmable logic device in step 102, preset configuration information in the Y-type cable includes: and the backboard programmable logic device receives preset configuration information in the Y-shaped cable, and determines first hard disk information corresponding to the first node and second hard disk information corresponding to the second node according to the configuration information.

According to the embodiment of the application, the VPP mapping identification rule is set in the CPLD, so that which port of which node the current hard disk originates from can be effectively identified, and VPP management is realized. The specific configuration of the Balance backboard is realized by two modes of pulling up and down and dialing in the cable, and the backboard layout space is saved.

In one embodiment of the present application, the determining the backplane virtual interface address corresponding to the node according to the mapping table and the configuration information in step 104 includes: acquiring target hard disk information and a target node port corresponding to the target hard disk information according to the configuration information; acquiring a target backboard virtual interface address corresponding to the target hard disk information according to the mapping table; and determining a target backboard virtual interface address corresponding to the target node port.

In the embodiment of the application, two nodes of a double-node server are connected with one backboard connector through a Y-shaped cable, a backboard programmable logic device receives preset configuration information in the Y-shaped cable, a preset mapping table is further obtained, the backboard virtual interface address corresponding to the node is determined according to the mapping table and the configuration information, and hard disk backboard management operation is executed based on the backboard virtual interface address. Under the condition that the virtual interface protocol related signal wires are not added, a certain configuration information and a mapping rule are set, so that the back plate programmable logic device can identify the configuration information of the current dual-node server, the corresponding relation between the virtual interface addresses of the related node back plates is mapped automatically, and the purpose of hard disk back plate management of the dual-node server is achieved under the condition that too many additional sideband signals are not added.

It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited in the present application, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the sub-steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of other steps or sub-steps of other steps.

According to the specific embodiment provided by the application, the technical scheme provided by the application can have the following advantages: the VPP management of the hard disk under the CPU Balance condition is realized under the condition that too many VPP sideband signals are not additionally added, the VPP lighting control of the hard disk under the CPU Balance condition is realized, the VPP lighting of the hard disk under the CPU Balance condition is realized, and the use of sideband signals can be reduced. By setting the VPP mapping identification rule in the CPLD, which port of which node the current hard disk originates from can be effectively identified, and VPP management is realized. The specific configuration of the Balance backboard is realized by two modes of pulling up and down and dialing in the cable, and the backboard layout space is saved.

Fig. 6 is a schematic structural diagram of a dual-node server hard disk backboard management device according to an embodiment of the present application, and as shown in fig. 6, the device may include:

Connection unit 601: the two nodes of the double-node server are connected with one backboard connector through the Y-shaped cable, wherein the first node and the second node of the double-node server are respectively connected with two ends of the Y-shaped cable, the backboard connector is connected with a single end of the Y-shaped cable, and the backboard connector is connected with a plurality of hard disks;

Configuration unit 602: the back panel programmable logic device is used for receiving preset configuration information in the Y-shaped cable, the configuration information represents hard disk information corresponding to the nodes, and the nodes comprise the first node and the second node;

mapping unit 603: the mapping table is used for obtaining a preset mapping table, and the mapping table comprises a mapping relation between the hard disk information and the backboard virtual interface address;

Management unit 604: for determining the backboard virtual interface address corresponding to the node according to the mapping table and the configuration information, and executing hard disk backboard management operation based on the backboard virtual interface address

In one embodiment of the present application, the connection unit 601 is further configured to:

In one embodiment of the present application, the first setting unit further includes a first setting unit for: and setting address signals on the backboard through cable internal resistor pull-up and resistor pull-down, and representing the configuration information through the address signals.

In one embodiment of the present application, the apparatus further comprises a second setting unit for: and a dial switch is arranged on the backboard, a dial signal is arranged according to the combination relation of the high level and the low level of the dial switch, and the configuration information is represented by the dial signal.

In one embodiment of the present application, the management unit 604 is further configured to:

In one embodiment of the present application, the configuration unit 602 is further configured to: and the backboard programmable logic device receives preset configuration information in the Y-shaped cable, and determines first hard disk information corresponding to the first node and second hard disk information corresponding to the second node according to the configuration information.

According to the specific embodiment provided by the application, the technical scheme provided by the application can have the following advantages:

The VPP management of the hard disk under the CPU Balance condition is realized under the condition that too many VPP sideband signals are not additionally added, the VPP lighting control of the hard disk under the CPU Balance condition is realized, the VPP lighting of the hard disk under the CPU Balance condition is realized, and the use of sideband signals can be reduced. By setting the VPP mapping identification rule in the CPLD, which port of which node the current hard disk originates from can be effectively identified, and VPP management is realized. The specific configuration of the Balance backboard is realized by two modes of pulling up and down and dialing in the cable, and the backboard layout space is saved.

The same and similar parts of the above embodiments are all referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.

It should be noted that, in the embodiment of the present application, the use of user data may be involved, and in practical application, user specific personal data may be used in the schemes described herein within the scope allowed by applicable legal regulations under the condition that the applicable legal regulations of the country are met (for example, the user explicitly agrees, the user is explicitly notified, the user is explicitly authorized, etc.).

According to an embodiment of the present application, the present application also provides a computer device, a computer-readable storage medium. The application also provides a computer device comprising at least one processor, and a memory communicatively coupled to the at least one processor; the memory stores computer instructions executable by the at least one processor to enable the at least one processor to perform the dual node server hard disk backplane management method according to any of the embodiments described above.

As shown in fig. 7, is a block diagram of a computer device according to an embodiment of the present application. Computer equipment is intended to represent various forms of digital computers or mobile devices. Wherein the digital computer may comprise a desktop computer, a portable computer, a workstation, a personal digital assistant, a server, a mainframe computer, and other suitable computers. The mobile device may include a tablet, a smart phone, a wearable device, etc.

As shown in fig. 7, the computer device 700 includes a computing unit 701, a ROM 702, a RAM 703, a bus 704, and an input/output (I/O) interface 705, and the computing unit 701, the ROM 702, and the RAM 703 are connected to each other through the bus 704. An input/output (I/O) interface 705 is also connected to bus 704.

The computing unit 701 may perform various processes in the method embodiments of the present application according to computer instructions stored in a Read Only Memory (ROM) 702 or computer instructions loaded from a storage unit 708 into a Random Access Memory (RAM) 703. The computing unit 701 may be a variety of general and/or special purpose processing components having processing and computing capabilities. The computing unit 701 may include, but is not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), as well as any suitable processor, controller, microcontroller, etc. In some embodiments, the methods provided by embodiments of the present application may be implemented as a computer software program tangibly embodied on a computer-readable storage medium, such as storage unit 708.

The RAM 703 may also store various programs and data required for the operation of the device 700. Part or all of the computer program may be loaded and/or installed onto the device 700 via the ROM 702 and/or the communication unit 709.

An input unit 706, an output unit 707, a storage unit 708, and a communication unit 709 in the computer apparatus 700 may be connected to the I/O interface 705. Wherein the input unit 706 may be, for example, a keyboard, mouse, touch screen, microphone, etc.; the output unit 707 may be, for example, a display, a speaker, an indicator light, or the like. The device 700 is capable of exchanging information, data, and the like with other devices through the communication unit 709.

It should be noted that the device may also include other components necessary to achieve proper operation. It is also possible to include only the components necessary to implement the inventive arrangements, and not necessarily all the components shown in the drawings.

Various implementations of the systems and techniques described here can be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof.

Computer instructions for implementing the methods of the present application may be written in any combination of one or more programming languages. These computer instructions may be provided to a computing unit 701 such that the computer instructions, when executed by the computing unit 701, such as a processor, cause the steps involved in embodiments of the method of the present application to be performed.

The present application also provides a computer readable storage medium having stored thereon computer instructions for causing a computer to execute the dual node server hard disk backplane management method according to any of the above embodiments.

The computer readable storage medium provided by the present application may be a tangible medium that may contain, or store, computer instructions for performing the steps involved in the method embodiments of the present application. The computer readable storage medium may include, but is not limited to, storage media in the form of electronic, magnetic, optical, electromagnetic, and the like.

The above embodiments do not limit the scope of the present application. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of the present application.

Claims

1. The method for managing the hard disk backboard of the double-node server is characterized by comprising the following steps of:

2. The method for managing a hard disk backplane of a dual-node server according to claim 1, wherein said connecting two nodes of the dual-node server to one backplane connector by a Y-cable comprises:

3. The method for managing a hard disk backplane of a dual node server according to claim 1, further comprising, before the backplane programmable logic device receives the configuration information preset in the Y-type cable:

4. The method for managing a hard disk backplane of a dual node server according to claim 1, further comprising, before the backplane programmable logic device receives the configuration information preset in the Y-type cable:

5. The dual node server hard disk backplane management method of claim 1, wherein the performing hard disk backplane management operations based on the backplane virtual interface address comprises:

6. The method for managing a hard disk backplane of a dual-node server according to claim 1, wherein the backplane programmable logic device receives preset configuration information in the Y-type cable, comprising:

7. The method for managing a hard disk backplane of a dual-node server according to claim 1, wherein the determining the virtual interface address of the backplane corresponding to the node according to the mapping table and the configuration information comprises:

acquiring target hard disk information and a target node port corresponding to the target hard disk information according to the configuration information; acquiring a target backboard virtual interface address corresponding to the target hard disk information according to the mapping table;

8. A dual node server hard disk backplane management apparatus, comprising:

Configuration unit: the back panel programmable logic device is used for receiving preset configuration information in the Y-shaped cable, the configuration information represents hard disk information corresponding to the nodes, and the nodes comprise the first node and the second node; mapping unit: the mapping table is used for obtaining a preset mapping table, and the mapping table comprises a mapping relation between the hard disk information and the backboard virtual interface address;

9. A computer device, comprising:

at least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores computer instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

10. A computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of any of claims 1 to 7.