CN1180270C - Method of detecting short circuit of inner layer in multilayer printed circuit board - Google Patents
Method of detecting short circuit of inner layer in multilayer printed circuit board Download PDFInfo
- Publication number
- CN1180270C CN1180270C CNB011328762A CN01132876A CN1180270C CN 1180270 C CN1180270 C CN 1180270C CN B011328762 A CNB011328762 A CN B011328762A CN 01132876 A CN01132876 A CN 01132876A CN 1180270 C CN1180270 C CN 1180270C
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- vcc
- gnd
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Abstract
The present invention relates to a method for detecting the short-circuit phenomenon of a multi-layer board, which comprises the following steps: (1), converting a layout data file of the printed circuit board into a text description file; (2), collecting the information of a first position coordinate comprising a chunk of the Vcc layer and a chunk of the GND layer according to the text description file; (3), utilizing the file to collect the information of a second position coordinate corresponding to all through holes and the form information of the through holes; (4), determining the through holes in the form of a Vcc and a GND according to the form information; (5), judging whether the information of the second position coordinate corresponding to the Vcc through holes is formed in the information of the first position coordinate corresponding to the Vcc chunk; if all the Vcc through holes are arranged in the Vcc chunk, then short circuit does not occur between the Vcc layer and the GND layer.
Description
Technical field
The present invention relates to be used for detecting the printed circuit board (pcb) production taxi driver brother primary (method of Gerber) File file (file) internal layer short circuit.
Background technology
Generally speaking, after circuit designers is finished its circuit layout design drawing (schematics), utilize a kind of printed circuit board (PCB) (PCB) layout tool software to carry out printed circuit board (PCB) (PCB) layout.
Below, the present invention makes example with " PCAD V8.5,8.7 " for layout tool software, cooperates explanation the present invention.
Because " PCAD V8.5,8.7 " are for being applicable to the layout of two layer printed circuit boards.If human negligence causes the short circuit of multilayer board PCB internal layer, " PCAD V8.5,8.7 " can't detect.
If there is not a kind of proper method to address this problem, will cause the PCB charging to produce semi-manufacture after, just pinpoint the problems via electric test, it causes damage and is difficult to really estimate.
Therefore, be necessary to provide a method, purpose is that PCB brother primary (Gerber) file to before the PCB manufacturer, can carry out self-quality testing, the generation of preventing error in advance.
Summary of the invention
The objective of the invention is is providing a method to detect PCB brother primary (Gerber) file internal layer problem of short-circuit.
In order to realize above-mentioned purpose of the present invention, the invention provides a kind of method of utilizing the printed circuit board layout data file to check whether to be short-circuited between multiple-plate Vcc layer and the GND layer phenomenon, comprising: the file that (1) changes this printed circuit board layout data file is the text description form; (2) according to the file of this text description form, produce the primary importance coordinate information, this primary importance coordinate information comprises to Vcc block coordinate that should the Vcc layer and to GND block coordinate that should the GND layer; (3) utilize the file of this text description form, collection corresponds to the second place coordinate information and the through hole pin position form information of all through holes, this second place coordinate information comprises the position coordinates of all through holes, the name of each bar circuit and the position coordinates of each hand plug-in unit, and this through hole pin position form information is Vcc or GND; (4) according to this form information, the form that determines which through hole is that the form of Vcc, which through hole is GND; And (5) judge pin position form be Vcc through hole to should whether being arranged in this Vcc block coordinate by second place coordinate information; If be positioned within this Vcc block coordinate, then be judged to be this Vcc layer and this GND interlayer is not short-circuited, if be not positioned within this Vcc block coordinate, show that then this Vcc layer and this GND interlayer constitute short circuit.
Description of drawings
Fig. 1 is the figure of expression man-machine interface of the present invention;
Fig. 2 is the test flow chart that expression the present invention checks the short circuit of multilayer printed circuit board PCB internal layer;
Fig. 3 is the figure of expression Vcc layer test by the example of (pass);
Fig. 4 is the figure of expression GND layer test by the example of (pass);
Fig. 5 is the figure of the example of expression Vcc layer test crash (fail).
Embodiment
Previous operations of the present invention comprises circuit layout design (schematics) and (after the step 12), carries out PCB layout (step 14) with a kind of particular software application instrument.
Then, shown in second figure, the present invention converts printed circuit board (PCB) (PCB) topology file (file) data file of text description form at first in step 16, produces the printed circuit board layout data file of a * * * .pdf form.This pdf formal file is a kind of text description file, includes the characteristic of each circuit unit, coordinate and the data that connect of circuit each other, can for the subsequent software program utilize this electrical form of judging each layer (Vcc, GND), or the position coordinates of each through hole and form.
In step 180, software program of the present invention then determines in each conductive layer it is Vcc layer or at the GND layer.
In step 181, software program of the present invention is then collected position coordinates, pin position form (pin type), the name (net name) of each bar circuit and the position of each hand plug-in unit of all through holes.
In step 182, software program of the present invention is then according to the through hole form, and the form that determines which through hole is that the form of Vcc, which through hole is GND.
In step 183, software program of the present invention then determines to reach on the Vcc layer line name on the GND layer.
In step 184, it is whether the pairing circuit of through hole of Vcc is defined in the Vcc layer that software program of the present invention then detects pin position form.
If in step 184 is non-, show that then this through hole and Vcc constitute short circuit (step 185).
If for being, software program of the present invention further checks in step 186 pin position form is whether the pairing circuit of through hole of GND is defined in the GND layer in step 184.
If in step 186 is non-, represent that then this through hole and GND constitute short circuit (step 187).
If for being, software program of the present invention further produces a Vcc layer block diagram in step 188, according to this block diagram inspection whether the different through hole of color is arranged in step 186, a different color is represented some through holes and the short circuit of Vcc formation.
If for being, obtain this through hole coordinate figure in step 188, this through hole is circuit and Vcc short circuit (step 189).
If in step 188 is non-, software program of the present invention further produces a GND layer block diagram in step 190, according to this block diagram inspection whether the different through hole of color is arranged, and on behalf of some through holes and GND, a different color constitute short circuit.
If for being, then obtain this through hole coordinate figure in step 190, this through hole is circuit and GND short circuit (step 191).If in step 190 is non-, then finish program of the present invention.
The specific embodiment of particular software application instrument of the present invention is " PCAD V8.5,8.7 ".Utilize the present invention can guarantee institute's layout the correctness of PCB document quality more than four layers.The artificial mistake that causes can be found out one by one, and can be with the GND of internal layer, whether Vcc plants wrong block detects.Guarantee that each figure can correctly go out to the correct PCB finished product of PCB manufacturer making.Fig. 1 represents an embodiment of man-machine interface of the present invention.
Fig. 3 represents the figure of Vcc layer test by example.
As seen from Figure 3, have five big blocks, all Vcc through holes all pass through the test of Vcc layer block.
Fig. 4 represents the figure of GND layer test by example.
As seen from Figure 4, have six blocks, all GND through holes all pass through the test of GND layer block.
The table of failure example:
The short circuit inventory:
X position, block position Y pin configuration state mistake project
OR7 1305 1440 53 short?to?GND
ER2 1270 2335 54 short?to?VCC1
LVDS2_GND 870 2090 54 short?to?VCC1
Fig. 5 represents the figure of Vcc layer test crash (fail) example.
As seen from Figure 5, have five blocks, and the through hole of arrow indication falls into wrong block.Therefore its coordinate need be marked.
Claims (7)
1. method of utilizing the printed circuit board layout data file to check whether to be short-circuited between multiple-plate Vcc layer and the GND layer phenomenon comprises:
(1) file that to change this printed circuit board layout data file be the text description form;
(2) according to the file of this text description form, produce the primary importance coordinate information, this primary importance coordinate information comprises to Vcc block coordinate that should the Vcc layer and to GND block coordinate that should the GND layer;
(3) utilize the file of this text description form, collection corresponds to the second place coordinate information and the through hole pin position form information of all through holes, this second place coordinate information comprises the position coordinates of all through holes, the name of each bar circuit and the position coordinates of each hand plug-in unit, and this through hole pin position form information is Vcc or GND;
(4) according to this form information, the form that determines which through hole is that the form of Vcc, which through hole is GND; And
(5) judge pin position form is whether the through hole institute of Vcc is to being arranged in this Vcc block coordinate by second place coordinate information; If be positioned within this Vcc block coordinate, then be judged to be this Vcc layer and this G ND interlayer is not short-circuited, if be not positioned within this Vcc block coordinate, show that then this Vcc layer and this GND interlayer constitute short circuit.
2. the method for claim 1, wherein step (5) is if for being further to comprise:
(6) check pin position form is whether pairing this second place coordinate information of through hole of GND is arranged in this GND block coordinate.
3. method as claimed in claim 2, wherein step (6) shows that then this through hole and GND constitute short circuit if be non-.
4. method as claimed in claim 2, wherein step (6) is if for being further to comprise:
(7) produce Vcc layer block diagram, check the through hole whether different color is arranged in the same block in this Vcc layer block diagram, on behalf of a certain through hole and Vcc, a different color constitute short circuit.
5. method as claimed in claim 4, wherein step (7) is if for being then to obtain the coordinate figure of different color through hole.
6. method as claimed in claim 4, wherein step (7) further comprises if be non-:
(8) produce GND layer block diagram, check the through hole whether different color is arranged in the same block in this GND layer block diagram, on behalf of a certain through hole and GND, a different color constitute short circuit.
7. method as claimed in claim 6, wherein step (8) is if for being then to obtain the coordinate figure of different color through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011328762A CN1180270C (en) | 2001-09-12 | 2001-09-12 | Method of detecting short circuit of inner layer in multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011328762A CN1180270C (en) | 2001-09-12 | 2001-09-12 | Method of detecting short circuit of inner layer in multilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1403826A CN1403826A (en) | 2003-03-19 |
| CN1180270C true CN1180270C (en) | 2004-12-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011328762A Expired - Fee Related CN1180270C (en) | 2001-09-12 | 2001-09-12 | Method of detecting short circuit of inner layer in multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1180270C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101697001B (en) * | 2009-01-22 | 2011-07-13 | 依利安达(广州)电子有限公司 | Method for detecting positional deviation among layers of multilayer printed circuit board |
| CN102567554A (en) * | 2010-12-27 | 2012-07-11 | 佛山市顺德区顺达电脑厂有限公司 | Power supply point and signal point separating system and method |
| NL2006759C2 (en) * | 2011-05-10 | 2012-11-13 | Jtag Technologies Bv | A method of and an arrangement for automatically measuring electric connections of electronic circuit arrangements mounted on printed circuit boards. |
| CN104020388A (en) * | 2014-05-09 | 2014-09-03 | 东莞市五株电子科技有限公司 | Method for testing internal short circuit of PCB |
| CN108362993B (en) * | 2018-01-20 | 2020-08-18 | 江苏本川智能电路科技股份有限公司 | Measuring device and measuring method for multilayer coil plate |
-
2001
- 2001-09-12 CN CNB011328762A patent/CN1180270C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| CN1403826A (en) | 2003-03-19 |
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