CN118019355A - Multi-wafer stacking structure and preparation method - Google Patents

Multi-wafer stacking structure and preparation method Download PDF

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Publication number
CN118019355A
CN118019355A CN202211397115.XA CN202211397115A CN118019355A CN 118019355 A CN118019355 A CN 118019355A CN 202211397115 A CN202211397115 A CN 202211397115A CN 118019355 A CN118019355 A CN 118019355A
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chip
wafer
chips
unit
stacking
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CN202211397115.XA
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Chinese (zh)
Inventor
王正波
景蔚亮
廖恒
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN202211397115.XA priority Critical patent/CN118019355A/en
Priority to PCT/CN2023/105340 priority patent/WO2024098818A1/en
Publication of CN118019355A publication Critical patent/CN118019355A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The embodiment of the application discloses a multi-wafer stacking structure, which comprises the following components: a first wafer comprising a plurality of first chips; a second wafer including a plurality of second chips; the plurality of second chips are divided into a plurality of units, each unit comprises at least two second chips with the same number, each first chip in the plurality of first chips is stacked corresponding to the second chip in each unit in the plurality of units, and each first chip covers the second chip of one unit; the size of each first chip is the same as the size of one unit on the second wafer, so that stacking efficiency between chips with different functions can be improved.

Description

Multi-wafer stacking structure and preparation method
Technical Field
The embodiment of the application relates to the technical field of semiconductors, in particular to a multi-wafer stacking structure and a preparation method.
Background
With the development of communication, artificial intelligence and other technologies, a great deal of data flow and transfer demands are increasing, and hardware supporting applications such as 5G applications, artificial intelligence and the like is required to have functions of high-speed computing, low latency, multiple bandwidths, system integration and the like. To meet the functional requirements of the hardware device, a plurality of chips with different functions are usually disposed inside the electronic device. Thus, in integrated circuit fabrication, multiple different types of chips, such as logic, memory, communication, or sensing, need to be stacked together to achieve greater performance and functionality.
In the current multi-chip stacking mode, a chip-wafer stacking mode is generally adopted. That is, a certain type of wafer is cut into individual chips, and the cut individual chips are aligned and bonded with the chips on another type of wafer by adopting a bonding process, so that stacking of chips between different types is completed. When the above-mentioned chip-wafer stacking method is adopted, the wafer needs to be cut, and then the cut chips are arranged on the wafer to be bonded one by one, so that the process flow and the cost of the chip stacking are increased, and the yield of the chip stacking is reduced. Thus, how to improve the stacking efficiency between chips with different functions becomes a problem to be solved.
Disclosure of Invention
The multi-wafer stacking structure and the preparation method provided by the application can improve the stacking efficiency of chips with different functions. In order to achieve the above purpose, the application adopts the following technical scheme:
In a first aspect, an embodiment of the present application provides a multi-wafer stacking structure, including: a first wafer comprising a plurality of first chips; a second wafer including a plurality of second chips; each first chip of the plurality of first chips is stacked with at least one second chip of the plurality of second chips, and each first chip covers the at least one second chip; the plurality of second chips are divided into a plurality of units, each unit comprises at least two second chips with the same number, each first chip in the plurality of first chips is stacked corresponding to the second chip in each unit in the plurality of units, and each first chip covers the second chip of one unit; wherein the size of each first chip is the same as the size of one unit on the second wafer.
According to the multi-wafer stacking structure provided by the embodiment of the application, the size of the first chip on the first wafer is set to be the same as the size of one unit formed by a plurality of second chips on the second wafer, and the size of the plurality of chips on the second wafer is always the same as the size of the chips on the first wafer no matter how the size of the chips on the first wafer is changed through the constraint relation, namely, one chip on the first wafer can be bonded with one or more chips on the second wafer in an alignment way at the same time, so that the second wafer can be stacked with the first wafer with various sizes without redesigning the second wafer, thereby reducing the process flow and cost of chip stacking and improving the efficiency of chip stacking.
In the embodiment of the application, the interval between the second chips in each two units is larger than the interval between the two chips in one unit in the plurality of units divided on the second wafer. Furthermore, in a possible implementation, a test circuit is further provided between each two units to test the second chip on the second wafer.
In one possible implementation, the length of each first chip is an integer multiple of the sum of the length of one second chip and the spacing between two second chips in one unit.
In one possible implementation, the width of each first chip is an integer multiple of the sum of the width of one second chip and the spacing between two second chips in one unit.
In one possible implementation manner, each unit on the second wafer includes second chips arranged in an array, a length of each second chip is a along a column direction of the array, a spacing between every two second chips is c, a length of each first chip along the column direction is m×a+ (M-1) c, where a and c are positive numbers, M is an integer greater than or equal to zero, and M is a number of second chips along the column direction.
In one possible implementation manner, along a row direction of the array, a width of each second chip is b, a distance between every two second chips is d, and a width of each first chip along the row direction is n×b+ (N-1) d, where b and d are positive numbers, N is an integer greater than or equal to zero, and N is a number of second chips along the row direction.
In one possible implementation, the first chip on the first wafer is a system-on-a-chip or a processor chip, and the second chip on the second wafer is a memory chip.
In a second aspect, embodiments of the present application provide a method for preparing a multi-wafer stack structure, the method comprising: providing a first substrate, and forming a plurality of first chips on the first substrate to form a first wafer; providing a second substrate, and forming a plurality of second chips on the second substrate to form a second wafer; bonding the first wafer and the second wafer in an alignment manner to form the multi-wafer stacking structure; the plurality of second chips are divided into a plurality of units, each unit comprises at least two second chips with the same number, each first chip in the plurality of first chips is stacked corresponding to the second chip in each unit in the plurality of units, and each first chip covers the second chip of one unit; wherein the size of each first chip is the same as the size of one unit on the second wafer.
In one possible implementation, the length of each first chip is an integer multiple of the sum of the length of one second chip and the spacing between two second chips in one unit.
In one possible implementation, the width of each first chip is an integer multiple of the sum of the width of one second chip and the spacing between two second chips in one unit.
In one possible implementation, the first chip on the first wafer is a system-on-a-chip or a processor chip, and the second chip on the second wafer is a memory chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1A-1B are schematic structural diagrams of a chip stack in the prior art according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a wafer stacking structure according to an embodiment of the present application;
FIG. 3 is a flowchart of a memory refresh method according to an embodiment of the present application;
fig. 4 is a schematic diagram of a memory refresh mode switching process according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the embodiments of the present application.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone.
The terms "first" and "second" and the like in the description of embodiments of the application and in the drawings are used for distinguishing between different objects or between different processes of the same object and not for describing a particular order of objects.
Furthermore, references to the terms "comprising" and "having" and any variations thereof in the description of embodiments of the present application are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed but may optionally include other steps or elements not listed or inherent to such process, method, article, or apparatus.
It should be noted that in the description of the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
To meet the functional requirements of the hardware device, a plurality of chips with different functions are usually disposed inside the electronic device. Thus, in integrated circuit fabrication, multiple different types of chips, such as logic, memory, communication, or sensing, need to be stacked together to achieve greater performance and functionality. Referring to fig. 1A, fig. 1A is a stacking manner between chips provided in the prior art. The chip stacking method shown in fig. 1A is a chip-on-wafer (CoW) stacking method. In the stacking manner, the wafer B is first diced, and the chips on the wafer B are diced into a plurality of independent chips j. Then, a plurality of independent chips j are stacked on each chip on the wafer a one by one through a plurality of bonding processes, that is, only one chip j is bonded with one chip on the wafer B in alignment during each bonding. As can be seen from fig. 1A, in the above-mentioned CoW stacking manner, firstly, the wafer B needs to be cut, and secondly, multiple bonding processes are required to bond the chips j on the wafer B and the chips on the wafer a together in a one-to-one alignment manner. This increases the process flow and cost of the chip stack and reduces the yield of the chip stack.
In order to reduce the process flow of chip stacking, please continue to refer to fig. 1B, fig. 1B is a schematic diagram of another stacking method between chips in the prior art according to an embodiment of the present application. The die stacking method shown in fig. 1B is a Wafer-to-Wafer (WoW) stacking method. In this stacking approach, the entire wafer a and wafer B are stacked together, i.e., the die on wafer a and the die on wafer B are bonded in one-to-one precise alignment, by through-silicon via (Through Silicon Via, TSV) interconnect technology. In such an implementation, in order to improve the accuracy of alignment between the chips on the wafer a and the wafer B, the wafer a and the wafer B are generally required to be designed to have the same size, and in addition, the size of the chips in the wafer a and the size of the chips in the wafer B are required to be designed to have the same size, and the positions of the chips in the wafer a and the positions of the chips in the wafer B are required to be designed to have the same size. In some scenarios, for example, stacking between Memory Die (Memory Die) and system-on-chip (SOC Die), since the system-on-chip includes various sizes, in order to meet the WoW stacking method, it is necessary to design and produce various size types of Memory wafers to match the different size types of system-on-chip. This results in the need to design, fabricate, test and maintain multiple sets of memory chips, which increases the cost of the process flow, chip stacking.
In summary, in the chip stacking manner in the prior art, both the CoW stacking manner and the WoW stacking manner increase the process flow and increase the chip stacking cost. According to the chip stacking mode provided by the embodiment of the application, the sizes of the chips on the first wafer are set to be integral multiples of the sum of the sizes of the chips on the second wafer and the intervals between the chips in the first wafer, and through the constraint relation, no matter how the sizes of the chips on the first wafer are changed, the sizes of one or more chips on the second wafer are the same as the sizes of the chips on the first wafer, namely, one chip on the first wafer can be bonded with one or more chips on the second wafer in an aligned mode at the same time, so that the second wafer does not need to be redesigned, the stacking of the second wafer and the first wafer with various sizes can be met, the technological process and the cost of chip stacking can be reduced, and the efficiency of chip stacking can be improved. The multi-wafer stack structure provided by the embodiment of the present application is described in more detail below with reference to the embodiments shown in fig. 2 to 4.
Referring to fig. 2, fig. 2 is a schematic diagram of an arrangement structure of chips on each wafer in the multi-wafer stacking structure according to an embodiment of the application. As shown in fig. 2, the multi-wafer stack structure includes a wafer a and a wafer B. The size of the wafer a is the same as that of the wafer B. The die i on wafer a has a smaller size than the die j on wafer B. In the embodiment of the present application, the chip i on the wafer a may be divided into a plurality of units, and each unit includes the same number of chips i. Wherein i is an integer of 2 or more. The size of one chip j on wafer B is the same as the size of one cell on wafer a. That is, one chip j on the wafer B covers at least two chips i on the wafer B, and at least two chips i covered by each chip j are different.
In the embodiment of the application, the spacing between the chips i in each two units is larger than the spacing between the two chips i in one unit in a plurality of units divided on the wafer B. As shown in fig. 2, on wafer B, the distance between two chips in cell 1 is smaller than the distance between two chips in cell 1 and cell 2, respectively. Furthermore, in one possible implementation, a test circuit is also provided between each two units to test the chip i on the wafer B.
In one possible implementation, the length of the chip j is an integer multiple of the sum of the length of the chip i and the spacing between the two chips i in one unit, and the width of the chip j is an integer multiple of the sum of the width of the chip i and the spacing between the two chips i in one unit.
In one possible implementation, a unit on wafer a may include a chip i, in which case the chips j on wafer B are stacked one-to-one with the chips i on wafer a.
In one possible implementation, the chips in each of the plurality of cells divided by wafer a form an array of M x N. Wherein M is the number of chips i along the row direction, N is the number of chips j along the column direction, and M and N are both positive integers. In addition, in the column direction, the length of the chip i is a, and the interval between two chips is c; in the row direction, the width of the chip i is b, and the spacing between two chips i is d. The length of the die j on the wafer B is m×a+ (M-1) c along the column direction and the width of the die on the wafer B is n×b+ (N-1) d along the row direction, as shown in fig. 3. Fig. 3 schematically shows the dimensions of chip i and of chip j.
With continued reference to fig. 2, fig. 2 shows that every four chips i on wafer a form a 2 x2 array as a unit. One chip j on wafer B is the same size as one unit formed by four chips i on wafer a. That is, M is 2, N is 2, the length of chip j is 2a+c, and the width of chip j is 2b+c.
It should be noted that, ideally, one chip j as shown in fig. 2 covers a chip i of a 2×2 array. In the actual production process, in some cases, due to various problems such as the wafer size, some edges of the wafer a are not provided with the chips i, so that the chips j may cover only three chips i, and the chips j may cover a blank area on the wafer a in addition to the three chips i. In this case, the size of the die j can be considered to be approximately equal to the size of one die unit on wafer a.
As can be seen from the dimensions of the wafer shown in fig. 2 and the die shown in fig. 3, in the embodiment of the present application, the dimension of one die j on the wafer B is set to be the same as the dimension of one unit on the wafer a, so that the die j on the wafer B can be bonded with at least one die i on the wafer a in an aligned manner no matter how the dimension of the die on the wafer B changes, so that the wafer a and the wafer B can be directly bonded, and stacking between the die i and the die j is realized. Therefore, in the multi-wafer stacking structure provided by the embodiment of the application, when the size of the chip on the wafer A is changed, the size of the chip on the wafer B can be matched with the chip on the wafer A without redesigning, so that compared with the prior art shown in fig. 1A, the wafer A is not required to be cut again, and the chip stacking can be realized only by bonding the wafer A and the wafer B, so that the yield of the chip stacking can be reduced; compared with the prior art shown in fig. 1B, it is not necessary to design and produce wafers a of various sizes to match different types of wafers B, and the design and manufacturing cost of the wafers a can be reduced.
In fig. 2, a die j on wafer B is shown, which is the same size as a cell of a 2x 2 array formed by four die i on wafer a. In other possible implementations, one chip i on the wafer a is a unit, and one chip j on the wafer B may also have the same size as one chip i on the wafer a; in addition, two chips i on the wafer B are one unit, and one chip j on the wafer B may also have the same size as one unit formed by two chips i on the wafer a. With continued reference to fig. 4, fig. 4 is a schematic diagram of a relative positional relationship between a chip i on a wafer a and a chip j on a wafer B according to another embodiment of the application. Wherein fig. 4 is a top view. As shown in fig. 4, every three chips i on wafer a form a unit, and the three chips form an array 1*3. One chip j on wafer B is the same size as one unit formed by three chips i on wafer a. That is, M is 3, N is 1, the length of chip j is 3a+2c, and the width of chip j is b.
The bonding relation between the chips on the polycrystalline wafer provided by the embodiment of the application can be applied to various chips. For example, as shown in fig. 2 to 4, the wafer a may be a memory wafer, and the chips on the memory wafer are memory chips. The memory chip may include, but is not limited to: a cache (cache) chip, a random access Memory (Random Access Memory, RAM) chip, a Read Only Memory (ROM) chip, or other Memory chip. As shown in fig. 2-4, wafer a may be a system-on-a-chip or a processor chip, which may include, but is not limited to: application processing (Application Processor, AP) chips, micro-Electro-MECHANICAL SYSTEM, MEMS chips, microwave radio frequency chips, application specific integrated circuit (ApplicationSpecific Integrated Circuit, ASIC) chips, and the like. The application processing chip or application specific integrated circuit chip may be a central processing unit (Central Processing Unit, CPU) chip, an image processing unit (Graphics Processing Unit, GPU) chip, an artificial intelligence processor chip, such as a neural network processor (Network Processing Unit, NPU) chip, etc. in a specific application.
In the embodiment of the application, the chips on the wafer a and the chips on the wafer B shown in fig. 2 to 4 can be stacked together by adopting standard processes such as etching, bonding and the like. Specifically, a die i with through silicon vias (TSV, through Silicon Via) may be first fabricated on a silicon substrate to form wafer a; a chip j with TSVs is fabricated on another silicon substrate to form wafer B. Then, the wafer a is aligned with the wafer B based on the principle that the length of the chip j is an integer multiple of the sum of the length of the chip i and the spacing between the two chips i, and the width of the chip j is an integer multiple of the sum of the width of the chip i and the spacing between the two chips i, and finally, the chips on the wafer a and the chips on the wafer B are bonded by using a wafer bonding process, so that the chip j and at least one chip i are stacked together.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A multi-wafer stack structure, comprising:
A first wafer comprising a plurality of first chips;
A second wafer including a plurality of second chips;
The plurality of second chips are divided into a plurality of units, each unit comprises at least two second chips with the same number, each first chip in the plurality of first chips is stacked corresponding to the second chip in each unit in the plurality of units, and each first chip covers the second chip of one unit;
wherein the size of each first chip is the same as the size of one unit on the second wafer.
2. The multi-wafer stack structure of claim 1, wherein the length of each first chip is an integer multiple of the sum of the length of one second chip and the spacing between two second chips in one unit.
3. The multi-wafer stack structure according to claim 1 or 2, wherein the width of each of the first chips is an integer multiple of the sum of the width of one second chip and the pitch between two second chips in one unit.
4. The multi-wafer stack structure of claim 1, wherein each unit on the second wafer includes second chips arranged in an array, a length of each second chip is a along a column direction of the array, a spacing between every two second chips is c, a length of each first chip along the column direction is M x a+ (M-1) c, wherein a and c are positive numbers, M is an integer greater than or equal to zero, and M is a number of second chips along the column direction.
5. The multi-wafer stack structure of claim 4 wherein each second chip has a width b and a spacing d between every two second chips along a row direction of the array, and each first chip has a width N x b+ (N-1) d along the row direction, wherein b and d are positive numbers, N is an integer greater than or equal to zero, and N is a number of second chips along the row direction.
6. The multi-wafer stack structure of any one of claims 1-5, wherein a first die on the first wafer is a system-on-a-chip or a processor die and a second die on the second wafer is a memory die.
7. A method for preparing a multi-wafer stack structure, comprising:
providing a first substrate, and forming a plurality of first chips on the first substrate to form a first wafer;
providing a second substrate, and forming a plurality of second chips on the second substrate to form a second wafer;
bonding the first wafer and the second wafer in an alignment manner to form the multi-wafer stacking structure;
The plurality of second chips are divided into a plurality of units, each unit comprises at least two second chips with the same number, each first chip in the plurality of first chips is stacked corresponding to the second chip in each unit in the plurality of units, and each first chip covers the second chip of one unit; wherein the size of each first chip is the same as the size of one unit on the second wafer.
8. The method of claim 7, wherein the length of each first chip is an integer multiple of the sum of the length of one second chip and the spacing between two second chips within a unit.
9. The method of claim 7 or 8, wherein the width of each first chip is an integer multiple of the sum of the width of one second chip and the spacing between two second chips within a unit.
10. The method of any of claims 7-9, wherein the first chip on the first wafer is a system-on-a-chip or a processor chip and the second chip on the second wafer is a memory chip.
CN202211397115.XA 2022-11-09 2022-11-09 Multi-wafer stacking structure and preparation method Pending CN118019355A (en)

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CN202211397115.XA CN118019355A (en) 2022-11-09 2022-11-09 Multi-wafer stacking structure and preparation method
PCT/CN2023/105340 WO2024098818A1 (en) 2022-11-09 2023-06-30 Multi-wafer stacked structure and preparation method

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US8493089B2 (en) * 2011-04-06 2013-07-23 International Business Machines Corporation Programmable logic circuit using three-dimensional stacking techniques
CN103985648B (en) * 2014-05-23 2017-01-04 格科微电子（上海）有限公司 The wafer-level packaging method of quasiconductor and semiconductor package part
WO2021081855A1 (en) * 2019-10-30 2021-05-06 华为技术有限公司 Chip package on package structure and packaging method therefor, and electronic device
CN112151444B (en) * 2020-09-28 2023-04-07 武汉新芯集成电路制造有限公司 Matching design method of wafer, wafer bonding structure and chip bonding structure

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