CN118019355A - Multi-wafer stacking structure and preparation method - Google Patents

Abstract

An embodiment of the present application discloses a multi-wafer stacking structure, which includes: a first wafer, the first wafer includes a plurality of first chips; a second wafer, the second wafer includes a plurality of second chips; the plurality of second chips are divided into a plurality of units, each unit includes at least two second chips of the same number, each first chip in the plurality of first chips is stacked correspondingly to the second chip in each unit in the plurality of units, and each first chip covers a second chip in one unit; wherein the size of each first chip is the same as the size of a unit on the second wafer, thereby improving the stacking efficiency between chips with different functions.

Description

Multi-wafer stacking structure and preparation method

Technical Field

The embodiments of the present application relate to the field of semiconductor technology, and in particular to a multi-wafer stacking structure and a preparation method.

Background technique

With the development of technologies such as communications and artificial intelligence, the demand for large amounts of data flow and transfer is increasing. Hardware that supports applications such as 5G and artificial intelligence needs to have functions such as high-speed computing, low latency, multiple bandwidths, and system integration. In order to meet the functional requirements of hardware devices, multiple chips with different functions are usually set up inside electronic devices. Therefore, in the process of integrated circuit manufacturing, multiple different types of chips such as logic, storage, communication, or sensing need to be stacked together to achieve stronger performance and more functions.

Among the current multi-chip stacking methods, the chip-wafer stacking method is usually adopted. That is to say, a certain type of wafer is cut into independent chips, and a bonding process is adopted to align and bond the cut independent chips one by one with the chips on another type of wafer, thereby completing the stacking of chips of different types. When the above-mentioned chip-wafer stacking method is adopted, since the wafer needs to be cut and then the cut chips are set one by one on the wafer to be bonded, this increases the process flow and cost of chip stacking and reduces the yield of chip stacking. Therefore, how to improve the stacking efficiency between chips with different functions becomes a problem that needs to be solved.

Summary of the invention

The multi-wafer stacking structure and preparation method provided in this application can improve the stacking efficiency between chips with different functions. To achieve the above purpose, this application adopts the following technical solutions:

In a first aspect, an embodiment of the present application provides a multi-wafer stacking structure, which includes: a first wafer, wherein the first wafer includes a plurality of first chips; a second wafer, wherein the second wafer includes a plurality of second chips; each first chip among the plurality of first chips is stacked with at least one second chip among the plurality of second chips, and each first chip covers the at least one second chip; the plurality of second chips are divided into a plurality of units, each unit includes at least two second chips of the same number, and each first chip among the plurality of first chips is stacked with a corresponding second chip of each unit among the plurality of units, and each first chip covers a second chip of a unit; wherein a size of each first chip is the same as a size of a unit on the second wafer.

The multi-wafer stacking structure provided in the embodiment of the present application sets the size of the first chip on the first wafer of the two types of wafers to be stacked to be the same as the size of a unit formed by multiple second chips on the second wafer. Through this constraint relationship, no matter how the size of the chip on the first wafer changes, there will always be multiple chips on the second wafer with the same size as the chip on the first wafer, that is, a chip on the first wafer can be aligned and bonded with one or more chips on the second wafer at the same time. In this way, there is no need to redesign the second wafer to meet the need for stacking the second wafer with first wafers of various sizes, thereby reducing the process flow and cost of chip stacking and improving the efficiency of chip stacking.

In the embodiment of the present application, in the plurality of units divided on the second wafer, the interval between the second chips of each two units is greater than the interval between the two chips in one unit. In addition, in a possible implementation, a test circuit is also provided between each two units to test the second chip on the second wafer.

In a possible implementation, the length of each first chip is an integer multiple of the sum of the length of a second chip and the distance between two second chips in a unit.

In a possible implementation, the width of each first chip is an integer multiple of the sum of the width of a second chip and the spacing between two second chips in a unit.

In one possible implementation, each unit on the second wafer includes second chips arranged in an array, and along the column direction of the array, the length of each second chip is a, the spacing between each two second chips is c, and the length of each first chip along the column direction is M*a+(M-1)c, wherein a and c are positive numbers, M is an integer greater than or equal to zero, and M is the number of second chips along the column direction.

In one possible implementation, along the row direction of the array, the width of each second chip is b, the spacing between each two second chips is d, and the width of each first chip along the row direction is N*b+(N-1)d, wherein b and d are positive numbers, N is an integer greater than or equal to zero, and N is the number of second chips along the row direction.

In a possible implementation, the first chip on the first wafer is a system-level chip or a processor chip, and the second chip on the second wafer is a memory chip.

In a second aspect, the present application provides an embodiment of a method for preparing a multi-wafer stacking structure, the method comprising: providing a first substrate, forming a plurality of first chips on the first substrate to form a first wafer; providing a second substrate, forming a plurality of second chips on the second substrate to form a second wafer; aligning and bonding the first wafer and the second wafer to form the multi-wafer stacking structure; the plurality of second chips are divided into a plurality of units, each unit comprising at least two second chips of the same number, each first chip in the plurality of first chips is stacked correspondingly to the second chip in each unit in the plurality of units, and each first chip covers a second chip of a unit; wherein the size of each first chip is the same as the size of a unit on the second wafer.

In a possible implementation, the length of each first chip is an integer multiple of the sum of the length of a second chip and the distance between two second chips in a unit.

In a possible implementation manner, the width of each of the first chips is an integer multiple of the sum of the width of a second chip and the spacing between two second chips in a unit.

In a possible implementation, the first chip on the first wafer is a system-level chip or a processor chip, and the second chip on the second wafer is a memory chip.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

1A-1B are schematic diagrams of the structure of chip stacking in the prior art provided by an embodiment of the present application;

FIG2 is a schematic diagram of a wafer stacking structure provided in an embodiment of the present application;

FIG3 is a schematic diagram of a flow chart of a memory refresh method provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of a memory refresh mode switching process provided in an embodiment of the present application.

Detailed ways

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present application.

The term "and/or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

The terms "first" and "second" and the like in the description and drawings of the embodiments of the present application are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects.

In addition, the terms "including" and "having" and any variations thereof mentioned in the description of the embodiments of the present application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

It should be noted that, in the description of the embodiments of the present application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as having priority or advantage over other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.

In order to meet the functional requirements of hardware devices, multiple chips with different functions are usually set inside electronic devices. Therefore, in the process of integrated circuit manufacturing, it is necessary to stack multiple different types of chips such as logic, storage, communication or sensing together to achieve stronger performance and more functions. Please refer to Figure 1A, which is a chip stacking method provided in the prior art. The chip stacking method shown in Figure 1A is a chip-wafer (CoW, chip on wafer) stacking method. In this stacking method, wafer B is first cut, and the chip on wafer B is cut into multiple independent chips j. Then, through multiple bonding processes, multiple independent chips j are stacked one by one on each chip on wafer A, that is, each time bonding, only one chip j is aligned and bonded with a chip on wafer B. As can be seen from Figure 1A, the above-mentioned CoW stacking method first requires wafer B to be cut, and then multiple bonding processes are required to align and bond the chip j on wafer B with the chip on wafer A one by one. This increases the process flow and cost of chip stacking and reduces the yield of chip stacking.

In order to reduce the process flow of chip stacking, please continue to refer to Figure 1B, which is a structural schematic diagram of another chip stacking method in the prior art provided by the embodiment of the present application. The chip stacking method as shown in Figure 1B is a wafer-wafer (WoW, Wafer on Wafer) stacking method. In this stacking method, the entire wafer A and wafer B are stacked together by silicon through hole (Through Silicon Via, TSV) interconnection technology, that is, the chip on wafer A and the chip on wafer B are precisely aligned and bonded one by one. In this implementation, in order to improve the accuracy of alignment between each chip on wafer A and wafer B, it is generally necessary to design wafer A and wafer B to the same size, and it is also necessary to design the size of the chip in wafer A to the size of the chip in wafer B to the same size, and the position of the chip in wafer A is designed to be the same as the position of the chip in wafer B. In some scenarios, such as stacking memory chips (Memory Die) and system-level chips (SOC Die), since system-level chips include various sizes, in order to meet the above-mentioned WoW stacking method, it is necessary to design and produce memory wafers of various sizes to match system-level chips of different sizes. This leads to the need to design, manufacture, test and maintain multiple sets of memory chips, which increases the process flow and the cost of chip stacking.

From the above, it can be seen that in the chip stacking method of the prior art, whether it is the CoW stacking method or the WoW stacking method, the process flow is increased and the chip stacking cost is increased. The chip stacking method provided in the embodiment of the present application sets the size of the chip on the first wafer of the two types of wafers to be stacked to an integer multiple of the sum of the chip size on the second type of wafer and the spacing between the two chips. Through this constraint relationship, no matter how the size of the chip on the first wafer changes, there will always be one or more chips on the second type of wafer that have the same size as the chip on the first wafer, that is, a chip on the first wafer can be aligned and bonded with one or more chips on the second type of wafer at the same time. In this way, there is no need to redesign the second type of wafer to meet the stacking of the second type of wafer with the first wafer of various sizes, thereby reducing the process flow and cost of chip stacking, and improving the efficiency of chip stacking. The multi-wafer stacking structure provided in the embodiment of the present application is described in more detail below in conjunction with the embodiments shown in Figures 2 to 4.

Please refer to Figure 2, which is a schematic diagram of the arrangement structure of chips on each wafer in the multi-wafer stacking structure provided in an embodiment of the present application. As shown in Figure 2, the multi-wafer stacking structure includes wafer A and wafer B. Among them, the size of wafer A is the same as the size of wafer B. The size of chip i on wafer A is smaller than the size of chip j on wafer B. In an embodiment of the present application, chip i on wafer A can be divided into multiple units, and each unit includes the same number of chips i. Among them, i is an integer greater than or equal to 2. The size of a chip j on wafer B is the same as the size of a unit on wafer A. In other words, a chip j on wafer B covers at least two chips i on wafer B, and at least two chips i covered by each chip j are different.

In the embodiment of the present application, in the multiple units divided on the wafer B, the interval between the chips i between each two units is greater than the interval between the two chips i in one unit. As shown in FIG2 , on the wafer B, the distance between the two chips in unit 1 is less than the distance between the two chips in unit 1 and unit 2, respectively. In addition, in a possible implementation, a test circuit is also provided between each two units to test the chip i on the wafer B.

In one possible implementation, the length of chip j is an integer multiple of the sum of the length of chip i and the spacing between two chips i in a unit, and the width of chip j is an integer multiple of the sum of the width of chip i and the spacing between two chips i in a unit.

In one possible implementation, a unit on wafer A may include a chip i. In this case, chip j on wafer B is stacked with chip i on wafer A in a one-to-one correspondence.

In one possible implementation, in the multiple units divided by wafer A, the chips in each unit form an M*N array. Wherein, M is the number of chips i along the row direction, N is the number of chips j along the column direction, and both M and N are positive integers. In addition, along the column direction, the length of chip i is a, and the spacing between two chips is c; along the row direction, the width of chip i is b, and the spacing between two chips i is d. Then, along the above-mentioned column direction, the length of chip j on wafer B is M*a+(M-1)c, and along the above-mentioned row direction, the width of the chip on wafer B is N*b+(N-1)d, as shown in Figure 3. Figure 3 schematically shows the size of chip i and the size of chip j.

Continuing to refer to FIG. 2 , FIG. 2 shows that every four chips i on wafer A form a unit, and the four chips i form a 2*2 array. A chip j on wafer B has the same size as a unit formed by four chips i on wafer A. That is, M is 2, N is 2, the length of chip j is 2a+c, and the width of chip j is 2b+c.

It should be noted that, ideally, one chip j, as shown in FIG2 , covers the chips i in the 2*2 array. In the actual production process, in some cases, due to various issues such as wafer size, some edges of wafer A are not provided with chips i, and chip j may only cover three chips i. In addition to covering the three chips i, chip j also covers the blank area on wafer A. In this case, it can be considered that the size of chip j is approximately equal to the size of a chip unit on wafer A.

It can be seen from the sizes of the wafers shown in FIG. 2 and the chips shown in FIG. 3 on each wafer that the embodiment of the present application sets the size of a chip j on wafer B to be the same as the size of a unit on wafer A. Therefore, no matter how the size of the chip on wafer B changes, the chip j on wafer B can always be aligned and bonded with at least one chip i on wafer A, so that wafer A and wafer B can be directly bonded to achieve stacking between chip i and chip j. Therefore, in the multi-wafer stacking structure provided by the embodiment of the present application, when the size of the chip on wafer A changes, the size of the chip on wafer B does not need to be redesigned to match the chip on wafer A, so that compared with the prior art shown in FIG. 1A, there is no need to re-cut wafer A, and only wafer A and wafer B need to be bonded to achieve chip stacking, thereby reducing the yield of chip stacking; compared with the prior art shown in FIG. 1B, there is no need to design and produce wafers A of various sizes to match wafers B of different sizes, which can reduce the design and manufacturing cost of wafer A.

FIG2 shows a chip j on wafer B, which is the same size as a unit of a 2*2 array formed by four chips i on wafer A. In other possible implementations, a chip i on wafer A is a unit, and a chip j on wafer B can also be the same size as a chip i on wafer A; in addition, two chips i on wafer B are a unit, and a chip j on wafer B can also be the same size as a unit formed by two chips i on wafer A. Please continue to refer to FIG4, which is a schematic diagram of the relative position relationship between another chip i on wafer A and a chip j on wafer B provided in an embodiment of the present application. Among them, FIG4 is a top view. As shown in FIG4, every three chips i on wafer A form a unit, and the three chips form a 1*3 array. A chip j on wafer B is the same size as a unit formed by three chips i on wafer A. That is to say, M is 3, N is 1, the length of chip j is 3a+2c, and the width of chip j is b.

The bonding relationship between chips on multiple wafers provided in the embodiment of the present application can be applied to a variety of chips. For example, wafer A as shown in Figures 2 to 4 can be a storage wafer, and the chip on the storage wafer is a memory chip. The memory chip may include but is not limited to: a cache chip, a random access memory (Random Access Memory, RAM) chip, a read-only memory (Read Only Memory, ROM) chip or other memory chips. Wafer A as shown in Figures 2 to 4 can be a system-on-chip chip or a processor chip, and the processor chip may include but is not limited to: an application processing (Application Processor, AP) chip, a micro-electro-mechanical system (Micro-Electro-Mechanical System, MEMS) chip, a microwave radio frequency chip, an application-specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC) chip and other chips. The above-mentioned application processing chip or application-specific integrated circuit chip can be a central processing unit (Central Processing Unit, CPU) chip, an image processor (Graphics Processing Unit, GPU) chip, an artificial intelligence processor chip, for example, a neural network processor (Network Processing Unit, NPU) chip, etc.

In the embodiment of the present application, standard processes such as etching and bonding can be used to stack the chips on wafer A and the chips on wafer B as shown in Figures 2 to 4. Specifically, a chip i with a through silicon via (TSV) can be first manufactured on a silicon substrate to form wafer A; and a chip j with TSV can be manufactured on another silicon substrate to form wafer B. Then, based on the principle that the length of chip j is an integer multiple of the sum of the length of chip i and the spacing between the two chips i, and the width of chip j is an integer multiple of the sum of the width of chip i and the spacing between the two chips i, wafer A is aligned with wafer B, and finally, the chip on wafer A is bonded to the chip on wafer B using a wafer bonding process, so that chip j is stacked with at least one chip i.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (10)

1. A multi-wafer stacking structure, comprising: A first wafer, wherein the first wafer includes a plurality of first chips; a second wafer, wherein the second wafer includes a plurality of second chips; The plurality of second chips are divided into a plurality of units, each unit includes at least two second chips of the same number, each first chip in the plurality of first chips is stacked correspondingly with the second chip in each unit in the plurality of units, and each first chip covers the second chip of one unit; The size of each of the first chips is the same as the size of a unit on the second wafer. 2 . The multi-wafer stacking structure according to claim 1 , wherein the length of each first chip is an integer multiple of the sum of the length of a second chip and the spacing between two second chips in a unit. 3. The multi-wafer stacking structure according to claim 1 or 2 is characterized in that the width of each first chip is an integer multiple of the sum of the width of a second chip and the spacing between two second chips in a unit. 4. The multi-wafer stacking structure according to claim 1 is characterized in that each unit on the second wafer includes second chips arranged in an array, and along the column direction of the array, the length of each second chip is a, the spacing between each two second chips is c, and the length of each first chip along the column direction is M*a+(M-1)c, wherein a and c are positive numbers, M is an integer greater than or equal to zero, and M is the number of second chips along the column direction. 5. The multi-wafer stacking structure according to claim 4 is characterized in that, along the row direction of the array, the width of each second chip is b, the spacing between every two second chips is d, and the width of each first chip along the row direction is N*b+(N-1)d, wherein b and d are positive numbers, N is an integer greater than or equal to zero, and N is the number of second chips along the row direction. 6 . The multi-wafer stacking structure according to claim 1 , wherein the first chip on the first wafer is a system-level chip or a processor chip, and the second chip on the second wafer is a memory chip. 7. A method for preparing a multi-wafer stacking structure, comprising: Providing a first substrate, and forming a plurality of first chips on the first substrate to form a first wafer; Providing a second substrate, and forming a plurality of second chips on the second substrate to form a second wafer; Aligning and bonding the first wafer and the second wafer to form the multi-wafer stacking structure; Wherein, the multiple second chips are divided into multiple units, each unit includes at least two second chips of the same number, each first chip among the multiple first chips is stacked corresponding to the second chip of each unit among the multiple units, and each first chip covers the second chip of one unit; wherein the size of each first chip is the same as the size of a unit on the second wafer. 8 . The method according to claim 7 , wherein the length of each first chip is an integer multiple of the sum of the length of a second chip and the spacing between two second chips in a unit. 9 . The method according to claim 7 or 8 , wherein the width of each first chip is an integer multiple of the sum of the width of a second chip and the spacing between two second chips in a unit. 10 . The method according to claim 7 , wherein the first chip on the first wafer is a system-on-chip or a processor chip, and the second chip on the second wafer is a memory chip.