CN111696983B - Multi-chip horizontally packaged chip module, wafer structure and processing method - Google Patents
Multi-chip horizontally packaged chip module, wafer structure and processing method Download PDFInfo
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- CN111696983B CN111696983B CN202010587156.XA CN202010587156A CN111696983B CN 111696983 B CN111696983 B CN 111696983B CN 202010587156 A CN202010587156 A CN 202010587156A CN 111696983 B CN111696983 B CN 111696983B
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- 238000003672 processing method Methods 0.000 title abstract description 7
- 239000011241 protective layer Substances 0.000 claims abstract description 6
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 abstract description 5
- 238000004364 calculation method Methods 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 56
- 230000002950 deficient Effects 0.000 description 8
- 238000011161 development Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000007888 film coating Substances 0.000 description 2
- 238000009501 film coating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a multi-chip horizontally packaged chip module, a wafer structure and a processing method, wherein the chip module comprises a first chip and a second chip, the first chip is arranged on a first wafer, the second chip is arranged on a second wafer, the first wafer is adjacent to the second wafer, a first connecting point is arranged on the first chip, a second connecting point is arranged on the first wafer, a third connecting point is arranged on the second wafer, a fourth connecting point is arranged on the second chip, the first connecting point is connected with the second connecting point, the second connecting point is connected with the third connecting point, the third connecting point is connected with the fourth connecting point, and the surfaces of the first chip and the second chip are covered with a protective layer. According to the embodiment of the invention, the plurality of chips are horizontally spread and directly packaged together, so that the volume of the chips is reduced, the distances among different ICs are reduced, and the calculation speed of the chip module is improved. In addition, compared with the vertical stacking package, the chip module has better heat dissipation performance.
Description
Technical Field
The present invention relates to semiconductor integrated circuit technology, and more particularly, to a multi-chip horizontally packaged chip module, a wafer structure and a processing method.
Background
With the demand of electronic products toward higher functionality, higher speed of signal transmission and higher density of circuit elements, the more powerful the integrated circuit chip presents, and the number of matched passive elements is also increased dramatically for consumer electronic products. When electronic products emphasize lightness, thinness and shortness, how to accommodate a large number of electronic components in a limited mounting space has become a technical bottleneck to be solved and overcome by electronic installers. The chip module for packaging a plurality of chips with different functions together to realize stronger functions may be a development trend in a period of time in the future. The volume can be reduced, the distance between different ICs can be reduced, and the calculation speed of the chip can be improved.
In the prior art, a first chip is disposed on a second chip in a face-to-face manner, and the second chip is electrically connected to a circuit board by a bump or wire bonding (wire bonding) manner through a conductive bump as a medium for electrically connecting the chips. This way of stacking packages in the vertical direction is poor in heat dissipation and results in difficulty in reduction of the chip thickness.
Disclosure of Invention
The invention aims to provide a multi-chip horizontally packaged chip module with higher integration level and better heat dissipation, a wafer structure and a processing method.
The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.
According to an aspect of the present invention, there is provided a multi-chip horizontally packaged chip module, including a first chip and a second chip, where the first chip is disposed on a first wafer, the second chip is disposed on a second wafer, the first wafer is adjacent to the second wafer, a first connection point is disposed on the first chip, a second connection point is disposed on the first wafer, a third connection point is disposed on the second wafer, a fourth connection point is disposed on the second chip, the first connection point is connected with the second connection point, the second connection point is connected with the third connection point, the third connection point is connected with the fourth connection point, and surfaces of the first chip and the second chip are covered with a protection layer.
In an embodiment, the first wafer of the chip module includes a chip carrying area and a dicing area, the first chip is disposed in the chip carrying area, the first connection point is disposed on the first chip, and the second connection point is disposed in the dicing area.
In one embodiment, the second connection point of the chip module is 10 μm to 20 μm away from the edge of the first wafer.
In an embodiment, the chip module further includes a third chip, the third chip is disposed on a third wafer, the third wafer is adjacent to the first wafer or the second wafer, a fifth connection point is disposed on the third chip, a sixth connection point is disposed on the third wafer, the fifth connection point is connected with the sixth connection point, the sixth connection point is connected with the second connection point or the fourth connection point, and a protection layer is covered on the surface of the third chip.
According to another aspect of the present invention, there is further provided a wafer structure for multi-chip horizontal package, including a wafer, where the wafer includes a plurality of dies, each die is provided with a chip, each two adjacent dies are in a group, and two dies on each group of dies have different functions and are connected to each other.
In an embodiment, the wafer of the wafer structure is divided into a central area and an edge area, the central area is the largest inscribed square of the wafer, the edge area is the area of the wafer except for the central area, each four chips in the central area form a connection group, and the chips in the connection group are connected in sequence.
According to still another aspect of the present invention, there is also provided a method for processing a chip module for multi-chip horizontal package, including the steps of: wafer production, wafer film coating, forming different chips on adjacent chips through development and etching, connecting the chips on the adjacent chips, doping, detecting defective products, planning cutting routes according to the positions of the defective chips, cutting the wafers, packaging into chip modules and testing.
The embodiment of the invention has the beneficial effects that: through spreading out a plurality of chips horizontally, the chips are directly packaged together, the size of the chips is reduced, the distance between different ICs is also reduced, and the calculation speed of the chip module is improved. In addition, compared with the vertical stacking package, the chip module has better heat dissipation performance.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
The above features and advantages of the present invention will be better understood after reading the detailed description of embodiments of the present disclosure in conjunction with the following drawings. In the drawings, the components are not necessarily to scale and components having similar related features or characteristics may have the same or similar reference numerals.
FIG. 1 is a schematic top view of a multi-chip horizontally packaged chip module according to an embodiment of the invention;
FIG. 2 is a schematic cross-sectional view of a multi-chip horizontally packaged chip module according to an embodiment of the invention;
FIG. 3 is a schematic top view of a multi-chip horizontally packaged chip module according to another embodiment of the invention;
FIG. 4 is a schematic diagram of a wafer structure for multi-chip horizontal package according to the present invention;
FIG. 5 is a schematic illustration of one of the connection sets of FIG. 4;
wherein: 1-a first chip; 2-a second chip; 3-a first wafer; 4-a second wafer; 5-a first connection point; 6-a second connection point; 7-a third connection point; 8-fourth connection point; 9-a protective layer; 10-a third chip; 11-a third wafer; 12-fifth connection point; 13-sixth connection point; 14-wafer; 15-a central region; 16-linked group;
Detailed Description
The invention is described in detail below with reference to the drawings and the specific embodiments. It is noted that the aspects described below in connection with the drawings and the specific embodiments are merely exemplary and should not be construed as limiting the scope of the invention in any way.
As shown in fig. 1 and fig. 2, the embodiment of the invention discloses a multi-chip horizontally packaged chip module, which comprises a first chip 1 and a second chip 2, wherein the first chip 1 is arranged on a first wafer 3, the second chip 2 is arranged on a second wafer 4, the first wafer 3 is adjacent to the second wafer 4, a first connecting point 5 is arranged on the first chip 1, a second connecting point 6 is arranged on the first wafer 3, a third connecting point 7 is arranged on the second wafer 4, a fourth connecting point 8 is arranged on the second chip 2, the first connecting point 5 is connected with the second connecting point 6, the second connecting point 6 is connected with the third connecting point 7, the third connecting point 7 is connected with the fourth connecting point 8, and the surfaces of the first chip 1 and the second chip 2 are covered with a protective layer 9. Through spreading out the first chip 1 and the second chip 2 horizontally and directly packaging them together, the whole volume of the chip module is reduced, the distance between different ICs is also reduced, and the calculation speed of the chip module is improved. In addition, compared with the vertical stacking package, the chip module has better heat dissipation performance.
Specifically, the first wafer 3 includes a chip carrying area and a dicing area, the first chip 1 is disposed in the chip carrying area, the first connection point 5 is disposed on the first chip 1, and the second connection point 6 is disposed in the dicing area. The second connection point 6 is 15 μm from the edge of the first wafer 3.
As shown in fig. 3, in addition to the module with two chips connected, the embodiment of the invention also discloses a three-chip connected chip module, which structurally comprises a first chip 1, a second chip 2, a third chip 10, wherein the third chip 10 is arranged on a third wafer 11, the third wafer 11 is adjacent to the first wafer 3 or the second wafer 4, a fifth connection point 12 is arranged on the third chip 10, a sixth connection point 13 is arranged on the third wafer 11, the fifth connection point 12 is connected with the sixth connection point 13, the sixth connection point 13 is connected with the second connection point 6 or the fourth connection point 8, and the surfaces of the first chip 1, the second chip 2 and the third chip 10 are covered with a protection layer 9.
As shown in fig. 4, the present invention further discloses a wafer structure of multi-chip horizontal package, including a wafer 14, where the wafer 14 includes a plurality of dies, each die is provided with a chip, every two adjacent dies are in a group, and the two dies on each group of dies have different functions and are connected with each other, so that the wafer structure can form the aforementioned multi-chip horizontal package chip module after dicing and packaging.
Preferably, the wafer 14 is divided into a central area 15 and an edge area, as shown in fig. 5, the central area 15 is the largest inscribed square of the wafer 14, the edge area is the area of the wafer 14 except for the central area 15, and the chips in the edge area are connected in pairs. The wafers in the central area 15 form a connection group 16 for every fourth wafer, the chips in the connection group 16 being connected in turn. It is readily understood that the largest inscribed square can contain the largest number of connection sets 16. Compared with the connection of every two, the four-in-one connection mode can reduce the loss caused by defective products. For example, if chip a and chip c are defective, chip b and chip d can form a two-chip packaged chip module. If the connection mode of the chip a and the chip b and the connection mode of the chip c and the chip d are adopted, the chip b and the chip d cannot form a double-chip module at the moment, so that waste is caused.
Correspondingly, the invention also discloses a processing method of the chip module of the multi-chip horizontal package, which comprises the following steps: wafer production, wafer film coating, forming different chips on adjacent chips through development and etching, connecting the chips on the adjacent chips, doping, detecting defective products, planning cutting routes according to the positions of the defective chips, cutting the wafers, packaging into chip modules and testing. The processing method is different from the prior art method in that the chips on the adjacent wafers are different in kind and the adjacent chips are connected with each other, so that a series of chip modules with specific functions can be formed. When cutting, the cutting path can be planned to bypass defective products, and the chip modules are formed as many as possible by utilizing the mutually connected defective products, so that higher yield is realized.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description is of the preferred embodiment of the present application and is not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and scope of the invention.
Claims (1)
1. The utility model provides a chip module of multicore piece level encapsulation which characterized in that: the semiconductor packaging structure comprises a first chip and a second chip, wherein the first chip is arranged on a first wafer, the second chip is arranged on a second wafer, the first wafer is adjacent to the second wafer, a first connecting point is arranged on the first chip, a second connecting point is arranged on the first wafer, a third connecting point is arranged on the second wafer, a fourth connecting point is arranged on the second chip, the first connecting point is connected with the second connecting point, the second connecting point is connected with the third connecting point, the third connecting point is connected with the fourth connecting point, and the surfaces of the first chip and the second chip are covered with a protective layer; the first wafer comprises a chip bearing area and a cutting area, the first chip is arranged in the chip bearing area, the first connecting point is arranged on the first chip, and the second connecting point is arranged in the cutting area; the second connection point is 10-20 mu m away from the edge of the first wafer; the semiconductor chip comprises a first chip, a second chip, a third wafer, a fifth connecting point, a sixth connecting point and a protective layer, wherein the third chip is arranged on the third wafer, the third chip is arranged on the third wafer and adjacent to the first wafer or the second wafer, the third chip is provided with the fifth connecting point, the sixth connecting point is connected with the second connecting point or the fourth connecting point, and the surface of the third chip is covered with the protective layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010587156.XA CN111696983B (en) | 2020-06-24 | 2020-06-24 | Multi-chip horizontally packaged chip module, wafer structure and processing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010587156.XA CN111696983B (en) | 2020-06-24 | 2020-06-24 | Multi-chip horizontally packaged chip module, wafer structure and processing method |
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| CN111696983A CN111696983A (en) | 2020-09-22 |
| CN111696983B true CN111696983B (en) | 2024-03-15 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114253135B (en) * | 2021-12-13 | 2024-03-26 | 深圳智现未来工业软件有限公司 | Chip performance parameter testing method and device based on machine learning |
| CN115881559B (en) * | 2023-01-18 | 2023-09-15 | 中科亿海微电子科技（苏州）有限公司 | FPGA chip, packaging method thereof and substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010026512A (en) * | 1999-09-07 | 2001-04-06 | 윤종용 | Multi chip package |
| WO2010095355A1 (en) * | 2009-02-20 | 2010-08-26 | 昭和電工株式会社 | Method for dicing semiconductor wafer |
| CN101964313A (en) * | 2010-08-16 | 2011-02-02 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method |
| CN102832189A (en) * | 2012-09-11 | 2012-12-19 | 矽力杰半导体技术(杭州)有限公司 | Multi-chip packaging structure and multi-chip packaging method |
| CN104201168A (en) * | 2014-09-16 | 2014-12-10 | 山东华芯半导体有限公司 | Wafer level package unit with chips stacked obliquely and package method |
| CN107039426A (en) * | 2015-10-19 | 2017-08-11 | 飞思卡尔半导体公司 | Integrated circuit and device with transistor unit staggeredly, and its manufacture method |
| CN107546205A (en) * | 2016-06-28 | 2018-01-05 | 格罗方德半导体公司 | The tampering detection of chip package |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5635247B2 (en) * | 2009-08-20 | 2014-12-03 | 富士通株式会社 | Multi-chip module |
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- 2020-06-24 CN CN202010587156.XA patent/CN111696983B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010026512A (en) * | 1999-09-07 | 2001-04-06 | 윤종용 | Multi chip package |
| WO2010095355A1 (en) * | 2009-02-20 | 2010-08-26 | 昭和電工株式会社 | Method for dicing semiconductor wafer |
| CN101964313A (en) * | 2010-08-16 | 2011-02-02 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method |
| CN102832189A (en) * | 2012-09-11 | 2012-12-19 | 矽力杰半导体技术(杭州)有限公司 | Multi-chip packaging structure and multi-chip packaging method |
| CN104201168A (en) * | 2014-09-16 | 2014-12-10 | 山东华芯半导体有限公司 | Wafer level package unit with chips stacked obliquely and package method |
| CN107039426A (en) * | 2015-10-19 | 2017-08-11 | 飞思卡尔半导体公司 | Integrated circuit and device with transistor unit staggeredly, and its manufacture method |
| CN107546205A (en) * | 2016-06-28 | 2018-01-05 | 格罗方德半导体公司 | The tampering detection of chip package |
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