CN111696983B - Multi-chip horizontally packaged chip module, wafer structure and processing method - Google Patents

Abstract

The invention discloses a multi-chip horizontally packaged chip module, a wafer structure and a processing method. The chip module includes a first chip and a second chip. The first chip is arranged on the first wafer, and the second chip is arranged on the first chip. On the second chip, the first chip is adjacent to the second chip, a first connection point is provided on the first chip, a second connection point is provided on the first chip, a third connection point is provided on the second chip, and the first connection point is provided on the first chip. The second chip is provided with a fourth connection point, the first connection point is connected to the second connection point, the second connection point is connected to the third connection point, the third connection point is connected to the fourth connection point, the first chip and the second chip The surface is covered with a protective layer. By spreading multiple chips horizontally and directly packaging them together, embodiments of the present invention reduce the size of the chips, reduce the distance between different ICs, and increase the computing speed of the chip module. In addition, compared with vertical stacking packaging, this chip module has better heat dissipation performance.

Description

Chip modules, wafer structures and processing methods for multi-chip horizontal packaging

Technical field

The present invention relates to semiconductor integrated circuit technology, and in particular, to a multi-chip horizontally packaged chip module, a wafer structure and a processing method.

Background technique

As the demand for electronic products moves toward higher functionality, faster signal transmission, and higher density of circuit components, integrated circuit chips are becoming more and more powerful, and for consumer electronics products, the number of passive components used has also increased dramatically. . As electronic products emphasize being thin, light and compact, how to accommodate a large number of electronic components in a limited installation space has become a technical bottleneck that electronic installation industry operators urgently need to solve and overcome. Packaging multiple chips with different functions together to realize chip modules with stronger functions may be a development trend in the future. This can not only reduce the size, but also reduce the distance between different ICs and increase the computing speed of the chip.

The existing multi-chip packaging technology mainly arranges the first chip on the second chip in a face-to-face manner, and uses conductive bumps as the medium for electrical connection between the chips, and the above-mentioned third chip The second chip will be electrically connected to the circuit board through bumps or wire bonding. This way of stacking packages in the vertical direction has poor heat dissipation and makes it difficult to reduce the chip thickness.

Contents of the invention

The object of the present invention is to provide a multi-chip horizontally packaged chip module, a wafer structure and a processing method with higher integration and better heat dissipation.

A brief overview of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all contemplated aspects and is intended to neither identify key or critical elements of all aspects nor attempt to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

According to an aspect of the present invention, a multi-chip horizontally packaged chip module is provided, including a first chip and a second chip. The first chip is disposed on the first wafer, and the second chip is disposed on the second chip. On the wafer, the first wafer is adjacent to the second wafer, a first connection point is provided on the first chip, a second connection point is provided on the first wafer, and a second connection point is provided on the second wafer. There is a third connection point, a fourth connection point is provided on the second chip, the first connection point is connected to the second connection point, and the second connection point is connected to the third connection point, so The third connection point is connected to the fourth connection point, and the surfaces of the first chip and the second chip are covered with a protective layer.

In one embodiment, the first chip of the chip module includes a chip carrying area and a cutting area, the first chip is disposed in the chip carrying area, and the first connection point is disposed in the first On the chip, the second connection point is disposed in the cutting area.

In one embodiment, the second connection point of the chip module is 10 μm˜20 μm away from the edge of the first chip.

In one embodiment, the chip module further includes a third chip, the third chip is disposed on a third wafer, the third wafer is adjacent to the first wafer or the second wafer, and the third wafer is adjacent to the first wafer or the second wafer. A fifth connection point is provided on the third chip, a sixth connection point is provided on the third chip, the fifth connection point is connected to the sixth connection point, and the sixth connection point is connected to the second connection point. point or the fourth connection point, and the surface of the third chip is covered with a protective layer.

According to another aspect of the present invention, a multi-chip horizontally packaged wafer structure is also provided, including a wafer. The wafer includes several wafers. Each of the wafers is provided with a chip, and each two phases Adjacent wafers are a group, and the two chips on each group of wafers have different functions and are connected to each other.

In one embodiment, the wafer of the wafer structure is divided into a central area and an edge area. The central area is the largest inscribed square of the wafer, and the edge area is the largest inscribed square of the wafer. In the area other than the central area, every four wafers in the central area form a connection group, and the chips in the connection group are connected in sequence.

According to another aspect of the present invention, a multi-chip horizontally packaged chip module processing method is also provided, including the following steps: wafer production, wafer coating, and forming different chips on adjacent wafers through development and etching. , connecting chips on adjacent wafers, doping, detecting defective products, planning cutting routes according to the position of good wafers, cutting wafers, packaging into chip modules, and testing.

The beneficial effects of the embodiments of the present invention are: by spreading multiple chips horizontally and directly packaging them together, the size of the chips is reduced, the distance between different ICs is also reduced, and the calculation speed of the chip module is improved. In addition, compared with vertical stacking packaging, this chip module has better heat dissipation performance.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present invention more clearly, the drawings required to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and therefore do not It should be regarded as a limitation of the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without exerting creative efforts.

The above-described features and advantages of the present invention can be better understood after reading the detailed description of the embodiments of the present disclosure in conjunction with the following drawings. In the drawings, components are not necessarily drawn to scale, and components with similar related properties or characteristics may have the same or similar reference numerals.

Figure 1 is a schematic top view of a multi-chip horizontally packaged chip module according to an embodiment of the present invention;

Figure 2 is a schematic cross-sectional view of a multi-chip horizontally packaged chip module according to an embodiment of the present invention;

3 is a schematic top view of a multi-chip horizontally packaged chip module according to another embodiment of the present invention;

Figure 4 is a schematic diagram of the wafer structure of multi-chip horizontal packaging of the present invention;

Figure 5 is a schematic diagram of a connection group in Figure 4;

Among them: 1-first chip; 2-second chip; 3-first wafer; 4-second wafer; 5-first connection point; 6-second connection point; 7-third connection point; 8-th Four connection points; 9-protective layer; 10-third chip; 11-third wafer; 12-fifth connection point; 13-sixth connection point; 14-wafer; 15-center area; 16-connection group;

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. Note that the aspects described below in conjunction with the drawings and specific embodiments are only exemplary and should not be construed as any limitation on the scope of the present invention.

As shown in Figures 1 and 2, an embodiment of the present invention discloses a multi-chip horizontally packaged chip module, which includes a first chip 1 and a second chip 2. The first chip 1 is disposed on the first wafer 3. The two chips 2 are arranged on the second wafer 4. The first wafer 3 is adjacent to the second wafer 4. The first chip 1 is provided with a first connection point 5, and the first wafer 3 is provided with a second connection point 6. The second wafer 4 is provided with a third connection point 7, the second chip 2 is provided with a fourth connection point 8, the first connection point 5 is connected to the second connection point 6, and the second connection point 6 is connected to the third connection point 7 , the third connection point 7 is connected to the fourth connection point 8, and the surfaces of the first chip 1 and the second chip 2 are covered with a protective layer 9. By spreading the first chip 1 and the second chip 2 horizontally and directly packaging them together, the overall volume of the chip module is reduced, the distance between different ICs is also reduced, and the calculation speed of the chip module is improved. In addition, compared with vertical stacking packaging, this chip module has better heat dissipation performance.

Specifically, the first wafer 3 includes a chip carrying area and a cutting area, the first chip 1 is arranged in the chip carrying area, the first connection point 5 is arranged on the first chip 1, and the second connection point 6 is arranged in the cutting area. . The second connection point 6 is 15 μm away from the edge of the first wafer 3 .

As shown in Figure 3, in addition to a module with two connected chips, an embodiment of the present invention also discloses a three-chip connected chip module. Its structure includes a first chip 1, a second chip 2, and a third chip. 10. The third chip 10 is disposed on the third wafer 11. The third wafer 11 is adjacent to the first wafer 3 or the second wafer 4. The third chip 10 is disposed with a fifth connection point 12. The third wafer 11 is disposed with a fifth connection point 12. There is a sixth connection point 13, the fifth connection point 12 is connected to the sixth connection point 13, the sixth connection point 13 is connected to the second connection point 6 or the fourth connection point 8, the first chip 1, the second chip 2 and the The surfaces of the three chips 10 are all covered with protective layers 9 .

As shown in Figure 4, the present invention also discloses a multi-chip horizontally packaged wafer structure, including a wafer 14. The wafer 14 includes several wafers, each wafer is provided with a chip, and every two adjacent wafers are As a group, the two chips on each group of wafers have different functions and are connected to each other. Such a wafer structure can form the aforementioned multi-chip horizontally packaged chip module after cutting and packaging.

Preferably, the wafer 14 is divided into a central area 15 and an edge area. As shown in FIG. 5 , the central area 15 is the largest inscribed square of the wafer 14 , and the edge area is the area of the wafer 14 except the central area 15 . Just connect the chips in the area two by two. Every four wafers in the central area 15 form a connection group 16, and the chips in the connection group 16 are connected in sequence. It is easy to understand that the largest inscribed square can contain the most connected groups 16. Compared with two-by-two connection, the connection method of four groups can reduce the losses caused by defective products. For example, if chip a and chip c are defective products, chip b and chip d can form a two-chip packaged chip module. If chip a is connected to chip b, and chip c is connected to chip d, neither chip b nor chip d can form a two-chip module at this time, resulting in waste.

Correspondingly, the present invention also discloses a multi-chip horizontally packaged chip module processing method, which includes the following steps: wafer production, wafer coating, forming different chips on adjacent wafers through development and etching, and converting the phases into Chip connection, doping, defective product detection on adjacent wafers, cutting route planning based on the position of good wafers, wafer cutting, packaging into chip modules, and testing. The difference between this processing method and the existing process method is that the chips on adjacent wafers are of different types, and the adjacent chips are connected to each other, so that a series of chip modules with specific functions can be formed. When cutting, the cutting path can be planned to avoid defective products, and interconnected good products can be used to form as many chip modules as possible to achieve a higher output rate.

Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on its differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The above are only preferred examples of this application and are not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included in the protection of this application. within the range.

Claims (1)

1. A multi-chip horizontally packaged chip module, characterized by: including a first chip and a second chip, the first chip being disposed on the first wafer, and the second chip being disposed on the second wafer, The first wafer is adjacent to the second wafer, a first connection point is provided on the first chip, a second connection point is provided on the first wafer, and a third connection point is provided on the second wafer. connection point, the second chip is provided with a fourth connection point, the first connection point is connected to the second connection point, the second connection point is connected to the third connection point, and the third connection point The connection point is connected to the fourth connection point, and the surfaces of the first chip and the second chip are covered with a protective layer; the first wafer includes a chip carrying area and a cutting area, and the first chip is arranged on the chip carrying area. In the area, the first connection point is arranged on the first chip, and the second connection point is arranged in the cutting area; the second connection point is 10 μm to 20 μm away from the edge of the first wafer; It also includes a third chip, the third chip is disposed on a third wafer, the third wafer is adjacent to the first wafer or the second wafer, and a fifth connection point is provided on the third chip, so A sixth connection point is provided on the third wafer, the fifth connection point is connected to the sixth connection point, the sixth connection point is connected to the second connection point or the fourth connection point, and the third connection point is connected to the second connection point or the fourth connection point. The surface of the three chips is covered with a protective layer.