CN118018020A - DAC error calibration method for pipelined ADC - Google Patents

Abstract

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a DAC error calibration method of a pipelined ADC; the method comprises the steps of obtaining the sampling data quantity of a pipeline ADC in a single period, and solving an output codeword set of each sampling data in the pipeline ADC; calculating first-stage unamplified residual differences of each sampled data according to the output codeword set, wherein each first-stage unamplified residual difference and the corresponding sampled data form a group of sampled point data; constructing an MDAC transmission curve according to a plurality of groups of sampling point data, and dividing subintervals of the MDAC transmission curve according to the sampling point data; calculating the subinterval offset of each subinterval, and compensating the digital output of the analog input in the same period according to the subinterval offset; the invention effectively improves the performance of the pipelined ADC.

Description

DAC error calibration method for pipelined ADC

Technical Field

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a DAC error calibration method of a pipelined ADC.

Background

The analog-to-digital converter (Analog to Digital Convertor) is a bridge connecting the analog world and the digital world, is a particularly important chip in a modern communication system, and is widely used in the fields of multimedia, automation, communication, instruments and equipment and the like. With the rapid increase of data information processing, the requirements of various fields on ADC performance indexes are also higher and higher. High speed, high precision and low power consumption are the hot research targets of the ADC in recent years, and pipeline ADC is the main stream of research at present because the pipeline ADC is more prominent in the trade-off of speed, precision, power consumption and other performances. The pipeline ADC has the effects of non-ideal factors such as sampling capacitance mismatch, charge injection effect, limited gain of the interstage amplifier, offset of the comparator and the like, so that the pipeline ADC is difficult to reach the performance index originally designed. In order to reduce the impact of these non-ideal factors on the pipeline ADC performance and improve the overall pipeline ADC performance, calibration techniques are required to calibrate errors caused by the non-ideal factors in the pipeline ADC.

Calibration of the ADC is largely divided into digital domain calibration and analog domain calibration. Calibration in the analog domain requires calibration of the ADC by adding additional analog circuitry, which increases the design complexity of the analog circuitry. The digital calibration algorithm extracts error information from the digital code output by the ADC without adding an analog circuit module, and compensates the result in the digital domain. Compared with an analog calibration algorithm, the digital calibration algorithm has smaller power consumption, higher anti-interference capability and better portability. Digital domain calibration typically includes capacitive mismatch calibration and operational amplifier nonlinear calibration, and conventional digital calibration algorithms typically use Pseudo-random Noise (PN) sequences or Least Mean Squares (LMS) algorithms. Both calibration methods can achieve good calibration results. But the method of injecting the pseudo-random noise sequence reduces the dynamic input range of the ADC and the convergence time of the extraction error is long. And the LMS algorithm needs to add a reference ADC in the analog domain, so that the resource waste of an analog circuit is increased.

Disclosure of Invention

The method aims to solve the problems of reduced overall performance of the ADC caused by DAC errors of the pipelined ADC and complex analog circuits existing in the traditional calibration technology; the invention provides a DAC error calibration method of a pipelined ADC, in the method, N-1 pipelined ADC sub-stages and 1 flash memory ADC are sequentially cascaded to form the pipelined ADC, wherein each pipelined ADC sub-stage comprises a sampling hold circuit, a sub-ADC, a sub-DAC, a subtracter and a residual amplifier; the DAC error calibration process for the pipelined ADC comprises the following steps:

s1, acquiring the sampling data quantity of a pipeline ADC in a single period, and solving an output codeword set of each sampling data in the pipeline ADC;

S2, calculating first-stage unamplified residual differences of each sampled data according to the output codeword set, wherein each first-stage unamplified residual difference and the corresponding sampled data form a group of sampled point data;

s3, constructing an MDAC transmission curve according to a plurality of groups of sampling point data, and dividing subintervals of the MDAC transmission curve according to the sampling point data;

S4, calculating the subinterval offset of each subinterval, and compensating the digital output of the analog input in the same period according to the subinterval offset.

The invention has the beneficial effects that:

The invention provides a DAC error calibration algorithm of a pipeline ADC based on MDAC subinterval offset detection, which does not need to add an additional analog circuit, only needs to count digital output of an analog end, extracts relevant error parameters through a calibration module, realizes the DAC error calibration of a first stage, and effectively improves the performance of the pipeline ADC.

Drawings

FIG. 1 is a schematic diagram of a conventional pipelined ADC;

FIG. 2 is a flow chart of a DAC error calibration algorithm of the pipelined ADC of the present invention;

FIG. 3 is a MDAC-output transfer curve of a 3bit with redundant sub-level ADC of the present invention;

FIG. 4 is a graph of the ADC-output transfer curve of the first stage of the pipelined ADC with DAC errors of the present invention;

FIG. 5 is a schematic diagram illustrating the MDAC subinterval offset detection according to the present invention;

Fig. 6 is a comparison plot of the FFT of the present invention, wherein (a) is a plot of the FFT analysis of the DAC error of an uncalibrated first-stage pipelined ADC and (b) is a plot of the FFT analysis after calibrating the first-stage DAC error of the pipelined.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The invention employs a 14bit pipelined ADC as shown in fig. 1, comprising a front N-1 stage pipelined ADC Sub-stage (with one bit redundancy per stage) and a KN bit flash ADC of the nth stage, wherein each pipelined ADC Sub-stage comprises a sample and hold circuit (S/H), a Sub-ADC (Sub-ADC), a Sub-DAC (Sub-DAC), a subtractor and a Residual Amplifier (RA); the ith pipelined ADC sub-stage is Ki (i is more than or equal to 1 and less than or equal to N-1, i is a positive integer, and N is an integer greater than 1) bit, and the pipelined ADC can realizeDigital output of bit precision; since the DAC error of the first pipelined ADC sub-stage has the greatest effect on the performance of the overall pipelined ADC; it is necessary to correct the DAC error of the first pipelined ADC sub-stage.

The invention provides a DAC error calibration method of a pipelined ADC, as shown in figure 2, comprising the following steps:

S1, acquiring the sampling data quantity of the pipeline ADC in a single period, and solving an output codeword set of each sampling data in the pipeline ADC.

Specifically, setting the sampling data amount of the pipelined ADC in a single period as M, and inputting the m=1, 2, … th sampling data into the pipelined ADC to obtain the output code word of each pipelined ADC sub-stage and the flash ADC at the moment, wherein the output code word obtaining process of the M-th sampling data in the i, i=1, 2, …, N-1 th pipelined ADC sub-stages includes:

S11, an input signal passes through a sampling hold circuit of an ith pipelined ADC sub-stage to obtain a sampling signal;

S12, inputting a sampling signal into a sub-ADC of an ith pipelined ADC sub-stage to obtain an ith stage output codeword Dout _m (i);

S13, inputting an i-th output codeword Dout _m (i) into a sub-DAC of an i-th pipelined ADC sub-stage to obtain an i-th analog quantity V _{daci_m};

S14, carrying out residual operation on the sampling signal and the ith analog quantity V _{daci_m} to obtain an output V _{oi_m} of the ith pipelined ADC sub-stage, wherein the output V _{oi_m} is used as an input signal of the (i+1) th pipelined ADC sub-stage.

Specifically, residual operation is performed on the sampling signal and the ith analog quantity V _{daci_m} to obtain an output V _{oi_m} of the ith pipelined ADC sub-stage, wherein the residual operation formula is as follows:

V_{oi_m}＝(V_{ini_m}-V_{daci_m})×Gi

Where V _{ini_m} represents the sample signal of the mth sample data at the ith pipelined ADC sub-stage, gi represents the inter-stage gain of the ith pipelined ADC sub-stage.

For the mth sampling data, the operations of steps S11-S14 are executed in each pipelined ADC sub-stage, and then the output V _{oN-1_m} of the N-1 th pipelined ADC sub-stage is input to the final flash ADC to obtain the output codeword Dout _m (N) of the flash ADC, so as to complete the analog-to-digital conversion of the mth sampling data, and obtain the corresponding output codeword set { Dout _m(1),Dout_m(2),…,Dout_m (N) }.

S2, calculating first-stage unamplified residual differences of each sampled data according to the output codeword set, wherein each first-stage unamplified residual difference and the corresponding sampled data form a group of sampled point data.

Specifically, each analog input has N output code words through the pipeline ADC, each output code word is multiplied by the weight of its corresponding pipeline ADC sub-stage, and then all the multiplication results are added to obtain the digital output of the analog input in the whole pipeline ADC (the digital output at this time is error-containing); therefore, the invention removes the multiplication result of the first output code word and the weight of the corresponding pipelined ADC sub-stage to obtain the first-stage unamplified residual of the analog input (the first-stage unamplified residual also contains errors).

Specifically, step S2 calculates the first-stage unamplified residual of the mth sampling data according to the output codeword set, where the calculation formula is:

Where V _{res_cal1} (m) represents the first-stage unamplified residual of the mth sample data, dout _m (i) represents the output codeword of the mth sample data at the ith pipelined ADC sub-stage, and w (i) represents the weight of the ith pipelined ADC sub-stage.

S3, constructing an MDAC transmission curve according to the plurality of groups of sampling point data, and dividing subintervals of the MDAC transmission curve according to the sampling point data.

Specifically, according to the sampling point data, the functional relation between the analog input (i.e. the sampling data) and the unamplified residual error of the first stage can be obtained, so that the MDAC transmission curve corresponding to the first pipelined ADC sub-stage is constructed according to the plurality of groups of sampling point data. The MDAC transmission curve acquired according to M groups of discrete sampling point data can be divided into a plurality of sections of subintervals, and each subinterval can deviate to different degrees in the vertical direction due to different DAC errors; the invention searches the obvious jump point on the MDAC transmission curve, then divides the MDAC transmission curve into subintervals according to the jump point, and then obtains the offset of the subintervals to carry out subsequent correction, thereby reducing the calculated amount and ensuring the correction precision.

Specifically, step S3 performs subinterval division on the MDAC transmission curve according to the sampling point data, including:

S31, calculating the difference value between the first-stage unamplified residual differences of every two adjacent sampled data to obtain M-1 difference values;

Specifically, the calculation formula of the difference between the first-stage unamplified residual of each two adjacent sampled data is:

V_d(a)＝G1×(V_{res_cal1}(a)-V_{res_cal1}(a+1))，a＝1,2,…,M-1

Where V _{res_cal1} (a) represents the first stage unamplified residual of the a-th sampled data, G1 represents the interstage gain of the 1 st pipelined ADC sub-stage, and V _d (a) represents the a-th difference.

S32, updating each difference value according to a preset threshold rule, screening all non-zero difference values, selecting one jumping point according to each non-zero difference value, and recording the number of the jumping points as k is less than or equal to M-1;

specifically, the preset threshold rule is expressed as:

Where V _d (a) represents the a-th difference and V _th represents the threshold.

Specifically, selecting a trip point according to any non-zero difference value includes: and determining two first-stage unamplified residual differences for calculating the non-zero difference value, and determining the sampling data corresponding to the former one of the two first-stage unamplified residual differences as a jump point. Assuming that V _d (a) noteq0, the equation V _d(a)＝G1×(V_{res_cal1}(a)-V_{res_cal1} (a+1) is used, the sampling data a corresponding to V _{res_cal1} (a) is used as the trip point x (j), j=1, 2, …, k, i.e., x (j) =a.

S33, dividing the MDAC transmission curve into k+1 subintervals according to the jump points.

S4, calculating the subinterval offset of each subinterval, and compensating the digital output of the analog input in the same period according to the subinterval offset.

Specifically, step S4 calculates a subinterval offset of each subinterval, corrects each subinterval according to the subinterval offset, and includes:

S41, calculating the subinterval offset of each subinterval;

Specifically, firstly, calculating the subinterval offset of a first subinterval relative to an ideal MDAC transmission curve without errors; as can be seen from the ideal MDAC transmission curve, V _in (min) (i.e., the minimum value of the abscissa of the MDAC transmission curve) should be 0; at this time, subtracting 0 from the multiplication result of the actual first-stage unamplified residual corresponding to V _in (min) and G1 to obtain the subinterval offset of the first subinterval of the MDAC transmission curve, and marking as E (0);

Then, calculating the subinterval offset of the second subinterval of the MDAC transmission curve relative to the first subinterval; the specific method comprises the following steps: calculating the difference between the last V _{res_cal1} (x (1)) of the first subinterval and the first V _{res_cal1} (x (1) +1) of the second subinterval of the MDAC transmission curve; then multiplying the difference by G1 and the reference voltage Vref to obtain a difference, wherein the difference is the relative offset between the second subinterval and the first subinterval of the MDAC transmission curve, and the offset is marked as E (1); similarly, calculating the relative offset of the rest subintervals and the previous subinterval to obtain E (2) -E (k); the calculation formula is that

Where x (1) represents a first trip point, x (k) represents a kth trip point, vref represents a reference voltage, V _{res_cal1} (1) represents a first level unamplified residual at a starting point of a first subinterval (i.e., a first subinterval abscissa minimum) of the MDAC transmission curve, V _{res_cal1} (x (1)) represents a first level unamplified residual at a first trip point (which may also be referred to as a first subinterval ending point, i.e., a first subinterval abscissa maximum), V _{res_cal1} (x (1) +1) represents a first level unamplified residual at a second subinterval starting point (i.e., a second subinterval abscissa minimum) of the MDAC transmission curve,Representing the first-level un-amplified residual value at the end point of the second sub-interval (i.e., the second sub-interval abscissa maximum), the above-mentioned parameters represent and so on.

S42, enabling the k+1 subintervals to correspond to a specific code word respectively;

Specifically, the MDAC transmission curve is divided into k+1 subintervals, where each subinterval corresponds to a specific codeword. In the preferred embodiment of the present invention, k=8, so the MDAC transmission curve is divided into 9 subintervals, and the specific codewords "1111", "0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111" are respectively corresponding to the 1 st-9 subintervals of the MDAC transmission curve; it is also understood that the analog input ranges from-Vref to-Vref, which is subdivided into 9 subintervals, and that the specific codeword "1111" represents an analog input within the range of-Vref to-7/8 Vref.

S43, obtaining a 1 st-stage output code word Dout (1) of analog input in the same period, determining a subinterval k '=1, 2, …, k+1 corresponding to the 1 st-stage output code word Dout (1), and compensating the first-stage output code word Dout (1) according to subinterval offset of the 1 st to k' subintervals to obtain digital output after analog input correction.

Specifically, the invention takes the first subinterval as the reference interval, and starts to correct the offset from the first subinterval until the last subinterval is corrected, thereby realizing the DAC error calibration of the first-stage pipelined ADC sublevel; that is, compensating the level 1 output codeword Dout (1) can be expressed as:

Where V denotes the digital output of the analog input, V _cal denotes the digital output after correction of the analog input, a1, a2, …, a (k+1) denotes the specific codeword corresponding to the 1 st to k+1 th subinterval.

In the preferred embodiment of the present invention, when k=8, if the first-stage output codeword Dout (1) =1111 of the analog input indicates that the 1 st-stage output codeword Dout (1) belongs to the first subinterval, the first-stage output codeword Dout (1) is compensated by E (0)/G1 according to the subinterval offset E (0), and if the first-stage output codeword Dout (1) =0000 of the analog input indicates that the 1 st-stage output codeword Dout (1) belongs to the second subinterval, the 1 st-stage output codeword Dout (1) is compensated by (E (0) +e1) according to the subinterval offsets E (0), E (1); and so on, namely, the compensation of the first-stage output codeword Dout (1) can be expressed as:

In one embodiment, described in connection with the pipelined ADC shown in fig. 1, the ideal value of the digital output of one analog input may be expressed as, for an overall pipelined ADC, without taking into account DAC errors of the first stage pipelined ADC sub-stages:

V＝Dout(1)×w(1)+Dout(2)×w(2)+…+Dout(N)×w(N)

FIG. 3 is a graph of MDAC-output transmission of a first stage pipelined ADC sub-stage of a conventional 14bit pipelined ADC with redundancy. When the first stage pipeline ADC sub-stage of the pipeline ADC contains DAC errors, the phenomenon of vertical offset of the whole sub-section is reflected on the sub-section of the MDAC-output transmission curve. In this ideal MDAC transmission curve, the vertical distance V _d of each trip point should be one V _ref. In reality, due to the DAC error, the vertical distance at each trip point increases or decreases to different extents, so that a corresponding offset is generated on the corresponding ADC-output transmission curve, as shown in fig. 4. The embodiment on the whole pipeline ADC is that the effective digit is reduced and the performance is reduced. Therefore, compensating for the offset caused by DAC error can effectively improve the performance of pipelined ADCs.

Fig. 5 is a schematic diagram of the detection of the MDAC subinterval offset of the first stage of the 14bit pipelined ADC. The difference between the former data G1 x V _{res_cal1} (x) and the latter data G1 x V _{res_cal1} (x+1) (1.ltoreq.x.ltoreq.m-1) is calculated sequentially from left to right. The difference V _d at the transition between adjacent subintervals contains information about the subinterval related DAC error, ideally V _d＝V_ref, if the two data are not equal, the difference is the calculated error. From this we can derive the following relationship:

v _d(x(j))＝V_ref-E(j)＝G1(V_{res_cal1}(x(j))-V_{res_cal1}(x(j)+1))V_d (x (j)) represents the difference at trip point x (j), j=1, 2, …, k.

Performing behavioral level modeling and then calibration on a 14-bit pipelined ADC, wherein the ADC adopts a six-level pipeline structure, the digital quantization bits of the first five levels are 3 bits and all contain one redundancy bit, and the last level Flash ADC is 4 bits. The behavior level of the overall working circuit and calibration circuit is modeled using MATLAB for the 14bit pipeline. In pipelined ADCs, the error of the first stage has the greatest effect on the performance of the pipelined ADC, and the invention only involves calibrating the DAC error of the first stage, with the interstage gain set to the ideal value. First, the first stage unamplified residual V _{res_cal1} is synthesized by the codeword output Dout (i) of each stage. And counting M data of a single period, and analyzing the MDAC transmission curve obtained by the data. Firstly, the division of subintervals is completed, and then the relative offset E (0) -E (8) of each MDAC subinterval is obtained according to the jump points on the MDAC transmission curve. And in the code word synthesis stage, according to different subintervals corresponding to the 1 st-stage output code word of the analog input, carrying out corresponding error compensation on the digital output of the analog input, and completing corresponding digital output calibration to synthesize the final output. Fig. 6 is a diagram showing comparison of FFT analysis of the first stage of the pipelined ADC having DAC errors before calibration (fig. 6 (a)) and after calibration (fig. 6 (b)). It can be seen that the signal-to-noise distortion ratio SNDR increases from 58.28dB to 84.79dB, the spurious-free dynamic range SFDR increases from 61.46dB to 96.93dB, and the effective Bit number increases from 9.39Bit to 13.79Bit.

In summary, the MDAC subinterval offset detection based on the pipelined ADC completes the division of the MDAC subintervals, and realizes the extraction and calibration of DAC error parameters of the MDAC subintervals. The algorithm simplifies the module design of digital calibration, optimizes the digital calibration structure, reduces the use of resources and makes the calibration simpler and more effective. On the basis of not increasing the design complexity of the analog circuit, the accuracy of the calibration coefficient is increased, and the overall performance of the pipelined ADC is improved.

In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "configured," "connected," "secured," "rotated," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with each other or in interaction with each other, unless explicitly defined otherwise, the meaning of the terms described above in this application will be understood by those of ordinary skill in the art in view of the specific circumstances.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (7)

1. A DAC error calibration method of a pipelined ADC is characterized in that N-1 pipelined ADC sub-stages and 1 flash memory ADC are sequentially cascaded to form the pipelined ADC, wherein each pipelined ADC sub-stage comprises a sample hold circuit, a sub-ADC, a sub-DAC, a subtracter and a residual amplifier; the DAC error calibration process for the pipelined ADC comprises the following steps:

s1, acquiring the sampling data quantity of a pipeline ADC in a single period, and solving an output codeword set of each sampling data in the pipeline ADC;

S2, calculating first-stage unamplified residual differences of each sampled data according to the output codeword set, wherein each first-stage unamplified residual difference and the corresponding sampled data form a group of sampled point data;

s3, constructing an MDAC transmission curve according to a plurality of groups of sampling point data, and dividing subintervals of the MDAC transmission curve according to the sampling point data;

S4, calculating the subinterval offset of each subinterval, and compensating the digital output of the analog input in the same period according to the subinterval offset.

2. The method for calibrating a DAC error in a pipelined ADC according to claim 1, wherein setting the amount of sampled data in a single cycle of the pipelined ADC to M, and inputting the M-th=1, 2, … sampled data into the pipelined ADC to obtain the output codeword of each of the pipelined ADC sub-stages and the flash ADC at that time, wherein the output codeword obtaining process of the M-th sampled data in the i-th, i=1, 2, …, N-1 pipelined ADC sub-stages comprises:

S11, an input signal passes through a sampling hold circuit of an ith pipelined ADC sub-stage to obtain a sampling signal;

S12, inputting a sampling signal into a sub-ADC of an ith pipelined ADC sub-stage to obtain an ith stage output codeword Dout _m (i);

S13, inputting an i-th output codeword Dout _m (i) into a sub-DAC of an i-th pipelined ADC sub-stage to obtain an i-th analog quantity V _{daci_m};

S14, carrying out residual operation on the sampling signal and the ith analog quantity V _dacim to obtain an output V _{oi_m} of the ith pipelined ADC sub-stage, wherein the output V _{oi_m} is used as an input signal of the (i+1) th pipelined ADC sub-stage.

3. The method for calibrating DAC error in pipelined ADC according to claim 1, wherein step S2 calculates a first-stage unamplified residual of the mth sample data from the set of output codewords, the calculation formula being:

Where V _{res_cal1} (m) represents the first-stage unamplified residual of the mth sample data, dout _m (i) represents the output codeword of the mth sample data at the ith pipelined ADC sub-stage, and w (i) represents the weight of the ith pipelined ADC sub-stage.

4. The method for calibrating a DAC error of a pipelined ADC as recited in claim 1, wherein step S3 sub-divides the MDAC transmission curve according to the sampling point data, comprising:

S31, calculating the difference value between the first-stage unamplified residual differences of every two adjacent sampled data to obtain M-1 difference values;

S32, updating each difference value according to a preset threshold rule, screening all non-zero difference values, selecting one jumping point according to each non-zero difference value, and recording the number of the jumping points as k is less than or equal to M-1;

S33, dividing the MDAC transmission curve into k+1 subintervals according to the jump points.

5. The method of calibrating a DAC error in a pipelined ADC according to claim 4, wherein the difference between the first-stage unamplified residual of each two adjacent sampled data is calculated by:

V_d(a)＝G1×(V_{res_cal1}(a)-V_{res_cal1}(a+1))，a＝1,2,…,M-1

Where V _{res_cal1} (a) represents the first stage unamplified residual of the a-th sampled data, G1 represents the interstage gain of the 1 st pipelined ADC sub-stage, and V _d (a) represents the a-th difference.

6. The method of calibrating DAC error in a pipelined ADC of claim 4 wherein the predetermined threshold rule is expressed as:

Where V _d (a) represents the a-th difference and V _th represents the threshold.

7. The method for calibrating a DAC error in a pipelined ADC according to claim 1, wherein step S4 calculates a subinterval offset for each subinterval, and correcting each subinterval according to the subinterval offset, comprises:

s41, calculating the subinterval offset of each subinterval according to the following formula:

Wherein x (1) represents a first jump point, x (k) represents a kth jump point, vref represents a reference voltage, and E (0) represents a subinterval offset of the first subinterval; e (k) represents the subinterval offset of the (k+1) th subinterval; v _{res_cal1} (1) represents the first-stage unamplified residual value at the start point of the first subinterval of the MDAC transmission curve, V _{res_cal1} (x (1)) represents the first-stage unamplified residual value at the first trip point, and V _{res_cal1} (x (1) +1) represents the first-stage unamplified residual value at the start point of the second subinterval of the MDAC transmission curve;

S42, enabling the k+1 subintervals to correspond to a specific code word respectively;

S43, obtaining a 1 st-stage output code word Dout (1) of analog input in the same period, determining a subinterval k '=1, 2, …, k+1 corresponding to the 1 st-stage output code word Dout (1), and compensating the first-stage output code word Dout (1) according to subinterval offset of the 1 st to k' subintervals to obtain digital output after analog input correction.