CN118017947A - Current multiplexing amplifier and electronic device - Google Patents
Current multiplexing amplifier and electronic device Download PDFInfo
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- CN118017947A CN118017947A CN202410119899.2A CN202410119899A CN118017947A CN 118017947 A CN118017947 A CN 118017947A CN 202410119899 A CN202410119899 A CN 202410119899A CN 118017947 A CN118017947 A CN 118017947A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
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- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
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Abstract
The application is suitable for the technical field of integrated circuit amplifier design, and provides a current multiplexing amplifier and an electronic device, wherein the current multiplexing amplifier comprises at least two stages of amplifiers, and the at least two stages of amplifiers are sequentially connected in series in the signal input direction; the amplifier connected with the signal input end is a first-stage amplifier, and the amplifier connected with the signal output end is a final-stage amplifier; the power end of the first-stage amplifier is connected with the positive end of the power supply of the amplifier, and the grounding end of the final-stage amplifier is connected with the negative end of the power supply of the amplifier; for the amplifiers of two adjacent stages, the grounding end of the amplifier of the previous stage is connected with the power end of the amplifier of the next stage; the amplifier power supply is used for supplying power to the first-stage amplifier to generate a power supply current; the power supply current flows from the positive end of the power supply of the amplifier, sequentially through at least two stages of amplifiers, flows out from the grounding end of the final stage amplifier, and finally flows back to the negative end of the power supply of the amplifier. The application can effectively improve the linearity of the current multiplexing amplifier.
Description
Technical Field
The application belongs to the technical field of integrated circuit amplifier design, and particularly relates to a current multiplexing amplifier and an electronic device.
Background
In high-frequency circuit systems such as microwaves, radio frequencies, millimeter waves, terahertz waves and the like, in order to reduce the power consumption of the system, an amplifier design technology with the advantage of low power consumption is required. The current multiplexing technology is a widely used low-power amplifier design technology, and is characterized in that two-stage or multi-stage amplifiers share the same current. The gain of the two-stage or three-stage amplifier is realized in an equivalent manner to the power consumption of the one-stage amplifier. Therefore, the current multiplexing technique can realize a high gain and low power consumption amplifier.
In the classical current multiplexing amplifier structure, an amplifier with a two-stage structure is taken as an example for explanation, and after current flows out from the positive end of a power supply, the current flows through the second-stage amplifier, then flows into the first-stage amplifier, and finally flows back to the negative end of the power supply. The overall power consumption of the amplifier is thus determined by the bias state of the first stage amplifier. When the input power of the amplifier is increased to a certain value, the first-stage amplifier is converted from a Class A working mode to a Class AB working mode, and the overall power consumption of the amplifier is increased. Likewise, when the amplifier input power increases to some extent, the second stage amplifier will also switch from a Class a mode to a Class AB mode. If the second stage amplifier is switched from the Class a mode to the Class AB mode prior to the first stage amplifier or if the increase in power consumption caused by the switching of the first stage amplifier from the Class a mode to the Class AB mode is not large enough, the second stage amplifier will immediately enter a gain compression state, resulting in a reduced amplifier linearity. Therefore, the amplifier adopting the classical current multiplexing structure has poor linearity and low output power.
Disclosure of Invention
The embodiment of the application provides a current multiplexing amplifier and an electronic device, which are used for improving the linearity of the whole current multiplexing amplifier.
The application is realized by the following technical scheme:
In a first aspect, an embodiment of the present application provides a current multiplexing amplifier, including: at least two stages of amplifiers, which are sequentially connected in series in a signal input direction; the amplifier connected with the signal input end is a first-stage amplifier, and the amplifier connected with the signal output end is a final-stage amplifier; the power end of the first-stage amplifier is connected with the positive end of the power supply of the amplifier, and the grounding end of the final-stage amplifier is connected with the negative end of the power supply of the amplifier; for the amplifiers of two adjacent stages, the grounding end of the amplifier of the previous stage is connected with the power end of the amplifier of the next stage; the amplifier power supply is used for supplying power to the first-stage amplifier to generate a power supply current; and the power supply current sequentially flows through the at least two stages of amplifiers from the positive end of the power supply of the amplifier, flows out from the grounding end of the final stage amplifier and finally flows back to the negative end of the power supply of the amplifier.
With reference to the first aspect, in some embodiments, the current multiplexing amplifier is a two-stage current multiplexing amplifier, including the first stage amplifier and the final stage amplifier; the grounding end of the first-stage amplifier is connected with the power end of the final-stage amplifier; the power supply current flows into the power supply end of the first-stage amplifier from the positive end of the power supply of the amplifier, flows out of the grounding end of the first-stage amplifier, flows into the power supply end of the final-stage amplifier, flows out of the grounding end of the final-stage amplifier, and finally flows back to the negative end of the power supply of the amplifier.
With reference to the first aspect, in some embodiments, the current multiplexing amplifier further includes an input matching network, an interstage matching network, and an output matching network; the first-stage amplifier is connected with the signal input end through the input matching network and is connected with the final-stage amplifier through the interstage matching network; and the final amplifier is connected with the signal output end through the output matching network.
With reference to the first aspect, in some embodiments, the first stage amplifier includes a first inductor, a first field effect transistor, a second field effect transistor, a third field effect transistor, and a fourth field effect transistor; the final amplifier includes a second inductor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, and an eighth field effect transistor.
One end of the input matching network is connected with one end of the signal input end, the other end of the input matching network is connected with the other end of the signal input end, one end of the output end of the input matching network is connected with the grid electrode of the first field effect transistor, and the other end of the output end of the input matching network is connected with the grid electrode of the second field effect transistor.
The source electrode of the first field effect transistor is connected with one end of the first inductor, and the drain electrode of the first field effect transistor is connected with the source electrode of the third field effect transistor; the source electrode of the second field effect transistor is connected with the other end of the first inductor, and the drain electrode of the second field effect transistor is connected with the source electrode of the fourth field effect transistor; and the grid electrode of the third field effect transistor is connected with the grid electrode of the fourth field effect transistor.
One end of the input end of the inter-stage matching network is connected with the drain electrode of the third field effect transistor, the other end of the input end of the inter-stage matching network is connected with the drain electrode of the fourth field effect transistor, one end of the output end of the inter-stage matching network is connected with the grid electrode of the fifth field effect transistor, and the other end of the output end of the inter-stage matching network is connected with the grid electrode of the sixth field effect transistor.
The source electrode of the fifth field effect transistor is connected with one end of the second inductor, and the drain electrode of the fifth field effect transistor is connected with the source electrode of the seventh field effect transistor; the source electrode of the sixth field effect transistor is connected with the other end of the second inductor, and the drain electrode of the sixth field effect transistor is connected with the source electrode of the eighth field effect transistor; the gate of the seventh field effect transistor is connected to the gate of the eighth field effect transistor.
One end of the input end of the output matching network is connected with the drain electrode of the seventh field effect transistor, the other end of the input end of the output matching network is connected with the drain electrode of the eighth field effect transistor, one end of the output matching network is connected with one end of the signal output end, and the other end of the output matching network is connected with the other end of the signal output end.
The positive end of the amplifier power supply is connected with the input end of the interstage matching network, and the negative end of the amplifier power supply is connected with the center tap of the second inductor; the center tap of the first inductor is grounded, and the center tap of the first inductor is connected with the input end of the output matching network. The power supply current flows out of the positive end of the amplifier power supply, flows through the interstage matching network, flows into the drains of the third field effect transistor and the fourth field effect transistor, flows out of the sources of the first field effect transistor and the second field effect transistor, flows through the first inductor and the output matching network, flows into the drains of the seventh field effect transistor and the eighth field effect transistor, flows out of the sources of the fifth field effect transistor and the sixth field effect transistor, flows through the second inductor, and flows back to the negative end of the amplifier power supply.
With reference to the first aspect, in some embodiments, the input matching network includes a first resistor, a first transformer, and a first capacitor, the inter-stage matching network includes a second transformer and a second resistor, and the output matching network includes a third transformer and a second capacitor. The current multiplexing amplifier further comprises a first bias voltage access terminal, a second bias voltage access terminal, a third bias voltage access terminal, a fourth bias voltage access terminal and a third capacitor.
One end of the input end of the first transformer is connected with one end of the first capacitor and one end of the signal input end, the other end of the input end of the first transformer is connected with the other end of the first capacitor and the other end of the signal input end, one end of the output end of the first transformer is connected with one end of the first resistor and the grid electrode of the first field effect transistor, and the other end of the output end of the first transformer is connected with the other end of the first resistor and the grid electrode of the second field effect transistor.
One end of the input end of the second transformer is connected with the drain electrode of the third field effect transistor, the other end of the input end of the second transformer is connected with the drain electrode of the fourth field effect transistor, one end of the output end of the second transformer is connected with one end of the second resistor and the grid electrode of the fifth field effect transistor, and the other end of the output end of the second transformer is connected with the other end of the second resistor and the grid electrode of the sixth field effect transistor.
One end of the input end of the third transformer is connected with the drain electrode of the seventh field effect transistor, the other end of the input end of the third transformer is connected with the drain electrode of the eighth field effect transistor, one end of the output end of the third transformer is connected with one end of the second capacitor and one end of the signal output end, and the other end of the output end of the third transformer is connected with the other end of the second capacitor and the other end of the signal output end.
The first bias voltage access end is connected with a center tap of the output end of the first transformer; the second bias voltage access terminal is connected with the grid electrode of the third field effect transistor and the grid electrode of the fourth field effect transistor; the third bias voltage access end is connected with a center tap of the output end of the second transformer; the fourth bias voltage access terminal is connected with the grid electrode of the seventh field effect transistor and the grid electrode of the eighth field effect transistor.
One end of the third capacitor is connected with the center tap of the first inductor and the center tap of the input end of the third transformer, and the other end of the third capacitor is grounded. The positive end of the amplifier power supply is connected with the center tap of the input end of the second transformer; and the negative end of the power supply of the amplifier is connected with the center tap of the second inductor. The power supply current flows out of the positive end of the power supply of the amplifier, flows into the drains of the third field effect transistor and the fourth field effect transistor through the second transformer, flows out of the sources of the first field effect transistor and the second field effect transistor, flows into the drains of the seventh field effect transistor and the eighth field effect transistor through the first inductor and the third transformer, and finally flows out of the sources of the fifth field effect transistor and the sixth field effect transistor, flows back to the negative end of the power supply of the amplifier through the second inductor.
With reference to the first aspect, in some embodiments, the current multiplexing amplifier is a three-stage current multiplexing amplifier, including the first stage amplifier, a second stage amplifier, and the final stage amplifier; the grounding end of the first-stage amplifier is connected with the power end of the second-stage amplifier, and the grounding end of the second-stage amplifier is connected with the power end of the final-stage amplifier; the power supply current flows from the positive end of the power supply of the amplifier into the power end of the first-stage amplifier, flows from the grounding end of the first-stage amplifier, flows into the power end of the second-stage amplifier, flows from the grounding end of the second-stage amplifier, flows into the power end of the final-stage amplifier, flows from the grounding end of the final-stage amplifier, and finally flows back to the negative end of the power supply of the amplifier.
With reference to the first aspect, in some embodiments, a ground terminal of the amplifier before the final stage amplifier is grounded through a bypass capacitor.
With reference to the first aspect, in some embodiments, the at least two-stage amplifier is a single-ended amplifier or the at least two-stage amplifier is a differential amplifier.
With reference to the first aspect, in some embodiments, the at least two-stage amplifier employs a field effect transistor as a signal amplifying element, and the at least two-stage amplifier is in a common source structure, a common gate structure, or a common source and common gate structure; or the at least two-stage amplifier adopts a triode as a signal amplifying element, and is of a common emitter structure, a common base structure or a common emitter and common base structure.
In a second aspect, an embodiment of the present application provides an electronic device comprising a current multiplexing amplifier according to any of the first aspects above.
Compared with the related art, the embodiment of the application has the beneficial effects that:
The embodiment of the application provides a current multiplexing amplifier and an electronic device, which comprise at least two stages of amplifiers, wherein the at least two stages of amplifiers are sequentially connected in series in a signal input direction; the power end of the first-stage amplifier is connected with the positive end of the power supply of the amplifier, and the grounding end of the final-stage amplifier is connected with the negative end of the power supply of the amplifier; for the amplifiers of the adjacent two stages, the ground terminal of the amplifier of the previous stage is connected with the power terminal of the amplifier of the next stage. The power supply current sequentially flows through at least two stages of amplifiers from the positive end of the power supply of the amplifier, flows out from the grounding end of the final stage amplifier, and finally flows back to the negative end of the power supply of the amplifier, so that the bias current of the current multiplexing amplifier is determined by the final stage amplifier. Thus, when the output power increases, the final amplifier is switched from the ClassA mode to ClassAB mode, and the bias current of the current multiplexing amplifier increases with the increase of the output power; further, when the bias current increases with the output power, the gain of the amplifier before the final stage amplifier may increase with the increase of the bias current, and the portion where the gain of the previous amplifier increases may cancel the gain decrease of the final stage amplifier due to the increase of the output power to some extent, thereby improving the linearity of the amplifier.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the related technical descriptions will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a current multiplexing amplifier according to an embodiment of the present application;
fig. 2 is a schematic diagram of a two-stage current multiplexing amplifier according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a three-stage current-multiplexing amplifier according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a differential two-stage current-multiplexing amplifier according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a differential three-stage current-multiplexing amplifier according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
fig. 7 is a schematic diagram of a two-stage current multiplexing amplifier according to another embodiment of the present application;
Fig. 8 is a schematic diagram of a two-stage current-multiplexing amplifier according to still another embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the term "comprises/comprising" when used in this specification and the appended claims is taken to specify the presence of stated features, integers, elements, and/or components, but does not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.
Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
The embodiment of the application provides a current multiplexing amplifier which can be used for the design of integrated circuit amplifier circuits in microwave, radio frequency, millimeter wave, terahertz and other frequency bands. The current multiplexing amplifier will be described in detail with reference to the drawings.
Fig. 1 shows a block diagram of a current multiplexing amplifier according to an embodiment of the application. Referring to fig. 1, the current multiplexing amplifier includes at least two stages of amplifiers (a first stage amplifier A1, a second stage amplifier A2, … …, a final stage amplifier A0) connected in series in order in a signal input direction; the amplifier connected to the signal input terminal In is a first-stage amplifier A1, and the amplifier connected to the signal output terminal Out is a final-stage amplifier A0. The power end of the first-stage amplifier A1 is connected with the positive end VDD of the power supply of the amplifier, and the grounding end of the final-stage amplifier A0 is connected with the negative end of the power supply of the amplifier; for the amplifiers of two adjacent stages, the grounding end of the amplifier of the previous stage is connected with the power end of the amplifier of the next stage; the amplifier power supply is used to supply power to the first stage amplifier A1 to generate the supply current I dc. The power supply current I dc flows through at least two stages of amplifiers in sequence from the positive end VDD of the power supply of the amplifiers, flows out from the ground end of the final amplifier A0, and finally flows back to the negative end of the power supply of the amplifiers.
In the above embodiment, the overall power consumption of the current multiplexing amplifier is determined by the bias state of the final stage amplifier A0, so that the linearity of the final stage amplifier A0 is improved, and the linearity of the entire current multiplexing amplifier is improved.
In some embodiments, the current multiplexing amplifier may be a two-stage current multiplexing amplifier. Referring to fig. 2, the two-stage current multiplexing amplifier includes a first stage amplifier A1 and a final stage amplifier A0. The ground terminal of the first stage amplifier A1 is connected to the power supply terminal of the final stage amplifier A0.
The power supply current I dc flows into the power supply end of the first-stage amplifier A1 from the positive end VDD of the power supply of the amplifier, flows out from the grounding end of the first-stage amplifier A1, flows into the power supply end of the final-stage amplifier A0, flows out from the grounding end of the final-stage amplifier A0, and finally flows back to the negative end of the power supply of the amplifier.
The bias current of the two-stage current multiplexing amplifier in the above embodiment is determined by the final stage amplifier A0. When the output power increases, the final stage amplifier A0 is switched from the Class a mode to the Class AB mode, and the bias current of the entire current multiplexing amplifier increases as the output power increases. While when the bias current of the entire current multiplexing amplifier increases with the output power, the gain of the first stage amplifier A1 increases with the increase of the bias current. The gain increasing part of the first-stage amplifier A1 can partially and even completely offset the gain reduction of the final-stage amplifier A0 caused by the increase of the output power, thereby remarkably improving the linearity of the current multiplexing amplifier.
In some embodiments, referring to fig. 3, the two-stage current multiplexing amplifier may further include an input matching network 31, an interstage matching network 32, and an output matching network 33. As shown In fig. 3, the first-stage amplifier A1 is connected to the signal input terminal In through an input matching network 31, and is connected to the final-stage amplifier A0 through an inter-stage matching network 32; the final amplifier A0 is connected to the signal output Out via an output matching network 33.
In some embodiments, the current-multiplexing amplifier may be a three-stage current-multiplexing amplifier. Referring to fig. 4, the three-stage current multiplexing amplifier includes a first stage amplifier A1, a second stage amplifier A2, and a final stage amplifier A0. The ground terminal of the first-stage amplifier A1 is connected with the power terminal of the second-stage amplifier A2, and the ground terminal of the second-stage amplifier A2 is connected with the power terminal of the final-stage amplifier A0.
The power supply current I dc flows from the positive end VDD of the power supply of the amplifier into the power end of the first-stage amplifier A1, flows from the ground end of the first-stage amplifier A1 into the power end of the second-stage amplifier A2, flows from the ground end of the second-stage amplifier A2 into the power end of the final-stage amplifier A0, flows from the ground end of the final-stage amplifier A0, and finally flows back to the negative end of the power supply of the amplifier.
In some embodiments, the amplifier before the final stage amplifier A0, i.e., the first amplifier A1 (when the current multiplexing amplifier includes only two stages of amplifiers), or the first stage amplifier A1, the second stage amplifier A2, etc. (when the current multiplexing amplifier includes three or more stages of amplifiers), may have its ground connected to ground through a bypass capacitor, thereby forming an ac ground at the circuit node. For example, the capacitor C01 in fig. 2, the capacitor C01 and the capacitor C02 in fig. 4, the capacitor C01 in fig. 5, and the capacitor C01 and the capacitor C02 in fig. 6 are bypass capacitors.
Alternatively, the two-stage amplifiers in the embodiment of the present application may be single-ended amplifiers, or may be differential amplifiers. Both fig. 2 and 3 can be regarded as current multiplexing amplifiers consisting of single-ended amplifiers. Fig. 5 and 6 show schematic structural diagrams of a differential two-stage current-multiplexing amplifier and a differential three-stage current-multiplexing amplifier, respectively. As shown in fig. 5 and 6, the differential current multiplexing amplifier is different from the single-ended current multiplexing amplifier in whether the input and output are differential signals. For the current multiplexing case, the differential current multiplexing amplifier is not substantially different from the single-ended current multiplexing amplifier, and will not be described here again.
Optionally, at least two stages of amplifiers in the embodiments of the present application may use a field effect transistor as a signal amplifying element, and each stage of amplifier may be a common source structure, a common gate structure, or a common source and common gate structure.
Optionally, at least two stages of amplifiers in the embodiment of the present application may use a transistor as a signal amplifying element, and each stage of amplifier may be a common emitter structure, a common base structure, or a common emitter and common base structure.
Alternatively, the current multiplexing amplifier in the embodiment of the application can be prepared by adopting transistors with various processes such as CMOS, gaAs, HBT, BJT or GaN.
Further, an embodiment of the present application provides a two-stage current-multiplexing amplifier based on a CMOS process, and fig. 7 shows a schematic diagram of the two-stage current-multiplexing amplifier.
As shown in fig. 7, the first stage amplifier A1 includes a first inductance L1, a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, and a fourth field effect transistor M4; the final amplifier A0 includes a second inductance L2, a fifth field effect transistor M5, a sixth field effect transistor M6, a seventh field effect transistor M7, and an eighth field effect transistor M8.
The first field effect Transistor M1, the second field effect Transistor M2, the third field effect Transistor M3 and the fourth field effect Transistor M4 are cores of the first amplifier A1, the fifth field effect Transistor M5, the sixth field effect Transistor M6, the seventh field effect Transistor M7 and the eighth field effect Transistor M8 are cores of the final amplifier A0, and M1 to M8 are MOSFETs (Metal Oxide Semiconductor FIELD EFFECT transistors ).
Referring to fig. 7, one end of an input terminal of the input matching network 31 is connected to one end of a signal input terminal In, the other end of the input terminal of the input matching network 31 is connected to the other end of the signal input terminal In, one end of an output terminal of the input matching network 31 is connected to a gate of the first field effect transistor M1, and the other end of the output terminal of the input matching network 31 is connected to a gate of the second field effect transistor M2.
The source electrode of the first field effect transistor M1 is connected with one end of the first inductor L1, and the drain electrode of the first field effect transistor M1 is connected with the source electrode of the third field effect transistor M3; the source electrode of the second field effect transistor M2 is connected with the other end of the first inductor L1, and the drain electrode of the second field effect transistor M2 is connected with the source electrode of the fourth field effect transistor M4; the gate of the third field effect transistor M3 is connected to the gate of the fourth field effect transistor M4.
One end of the input end of the inter-stage matching network 32 is connected with the drain electrode of the third field effect transistor M3, the other end of the input end of the inter-stage matching network 32 is connected with the drain electrode of the fourth field effect transistor M4, one end of the output end of the inter-stage matching network 32 is connected with the gate electrode of the fifth field effect transistor M5, and the other end of the output end of the inter-stage matching network 32 is connected with the gate electrode of the sixth field effect transistor M6.
The source electrode of the fifth field effect transistor M5 is connected with one end of the second inductor L2, and the drain electrode of the fifth field effect transistor M5 is connected with the source electrode of the seventh field effect transistor M7; the source electrode of the sixth field effect transistor M6 is connected with the other end of the second inductor L2, and the drain electrode of the sixth field effect transistor M6 is connected with the source electrode of the eighth field effect transistor M8; the gate of the seventh field effect transistor M7 is connected to the gate of the eighth field effect transistor M8.
One end of the input end of the output matching network 33 is connected to the drain of the seventh field effect transistor M7, the other end of the input end of the output matching network 33 is connected to the drain of the eighth field effect transistor M8, one end of the output matching network 33 is connected to one end of the signal output end Out, and the other end of the output matching network 33 is connected to the other end of the signal output end Out.
The positive end VDD (power supply voltage is 2.5V) of the amplifier power supply is connected with the input end of the interstage matching network 32, and the negative end of the amplifier power supply is connected with the center tap of the second inductor L2; the center tap of the first inductance L1 is grounded and the center tap of the first inductance L1 is connected to the input of the output matching network 33.
In the two-stage current multiplexing amplifier shown in fig. 7, the power supply current I dc flows from the positive terminal VDD of the amplifier power supply, flows through the inter-stage matching network 32, flows into the drains of the third field effect transistor M3 and the fourth field effect transistor M4, flows from the sources of the first field effect transistor M1 and the second field effect transistor M2, flows through the first inductor L1 and the output matching network 33, flows into the drains of the seventh field effect transistor M7 and the eighth field effect transistor M8, and finally flows from the sources of the fifth field effect transistor M5 and the sixth field effect transistor M6, flows through the second inductor L2, and flows back to the negative terminal of the amplifier power supply.
In one possible implementation, referring to fig. 8, the input matching network 31 in the two-stage current multiplexing amplifier shown in fig. 7 may include a first resistor R1, a first transformer T1, and a first capacitor C1, the inter-stage matching network 32 may include a second transformer T2 and a second resistor R2, and the output matching network 33 may include a third transformer T3 and a second capacitor C2. The two-stage current multiplexing amplifier may further include a first bias voltage access terminal V g1, a second bias voltage access terminal V g2, a third bias voltage access terminal V g3, a fourth bias voltage access terminal V g4, and a third capacitor C3.
The transformers T1, T2, and T3 are all coupling transformers for realizing impedance matching. In other embodiments, the transformers T1, T2, T3 may be replaced by matching networks consisting of inductors and capacitors. It should be noted that when the differential signal needs to be converted into a single-ended signal or the single-ended signal needs to be converted into the differential signal, the transformers T1, T2, T3 are all balun.
It can be appreciated that the first bias voltage access terminal V g1, the second bias voltage access terminal V g2, the third bias voltage access terminal V g3, and the fourth bias voltage access terminal V g4 are used to provide bias voltages for the gates of the field effect transistors M1 to M8. The third capacitor C3 is a bypass capacitor of the first stage amplifier A1 in this embodiment.
As shown In fig. 8, one end of the input end of the first transformer T1 is connected to one end of the first capacitor C1 and one end of the signal input end In, the other end of the input end T1 of the first transformer is connected to the other end of the first capacitor C1 and the other end of the signal input end In, one end of the output end of the first transformer T1 is connected to one end of the first resistor R1 and the gate of the first field effect transistor M1, and the other end of the output end of the first transformer T1 is connected to the other end of the first resistor R1 and the gate of the second field effect transistor M2.
One end of the input end of the second transformer T2 is connected with the drain electrode of the third field effect transistor M3, the other end of the input end of the second transformer T2 is connected with the drain electrode of the fourth field effect transistor M4, one end of the output end of the second transformer T2 is connected with one end of the second resistor R2 and the grid electrode of the fifth field effect transistor M5, and the other end of the output end of the second transformer T2 is connected with the other end of the second resistor R2 and the grid electrode of the sixth field effect transistor M6.
One end of the input end of the third transformer T3 is connected with the drain electrode of the seventh field effect transistor M7, the other end of the input end of the third transformer T3 is connected with the drain electrode of the eighth field effect transistor M8, one end of the output end of the third transformer T3 is connected with one end of the second capacitor C2 and one end of the signal output end Out, and the other end of the output end of the third transformer T3 is connected with the other end of the second capacitor C2 and the other end of the signal output end Out.
The first bias voltage access terminal V g1 is connected with a center tap of the output terminal of the first transformer T1; the second bias voltage access terminal V g2 is connected to the gate of the third field effect transistor M3 and the gate of the fourth field effect transistor M4; the third bias voltage access terminal V g3 is connected with a center tap of the output terminal of the second transformer T2; the fourth bias voltage access terminal V g4 is connected to the gate of the seventh field effect transistor M7 and the gate of the eighth field effect transistor M8.
One end of the third capacitor C3 is connected with the center tap of the first inductor L1 and the center tap of the input end of the third transformer T3, and the other end of the third capacitor C3 is grounded.
The positive end VDD of the amplifier power supply is connected with a center tap of the input end of the second transformer T2; the negative terminal of the amplifier power supply is connected with the center tap of the second inductor L2.
It will be appreciated that the transformers T2, T3 are made using two coupled inductances with center taps, which are the equal split points of the inductance values, so that for differential signals there is an ac ground (virtual ground) at the center tap, where there is no signal. Thus, the center tap of the inductor and transformer are ideal locations for dc feeds.
Referring to fig. 8, the power supply current I dc flows from the positive terminal VDD of the amplifier power supply, flows through the second transformer T2 into the drains of the third and fourth field effect transistors M3 and M4, flows from the sources of the first and second field effect transistors M1 and M2, flows through the first inductor L1 and the third transformer T3 into the drains of the seventh and eighth field effect transistors M7 and M8, and finally flows from the sources of the fifth and sixth field effect transistors M5 and M6, flows through the second inductor L2, and flows back to the negative terminal of the amplifier power supply.
According to the current multiplexing amplifier provided by the embodiment of the application, the power end of the first-stage amplifier is connected with the positive end of the power supply of the amplifier, and the grounding end of the previous-stage amplifier is connected with the power end of the adjacent next-stage amplifier, so that the power current finally flows out of the grounding end of the final-stage amplifier and flows into the negative end of the power supply of the amplifier, and the linearity of the whole current multiplexing amplifier is effectively improved. Experiments prove that compared with the traditional current multiplexing amplifier, the power of the 1dB compression point output by the amplifier can be improved by about 3dB on the premise of the same power consumption.
The embodiment of the application also provides an electronic device which comprises the current multiplexing amplifier.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. The current multiplexing amplifier is characterized by comprising at least two stages of amplifiers, wherein the at least two stages of amplifiers are sequentially connected in series in the signal input direction; the amplifier connected with the signal input end is a first-stage amplifier, and the amplifier connected with the signal output end is a final-stage amplifier;
The power end of the first-stage amplifier is connected with the positive end of the power supply of the amplifier, and the grounding end of the final-stage amplifier is connected with the negative end of the power supply of the amplifier; for the amplifiers of two adjacent stages, the grounding end of the amplifier of the previous stage is connected with the power end of the amplifier of the next stage; the amplifier power supply is used for supplying power to the first-stage amplifier to generate a power supply current;
and the power supply current sequentially flows through the at least two stages of amplifiers from the positive end of the power supply of the amplifier, flows out from the grounding end of the final stage amplifier and finally flows back to the negative end of the power supply of the amplifier.
2. The current-multiplexing amplifier of claim 1, wherein the current-multiplexing amplifier is a two-stage current-multiplexing amplifier comprising the first stage amplifier and the final stage amplifier;
The grounding end of the first-stage amplifier is connected with the power end of the final-stage amplifier;
The power supply current flows into the power supply end of the first-stage amplifier from the positive end of the power supply of the amplifier, flows out of the grounding end of the first-stage amplifier, flows into the power supply end of the final-stage amplifier, flows out of the grounding end of the final-stage amplifier, and finally flows back to the negative end of the power supply of the amplifier.
3. The current multiplexing amplifier of claim 2, further comprising an input matching network, an interstage matching network, and an output matching network; the first-stage amplifier is connected with the signal input end through the input matching network and is connected with the final-stage amplifier through the interstage matching network; and the final amplifier is connected with the signal output end through the output matching network.
4. The current-multiplexing amplifier of claim 3, wherein the first stage amplifier comprises a first inductor, a first field effect transistor, a second field effect transistor, a third field effect transistor, and a fourth field effect transistor; the final amplifier comprises a second inductor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor and an eighth field effect transistor;
One end of the input matching network is connected with one end of the signal input end, the other end of the input matching network is connected with the other end of the signal input end, one end of the output end of the input matching network is connected with the grid electrode of the first field effect transistor, and the other end of the output end of the input matching network is connected with the grid electrode of the second field effect transistor;
The source electrode of the first field effect transistor is connected with one end of the first inductor, and the drain electrode of the first field effect transistor is connected with the source electrode of the third field effect transistor; the source electrode of the second field effect transistor is connected with the other end of the first inductor, and the drain electrode of the second field effect transistor is connected with the source electrode of the fourth field effect transistor; the grid electrode of the third field effect transistor is connected with the grid electrode of the fourth field effect transistor;
One end of the input end of the inter-stage matching network is connected with the drain electrode of the third field effect transistor, the other end of the input end of the inter-stage matching network is connected with the drain electrode of the fourth field effect transistor, one end of the output end of the inter-stage matching network is connected with the grid electrode of the fifth field effect transistor, and the other end of the output end of the inter-stage matching network is connected with the grid electrode of the sixth field effect transistor;
the source electrode of the fifth field effect transistor is connected with one end of the second inductor, and the drain electrode of the fifth field effect transistor is connected with the source electrode of the seventh field effect transistor; the source electrode of the sixth field effect transistor is connected with the other end of the second inductor, and the drain electrode of the sixth field effect transistor is connected with the source electrode of the eighth field effect transistor; a grid electrode of the seventh field effect transistor is connected with a grid electrode of the eighth field effect transistor;
One end of the input end of the output matching network is connected with the drain electrode of the seventh field effect transistor, the other end of the input end of the output matching network is connected with the drain electrode of the eighth field effect transistor, one end of the output matching network is connected with one end of the signal output end, and the other end of the output matching network is connected with the other end of the signal output end;
the positive end of the amplifier power supply is connected with the input end of the interstage matching network, and the negative end of the amplifier power supply is connected with the center tap of the second inductor; the center tap of the first inductor is grounded, and the center tap of the first inductor is connected with the input end of the output matching network;
The power supply current flows out of the positive end of the amplifier power supply, flows through the interstage matching network, flows into the drains of the third field effect transistor and the fourth field effect transistor, flows out of the sources of the first field effect transistor and the second field effect transistor, flows through the first inductor and the output matching network, flows into the drains of the seventh field effect transistor and the eighth field effect transistor, flows out of the sources of the fifth field effect transistor and the sixth field effect transistor, flows through the second inductor, and flows back to the negative end of the amplifier power supply.
5. The current-multiplexing amplifier of claim 4, wherein the input matching network comprises a first resistor, a first transformer, and a first capacitor, the inter-stage matching network comprises a second transformer and a second resistor, and the output matching network comprises a third transformer and a second capacitor;
the current multiplexing amplifier further comprises a first bias voltage access terminal, a second bias voltage access terminal, a third bias voltage access terminal, a fourth bias voltage access terminal and a third capacitor;
One end of the input end of the first transformer is connected with one end of the first capacitor and one end of the signal input end, the other end of the input end of the first transformer is connected with the other end of the first capacitor and the other end of the signal input end, one end of the output end of the first transformer is connected with one end of the first resistor and the grid electrode of the first field effect transistor, and the other end of the output end of the first transformer is connected with the other end of the first resistor and the grid electrode of the second field effect transistor;
one end of the input end of the second transformer is connected with the drain electrode of the third field effect transistor, the other end of the input end of the second transformer is connected with the drain electrode of the fourth field effect transistor, one end of the output end of the second transformer is connected with one end of the second resistor and the grid electrode of the fifth field effect transistor, and the other end of the output end of the second transformer is connected with the other end of the second resistor and the grid electrode of the sixth field effect transistor;
One end of the input end of the third transformer is connected with the drain electrode of the seventh field effect transistor, the other end of the input end of the third transformer is connected with the drain electrode of the eighth field effect transistor, one end of the output end of the third transformer is connected with one end of the second capacitor and one end of the signal output end, and the other end of the output end of the third transformer is connected with the other end of the second capacitor and the other end of the signal output end;
The first bias voltage access end is connected with a center tap of the output end of the first transformer; the second bias voltage access terminal is connected with the grid electrode of the third field effect transistor and the grid electrode of the fourth field effect transistor; the third bias voltage access end is connected with a center tap of the output end of the second transformer; the fourth bias voltage access terminal is connected with the grid electrode of the seventh field effect transistor and the grid electrode of the eighth field effect transistor;
One end of the third capacitor is connected with the center tap of the first inductor and the center tap of the input end of the third transformer, and the other end of the third capacitor is grounded;
The positive end of the amplifier power supply is connected with the center tap of the input end of the second transformer; the negative end of the amplifier power supply is connected with the center tap of the second inductor;
The power supply current flows out of the positive end of the power supply of the amplifier, flows into the drains of the third field effect transistor and the fourth field effect transistor through the second transformer, flows out of the sources of the first field effect transistor and the second field effect transistor, flows into the drains of the seventh field effect transistor and the eighth field effect transistor through the first inductor and the third transformer, and finally flows out of the sources of the fifth field effect transistor and the sixth field effect transistor, flows back to the negative end of the power supply of the amplifier through the second inductor.
6. The current-multiplexing amplifier of claim 1, wherein the current-multiplexing amplifier is a three-stage current-multiplexing amplifier comprising the first stage amplifier, a second stage amplifier, and the final stage amplifier;
The grounding end of the first-stage amplifier is connected with the power end of the second-stage amplifier, and the grounding end of the second-stage amplifier is connected with the power end of the final-stage amplifier;
the power supply current flows from the positive end of the power supply of the amplifier into the power end of the first-stage amplifier, flows from the grounding end of the first-stage amplifier, flows into the power end of the second-stage amplifier, flows from the grounding end of the second-stage amplifier, flows into the power end of the final-stage amplifier, flows from the grounding end of the final-stage amplifier, and finally flows back to the negative end of the power supply of the amplifier.
7. The current-multiplexing amplifier of claim 1, wherein the ground terminal of the amplifier before the final stage amplifier is grounded through a bypass capacitor.
8. The current-multiplexing amplifier of claim 1, wherein the at least two-stage amplifier is a single-ended amplifier or the at least two-stage amplifier is a differential amplifier.
9. The current-multiplexing amplifier of claim 1, wherein the at least two-stage amplifier employs a field effect transistor as a signal amplifying element, and the at least two-stage amplifier is of a common-source structure, a common-gate structure, or a common-source common-gate structure; or the at least two-stage amplifier adopts a triode as a signal amplifying element, and is of a common emitter structure, a common base structure or a common emitter and common base structure.
10. An electronic device comprising a current multiplexing amplifier according to any of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410119899.2A CN118017947A (en) | 2024-01-29 | 2024-01-29 | Current multiplexing amplifier and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410119899.2A CN118017947A (en) | 2024-01-29 | 2024-01-29 | Current multiplexing amplifier and electronic device |
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| CN202410119899.2A Pending CN118017947A (en) | 2024-01-29 | 2024-01-29 | Current multiplexing amplifier and electronic device |
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