CN118012220B - SiC MOSFET active gate driving circuit based on Wilson current mirror - Google Patents
SiC MOSFET active gate driving circuit based on Wilson current mirror Download PDFInfo
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Abstract
The invention relates to a SiC MOSFET active gate driving circuit based on a Wilson current mirror, which is characterized in that a driving current is provided based on a current providing circuit (1), a first mirror current source control switch circuit (4) and a second mirror current source control switch circuit (5) respectively detect the voltage of the source electrode of a SiC MOSFET U1 to be tested, and a corresponding first bypass current generating circuit (2) and a second bypass current generating circuit (3) are controlled to respectively work so as to drive the SiC MOSFET U1 to be tested; the design scheme designs a bypass Wilson current mirror cut into a grid driving circuit in the switching-on and switching-off processes, and is used for accelerating the grid source voltage in the switching-on process) The change speed is kept, so that the drain-source voltage is not influenced) Drain current [ ]) Under the condition of overshoot, the switching speed is increased, thereby achieving the purpose of reducing switching loss.
Description
Technical Field
The invention relates to a SiC MOSFET active gate driving circuit based on a Wilson current mirror, and belongs to the technical field of driving circuits.
Background
With the continuous advancement of power semiconductor technology, siC semiconductor devices are rapidly reaching the corner of the world, to meet the growing demands of the high power semiconductor device market. Compared with the traditional silicon (Si) semiconductor device, the SiC power device has excellent performance, so that the SiC power device gradually occupies market share in the application fields of higher switching frequency and higher power level, such as new energy power generation, electric automobile converters, industrial equipment, servers and the like.
SiC MOSFETs exhibit excellent switching speeds, which place stringent requirements on the design of the gate drive circuit. The gate drive circuit must quickly deliver a signal to ensure quick turn-on of the SiC MOSFET, minimize power consumption, and need to provide sufficient voltage to maintain proper operation, while also having to provide sufficient current and power to achieve efficient driving.
However, in practical applications, parasitic parameters in devices and circuits are unavoidable. When the SiC MOSFET device works under a high-frequency condition, the phenomena of overshoot and oscillation and the like of voltage and current passing through the SiC MOSFET can be caused due to the existence of stray inductance and parasitic capacitance in a circuit, and when the voltage or current overshoot exceeds the breakdown voltage of the SiC MOSFET or the maximum recovery current of an anti-parallel diode of the SiC MOSFET, the SiC MOSFET device can be damaged.
The Conventional Gate Driver (CGD) adjusts the switching speed of the power device by changing the gate driving voltage, the driving resistance, the gate input capacitance, and the like, which adjust the speed of the power device in the whole on or off process, but cannot flexibly adjust the switching speed of the power device in the stage of on or off part.
Document "Sayan Acharya, Xu She, Fengfeng Tao, Tony Frangieh, Maja Harfman Todorovic and Rajib Datta, "Active Gate Driver for SiC-MOSFET-Based PV Inverter With Enhanced Operating Range," [J] IEEE Transactions on Industrial Electronics , vol. 55, no. 2, pp. 1677-1689, Mar.-Apr. 2019" proposes an active driving implementation method for switching resistors, the method switches the driving resistors in the switching-on and switching-off processes by switching the switching states of different switching transistors QN1-QN3 and QP1-QP3, the method changes a driving loop in the switching-on and switching-off process of a power switch, but the driving current at the moment can reach several amperes, the influence of the driving loop resistor on a grid electrode is larger, and the scheme adopts more switching transistors and has higher implementation cost.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a SiC MOSFET active gate driving circuit based on a Wilson current mirror, wherein a bypass Wilson current mirror cut into the gate driving circuit is designed in the process of switching on and off and is used for accelerating the gate-source voltage in the switching process) The speed of change is changed so as not to influence the drain-source voltage (/ >)) Drain current (/ >)) Under the condition of overshoot, the switching speed is increased, thereby achieving the purpose of reducing switching loss.
The invention adopts the following technical scheme for solving the technical problems: the invention designs a SiC MOSFET active gate driving circuit based on a Wilson current mirror, which comprises a current supply circuit, a first bypass current generation circuit, a second bypass current generation circuit, a first mirror current source control switch circuit and a second mirror current source control switch circuit, wherein the first bypass current generation circuit is connected with the first mirror current source control switch circuit;
The output end of the first mirror current source control switch circuit is connected with the power supply control end of the first bypass current generation circuit in a butt joint mode, the detection end of the first mirror current source control switch circuit is connected with the source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit, the first mirror current source control switch circuit detects the voltage of the source electrode of the SiC MOSFET U1 to be tested, and the first bypass current generation circuit is controlled to work; the output end of the second mirror current source control switch circuit is connected with the power supply control end of the second bypass current generation circuit in a butt joint mode, the detection end of the second mirror current source control switch circuit is connected with the source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit, and the second mirror current source control switch circuit detects the voltage of the source electrode of the SiC MOSFET U1 to be tested and controls the second bypass current generation circuit to work;
The first current end of the current supply circuit is connected with the control output end of the first bypass current generation circuit, the second current end of the current supply circuit is connected with the control output end of the second bypass current generation circuit, and the two connected ends are further connected with each other to form a front end, and the front end is abutted against the grid electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit.
As a preferred technical scheme of the invention: the double-pulse testing device comprises a double-pulse testing circuit, and is characterized by further comprising an overvoltage protection circuit, wherein the front end is connected with the front side end of the overvoltage protection circuit in a butt joint mode, the first control end of the overvoltage protection circuit is connected with the grid electrode of the SiC MOSFET U1 to be tested in the double-pulse testing circuit in a butt joint mode, and the second control end of the overvoltage protection circuit is connected with the source electrode of the SiC MOSFET U1 to be tested in the double-pulse testing circuit in a butt joint mode.
As a preferred technical scheme of the invention: the overvoltage protection circuit comprises a transient voltage suppression diode D3 and a transient voltage suppression diode D4, wherein the negative electrode of the transient voltage suppression diode D3 simultaneously forms a front side end and a first control end of the overvoltage protection circuit, the positive electrode of the transient voltage suppression diode D3 is connected with the positive electrode of the transient voltage suppression diode D4 in a butt joint mode, and the negative electrode of the transient voltage suppression diode D4 forms a second control end of the overvoltage protection circuit.
As a preferred technical scheme of the invention: the first bypass current generating circuit includes an NPN transistor Q1, an NPN transistor Q2, an NPN transistor Q7, an NPN transistor Q8, a resistor R4, and a diode D1, wherein an emitter of the NPN transistor Q1 is connected to an emitter of the NPN transistor Q2 and grounded, a base of the NPN transistor Q1, a base of the NPN transistor Q2, a collector of the NPN transistor Q2, and an emitter of the NPN transistor Q8 are connected, one end of the base of the NPN transistor Q8, the base of the NPN transistor Q7, the collector of the NPN transistor Q7, and one end of the resistor R4 is connected, a collector of the NPN transistor Q1 is connected to an emitter of the NPN transistor Q7, a collector of the NPN transistor Q8 is connected to a negative electrode of the diode D1, an anode of the diode D1 forms a control output terminal of the first bypass current generating circuit, and the other end of the resistor R4 forms a power supply control terminal of the first bypass current generating circuit.
As a preferred technical scheme of the invention: the second bypass current generating circuit comprises a PNP type transistor Q5, a PNP type transistor Q6, a PNP type transistor Q9, a PNP type transistor Q10, a bypass control terminal power supply V6, a diode D2, and a resistor R7, wherein the negative electrode of the bypass control terminal power supply V6 is grounded, the positive electrode of the bypass control terminal power supply V6, the emitter of the PNP type transistor Q5, and the emitter of the PNP type transistor Q6 are connected, the base of the PNP type transistor Q6, the base of the PNP type transistor Q5, the collector of the PNP type transistor Q5, and the emitter of the PNP type transistor Q9 are connected, the base of the PNP type transistor Q9, the base of the PNP type transistor Q10, the collector of the PNP type transistor Q10, and one end of the resistor R7 are connected, the positive electrode of the collector of the PNP type transistor Q9 is connected to the diode D2, the negative electrode of the diode D2 forms the control output terminal of the second bypass current generating circuit, and the other end of the resistor R forms the second bypass current generating circuit.
As a preferred technical scheme of the invention: the first mirror current source control switch circuit comprises a voltage-controlled switch circuit SW1, a bypass control end power supply V7, a capacitor C2 and a resistor R10, wherein the voltage-controlled switch circuit SW1 comprises an NMOS tube M1, a voltage comparator U5 and a resistor R8; the negative electrode of the bypass control end power supply V7 is grounded, the positive electrode of the bypass control end power supply V7 is connected with the drain electrode of the NMOS tube M1 in a butt joint mode, the source electrode of the NMOS tube M1 is connected with one end of the capacitor C2, the grid electrode of the NMOS tube M1 is connected with one end of the resistor R8 in a butt joint mode, the other end of the resistor R8 is connected with the output end of the voltage comparator U5 in a butt joint mode, and the positive input end of the voltage comparator U5 forms a detection end of the first mirror current source control switch circuit and is used for being connected with the source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit; the negative input end of the voltage comparator U5 is used for accessing a preset reference voltage Vref; the other end of the capacitor C2 is connected with one end of the resistor R10, and the connected end forms the output end of the first mirror current source control switch circuit, and the other end of the resistor R10 is grounded.
As a preferred technical scheme of the invention: the second mirror current source control switch circuit comprises a voltage-controlled switch circuit SW2, the voltage-controlled switch circuit SW2 comprises an NMOS tube M2, a voltage comparator U6 and a resistor R11, wherein the negative input end of the voltage comparator U6 is used for accessing a preset reference voltage Vref, and the positive input end of the voltage comparator U6 forms a detection end of the second mirror current source control switch circuit and is used for butting the source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit; the output end of the voltage comparator U6 is connected with one end of a resistor R11, the other end of the resistor R11 is connected with the grid electrode of an NMOS tube M2 in a butt joint mode, the source electrode of the NMOS tube M2 is grounded, and the drain electrode of the NMOS tube M2 forms the output end of the second mirror current source control switch circuit.
As a preferred technical scheme of the invention: the current supply circuit is a push-pull amplifying circuit and comprises a PNP type transistor Q3, an NPN type transistor Q4, a control power supply V3, a high-level power supply V4, a low-level power supply V5, an on resistor R5, an off resistor R6, a resistor R2 and a resistor R3, wherein the negative electrode of the control power supply V3 is grounded, the positive electrode of the control power supply V3, one end of the resistor R2 and one end of the resistor R3 are grounded, the other end of the resistor R2 is in butt joint with the grid electrode of the NPN type transistor Q4, the drain electrode of the NPN type transistor Q4 is in butt joint with the positive electrode of the high-level power supply V4, the negative electrode of the high-level power supply V4 is grounded, and the source electrode of the NPN type transistor Q4 is connected with the on resistor R5 in series to form a first current end of the current supply circuit; the other end of the resistor R3 is connected with the grid electrode of the PNP type transistor Q3 in a butt joint mode, the drain electrode of the PNP type transistor Q3 is connected with the positive electrode of the low-level power supply V5 in a butt joint mode, the negative electrode of the low-level power supply V5 is grounded, and the source electrode of the PNP type transistor Q3 is connected with the resistor R6 in series to form a second current end of the current supply circuit.
As a preferred technical scheme of the invention: the resistor R1 is further included, a first current end of the current supply circuit is connected with a control output end of the first bypass current generation circuit, a second current end of the current supply circuit is connected with a control output end of the second bypass current generation circuit, the two connected ends are further connected with each other, and the resistor R1 is connected in series to form a front end.
As a preferred technical scheme of the invention: the double-pulse test circuit further comprises a SiC MOSFET U2, a power supply V1, a power supply V2, a resistor R9, an inductor L9, a capacitor C1 and a power supply V8, wherein the negative electrode of the power supply V2, the drain electrode of the SiC MOSFET U1 to be tested, the source electrode of the SiC MOSFET U2 and one end of the inductor L9 are connected, the positive electrode of the power supply V2 is connected with the grid electrode of the SiC MOSFET U2, the drain electrode of the SiC MOSFET U2, the other end of the inductor L9, one end of the capacitor C1 and the positive electrode of the power supply V8 are connected, the source electrode of the SiC MOSFET U1 to be tested, the other end of the capacitor C1 and the negative electrode of the power supply V8 are connected and grounded, the temperature control end of the SiC MOSFET U1 to be tested, the temperature control end of the SiC MOSFET U2 and the positive electrode of the power supply V1 are connected, and the negative electrode of the power supply V1 is grounded.
Compared with the prior art, the SiC MOSFET active gate driving circuit based on the Wilson current mirror has the following technical effects:
The invention designs a SiC MOSFET active gate driving circuit based on a Wilson current mirror, which aims at a SiC MOSFET U1 to be tested contained in a double-pulse testing circuit, provides driving current based on a current providing circuit, respectively detects the voltage of a source electrode of the SiC MOSFET U1 to be tested by a first mirror current source control switching circuit and a second mirror current source control switching circuit, and controls the Wilson current mirror formed by a corresponding first bypass current generating circuit and a corresponding second bypass current generating circuit to work so as to realize driving of the SiC MOSFET U1 to be tested; the design scheme designs a bypass Wilson current mirror cut into a grid driving circuit in the switching-on and switching-off processes, and is used for accelerating the grid source voltage in the switching-on process ) The speed of change is changed so as not to influence the drain-source voltage (/ >)) Drain current (/ >)) Under the condition of overshoot, the switching speed is increased, so that the purpose of reducing switching loss is achieved; in addition, parasitic inductance of the driving loop, the main power loop and the connection part of the driver and the main power circuit is reduced in the circuit design, so that enough driving current is ensured, and the driving effect is improved;
In the SiC MOSFET active gate driving circuit based on the Wilson current mirror, the design of the Wilson current mirror is that the improved Wilson current mirror composed of 4 transistors is suitable for a large-current circuit, the problem of mismatch of base current can be obviously eliminated, the output current and the input current are nearly consistent, two bypass currents are better regulated and controlled, and the change speed of gate-source voltage is precisely controlled; and an overvoltage protection circuit is introduced to limit the grid voltage of the SiC MOSFET U1 to be tested within the range of the threshold voltage so as to prevent the positive and negative surge voltages of the grid from damaging the SiC MOSFET U1 to be tested and ensure the actual driving test effect.
Drawings
FIG. 1 is a schematic diagram of a SiC MOSFET active gate drive circuit based on a Wilson current mirror in accordance with the present invention;
FIG. 2 shows the gate-source voltages of WAGD and CGD according to the present invention during the on-phase ) Comparing the waveform diagrams with the schematic diagrams;
FIG. 3 shows the gate-source voltages of WAGD and CGD according to the present invention in the off phase ) Comparing the waveform diagrams with the schematic diagrams;
FIG. 4 shows the drain-source voltages of WAGD and CGD according to the present invention during the on-phase ) Comparing the waveform diagrams with the schematic diagrams;
FIG. 5 shows the drain currents of WAGD and CGD according to the present invention during the on phase ) Waveform diagram contrast schematic.
The current supply circuit comprises a current supply circuit 1, a first bypass current generation circuit 2, a second bypass current generation circuit 3, a first mirror current source control switch circuit 4, a second mirror current source control switch circuit 5, an overvoltage protection circuit 6 and a double-pulse test circuit 7.
Detailed Description
The following describes the embodiments of the present invention in further detail with reference to the drawings.
The invention designs a SiC MOSFET active gate driving circuit (WAGD) based on a Wilson current mirror, which comprises a current supply circuit 1, a first bypass current generation circuit 2, a second bypass current generation circuit 3, a first mirror current source control switch circuit 4, a second mirror current source control switch circuit 5, an overvoltage protection circuit 6 and a resistor R1 as shown in figure 1.
As shown in fig. 1, an output end of the first mirrored current source control switch circuit 4 is connected to a power control end of the first bypass current generating circuit 2, a detection end of the first mirrored current source control switch circuit 4 is connected to a source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit 7, and the first mirrored current source control switch circuit 4 detects a voltage of the source electrode of the SiC MOSFET U1 to be tested and controls the first bypass current generating circuit 2 to work; the output end of the second mirror current source control switch circuit 5 is connected with the power supply control end of the second bypass current generation circuit 3 in a butt joint mode, the detection end of the second mirror current source control switch circuit 5 is connected with the source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit 7, the second mirror current source control switch circuit 5 detects the voltage of the source electrode of the SiC MOSFET U1 to be tested, and the second bypass current generation circuit 3 is controlled to work.
As shown in fig. 1, a first current end of the current supply circuit 1 is connected with a control output end of the first bypass current generating circuit 2, a second current end of the current supply circuit 1 is connected with a control output end of the second bypass current generating circuit 3, the two connected ends are further connected with each other and form a leading end after being connected with a resistor R1 in series, the leading end is connected with a leading side end of the overvoltage protection circuit 6 in a butt joint manner, a first control end of the overvoltage protection circuit 6 is connected with a grid electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit 7, and a second control end of the overvoltage protection circuit 6 is connected with a source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit 7.
Regarding the above design scheme, in practical applications, as shown in fig. 1, the specific design of the current supply circuit 1 is a push-pull amplifying circuit, which specifically includes a PNP transistor Q3, an NPN transistor Q4, a control power source V3, a high-level power source V4, a low-level power source V5, an on resistor R5, an off resistor R6, a resistor R2, and a resistor R3, where the negative electrode of the control power source V3 is grounded, the positive electrode of the control power source V3, one end of the resistor R2, and one end of the resistor R3 are grounded, the other end of the resistor R2 is connected to the gate of the NPN transistor Q4, the drain electrode of the NPN transistor Q4 is connected to the positive electrode of the high-level power source V4, the negative electrode of the high-level power source V4 is grounded, and the source of the NPN transistor Q4 is connected in series to the on resistor R5 to form the first current end of the current supply circuit 1; the other end of the resistor R3 is connected with the grid electrode of the PNP type transistor Q3 in a butt joint mode, the drain electrode of the PNP type transistor Q3 is connected with the positive electrode of the low-level power supply V5 in a butt joint mode, the negative electrode of the low-level power supply V5 is grounded, and the source electrode of the PNP type transistor Q3 is connected with the resistor R6 in series to form a second current end of the current supply circuit 1. The PNP transistor Q3 and the NPN transistor Q4 form a push-pull circuit, and when the control signal is at a high level, the upper tube is conducted to pull the grid voltage of the SiC MOSFET U1 to be tested to a high level V4; the down tube is turned on when the control signal is low, pulling the gate voltage of the SiC MOSFET U1 to be tested to a low level V5 and providing a larger drive current. The driving resistor in the switching process is designed separately and is divided into a driving on resistor R5 in the on state and a driving off resistor R6 in the off state, so that the off speed in the off process can be accelerated to a greater extent, and the off loss is reduced. The driving circuit is designed as compact as possible, and the driving resistors are all non-inductive resistors so as to reduce parasitic inductance in the driving circuit.
As shown in fig. 1, the first bypass current generating circuit 2 specifically includes an NPN transistor Q1, an NPN transistor Q2, an NPN transistor Q7, an NPN transistor Q8, a resistor R4, and a diode D1, wherein an emitter of the NPN transistor Q1 is connected to an emitter of the NPN transistor Q2 and grounded, a base of the NPN transistor Q1, a base of the NPN transistor Q2, a collector of the NPN transistor Q2, and an emitter of the NPN transistor Q8 are connected to one another, a base of the NPN transistor Q8, a base of the NPN transistor Q7, a collector of the NPN transistor Q7, and one end of the resistor R4 are connected to one another, a collector of the NPN transistor Q1 is connected to an emitter of the NPN transistor Q7, a collector of the NPN transistor Q8 is connected to a negative electrode of the diode D1, an anode of the diode D1 forms a control output terminal of the first bypass current generating circuit 2, and another end of the resistor R4 forms a control terminal of the first bypass current generating circuit 2.
As shown in fig. 1, the second bypass current generating circuit 3 specifically includes a PNP transistor Q5, a PNP transistor Q6, a PNP transistor Q9, a PNP transistor Q10, a bypass control terminal power source V6, a diode D2, and a resistor R7, wherein a negative electrode of the bypass control terminal power source V6 is grounded, a positive electrode of the bypass control terminal power source V6, an emitter of the PNP transistor Q5, and an emitter of the PNP transistor Q6 are connected, a base of the PNP transistor Q6, a base of the PNP transistor Q5, a collector of the PNP transistor Q5, and an emitter of the PNP transistor Q9 are connected, a base of the PNP transistor Q9, a base of the PNP transistor Q10, a collector of the PNP transistor Q10, and one end of the resistor R7 are connected, an emitter of the PNP transistor Q10 is connected to the PNP transistor Q6, a positive electrode of the collector of the PNP transistor Q9 is connected to the diode D2, and a negative electrode of the PNP transistor D2 forms the negative electrode of the second bypass current generating circuit 3, and a collector of the second bypass current generating circuit forms the second bypass current generating circuit 3.
The design of the Wilson current mirror, namely the specific structural design of the first bypass current generation circuit 2 and the second bypass current generation circuit 3, is applicable to a large current circuit through an improved Wilson current mirror formed by 4 transistors, can obviously eliminate the problem of mismatch of base current, enables output current and input current to be nearly consistent, regulates and controls the two bypass currents better, and controls the change speed of gate-source voltage accurately.
As shown in fig. 1, the first mirrored current source control switch circuit 4 specifically includes a voltage-controlled switch circuit SW1, a bypass control end power supply V7, a capacitor C2, and a resistor R10, where the voltage-controlled switch circuit SW1 includes an NMOS tube M1, a voltage comparator U5, and a resistor R8; the negative electrode of the bypass control end power supply V7 is grounded, the positive electrode of the bypass control end power supply V7 is connected with the drain electrode of the NMOS tube M1 in a butt joint mode, the source electrode of the NMOS tube M1 is connected with one end of the capacitor C2, the grid electrode of the NMOS tube M1 is connected with one end of the resistor R8 in a butt joint mode, the other end of the resistor R8 is connected with the output end of the voltage comparator U5 in a butt joint mode, and the positive input end of the voltage comparator U5 forms a detection end of the first mirror current source control switch circuit 4 and is used for being connected with the source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit 7 in a butt joint mode; the negative input end of the voltage comparator U5 is used for accessing a preset reference voltage Vref; the other end of the capacitor C2 is connected to one end of the resistor R10, and the connected end forms an output end of the first mirrored current source control switch circuit 4, and the other end of the resistor R10 is grounded. When the voltage Vss of the source of the SiC MOSFET U1 to be tested is compared with the set reference voltage Vref by the voltage comparator U5, if Vss is greater than the reference voltage Vref, the NMOS transistor M1 is turned on, the node voltage of N1 rises, the first bypass current generating circuit 2 is turned on, and the resistor R10 is used to raise the voltage of the node N1.
The second mirror current source control switch circuit 5 is shown in fig. 1, and specifically designed to include a voltage-controlled switch circuit SW2, where the voltage-controlled switch circuit SW2 includes an NMOS tube M2, a voltage comparator U6, and a resistor R11, where a negative input end of the voltage comparator U6 is used to access a preset reference voltage Vref, and a positive input end of the voltage comparator U6 forms a detection end of the second mirror current source control switch circuit 5 and is used to dock a source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit 7; the output end of the voltage comparator U6 is connected with one end of a resistor R11, the other end of the resistor R11 is connected with the grid electrode of an NMOS tube M2 in a butt joint mode, the source electrode of the NMOS tube M2 is grounded, and the drain electrode of the NMOS tube M2 forms the output end of the second mirror current source control switch circuit 5. When the voltage Vss at the source of the SiC MOSFET U1 to be tested is compared with the set reference voltage Vref by the voltage comparator U6, if the voltage Vss is greater than the reference voltage Vref, the NMOS transistor M2 is turned on, the voltage at the node N2 rises, and the second bypass current generating circuit 3 is turned on.
In application, the first mirror current source control switch circuit 4 and the second mirror current source control switch circuit 5 are used for respectively and independently controlling the Wilson current mirror formed by the first bypass current generating circuit 2 and the second bypass current generating circuit 3, when the voltage Vss of the source electrode of the SiC MOSFET U1 to be tested is detected to reach the reference voltage Vref, the voltage-controlled switch circuits SW1 and SW2 are turned on and off, and the two Wilson current mirrors are controlled to generate bypass current so as to accelerate the change speed of the gate-source voltage of the SiC MOSFET U1 to be tested in the switching process. The voltage-controlled switching circuits SW1, SW2 can switch states relatively quickly because transistors have a fast response characteristic. Typically, the switching speed can reach nanosecond level, and the method is suitable for high-frequency and high-speed signal switching.
As shown in fig. 1, the specific design of the overvoltage protection circuit 6 includes a transient voltage suppression diode D3 and a transient voltage suppression diode D4, where the negative pole of the transient voltage suppression diode D3 simultaneously forms a front side end and a first control end of the overvoltage protection circuit 6, the positive pole of the transient voltage suppression diode D3 is abutted to the positive pole of the transient voltage suppression diode D4, and the negative pole of the transient voltage suppression diode D4 forms a second control end of the overvoltage protection circuit 6. Two anti-series transient voltage suppression diodes (TVS) are added between the grid electrode and the source electrode of the SiC MOSFET U1 to be tested, wherein the D3 tube limits the amplitude of positive voltage, and the lower D4 tube limits the amplitude of negative voltage, so that the grid voltage is limited in the range of threshold voltage, and the oscillation of the grid voltage is prevented from damaging devices. And the overvoltage protection circuit 6 is used for limiting the grid voltage of the SiC MOSFET U1 to be tested within the range of the threshold voltage so as to prevent the positive and negative surge voltages of the grid from damaging the SiC MOSFET U1 to be tested and ensure the actual driving test effect.
As shown in fig. 1, the specific design of the double-pulse test circuit 7 further includes a SiC MOSFET U2, a power source V1, a power source V2, a resistor R9, an inductor L9, a capacitor C1, and a power source V8, wherein the negative electrode of the power source V2, the drain of the SiC MOSFET U1 to be tested, the source of the SiC MOSFET U2, one end of the inductor L9 are connected, the positive electrode of the power source V2 is connected to the gate of the SiC MOSFET U2, the drain of the SiC MOSFET U2, the other end of the inductor L9, one end of the capacitor C1, and the positive electrode of the power source V8 are connected to each other, and are grounded, and the temperature control end of the SiC MOSFET U1 to be tested, the temperature control end of the SiC MOSFET U2, and the positive electrode of the power source V1 are connected to each other, and the negative electrode of the power source V1 is grounded.
In application, during switching of SiC MOSFET U1 to be tested, the change rate of voltage drop V SS on parasitic inductance L SS on source electrode and drain current thereofIs proportional to the sampling drain current/>/>As a judgment condition, differential amount/>Ratio/>This physical quantity reflects the entrance and exit of the SiC MOSFET into the current rise region and the current fall region more quickly.
The WAGD circuit therefore detects the voltage drop across the source inductance L SS The switching of the two bypass current sources, namely the first bypass current generating circuit 2 and the second bypass current generating circuit 3, is controlled to be orderly turned on and off in the turn-on and turn-off stages of the SiC MOSFET U1 to be tested, so that the switching speed is increased, and the switching loss is reduced.
In practical application, as shown in FIG. 2, the design scheme of the invention enables the gate-source voltage of the SiC MOSFET U1 to be tested in the turn-on stageThe waveform of the pulse is more stable, the opening speed is increased, the opening time is changed from 52.96ns to 44.48ns, and the speed is increased by 16%; as shown in FIG. 3, the design scheme of the invention enables the gate-source voltage/>, of the SiC MOSFET U1 to be tested in the turn-off stageThe waveform of the pulse is smoother, the turn-off speed is increased, the turn-off time is from 56.11ns to 42.32ns, and the speed is increased by 25%; the design scheme of the invention as shown in fig. 4 and 5 ensures that the voltage between the drain and source stages in the opening stage/>And drain current/>Is kept unchanged; namely, the gate-source voltage/>, of the SiC MOSFET U1 to be tested is accelerated through a bypass current source branchFor accelerating the switching speed of certain time phases without affecting/>And/>Under the condition of overshoot, the grid source voltage/>, of the SiC MOSFET U1 to be tested is madeThe waveform is smoother when the waveform is turned on and off. Meanwhile, the switching speed of the SiC MOSFET U1 to be tested is increased, and the starting process is increased by 16%. The turn-off process is quickened by 25%, and the purposes of quickening the switching speed and reducing the switching loss are realized.
The invention designs a device for testing SiC MOSFET U1 contained in a double-pulse testing circuit 7, which is based on a current providing circuit 1 to provide driving current, wherein a first mirror current source control switch circuit 4 and a second mirror current source control switch circuit 5 respectively detect the voltage of the source electrode of the SiC MOSFET U1 to be tested and control a Wilson current mirror respectively formed by a corresponding first bypass current generating circuit 2 and a corresponding second bypass current generating circuit 3 to work so as to drive the SiC MOSFET U1 to be tested; the design scheme designs a bypass Wilson current mirror cut into a grid driving circuit in the switching-on and switching-off processes, and is used for accelerating the grid source voltage in the switching-on process) The speed of change is changed so as not to influence the drain-source voltage (/ >)) Drain current (/ >)) Under the condition of overshoot, the switching speed is increased, so that the purpose of reducing switching loss is achieved; and the parasitic inductance of the connection parts of the drive loop, the main power loop and the driver and the main power circuit is reduced in the circuit design, so that the enough large drive current is ensured, and the drive effect is improved.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention.
Claims (5)
1. A wilson current mirror based SiC MOSFET active gate driving circuit for driving a SiC MOSFET U1 to be tested contained in a double pulse test circuit (7), characterized in that: the current supply circuit comprises a current supply circuit (1), a first bypass current generation circuit (2), a second bypass current generation circuit (3), a first mirror current source control switch circuit (4) and a second mirror current source control switch circuit (5);
The output end of the first mirror current source control switch circuit (4) is connected with the power supply control end of the first bypass current generation circuit (2), the detection end of the first mirror current source control switch circuit (4) is connected with the source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit (7), the first mirror current source control switch circuit (4) detects the voltage of the source electrode of the SiC MOSFET U1 to be tested, and the first bypass current generation circuit (2) is controlled to work; the output end of the second mirror current source control switch circuit (5) is connected with the power supply control end of the second bypass current generation circuit (3), the detection end of the second mirror current source control switch circuit (5) is connected with the source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit (7), the second mirror current source control switch circuit (5) detects the voltage of the source electrode of the SiC MOSFET U1 to be tested, and the second bypass current generation circuit (3) is controlled to work;
A first current end of the current supply circuit (1) is connected with a control output end of the first bypass current generation circuit (2), a second current end of the current supply circuit (1) is connected with a control output end of the second bypass current generation circuit (3), the two connected ends are further connected with each other to form a front end, and the front end is in butt joint with a grid electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit (7);
The first bypass current generation circuit (2) comprises an NPN transistor Q1, an NPN transistor Q2, an NPN transistor Q7, an NPN transistor Q8, a resistor R4 and a diode D1, wherein the emitter of the NPN transistor Q1 is connected with the emitter of the NPN transistor Q2 and grounded, the base of the NPN transistor Q1, the base of the NPN transistor Q2, the collector of the NPN transistor Q2 and the emitter of the NPN transistor Q8 are connected, one end of the base of the NPN transistor Q8, the base of the NPN transistor Q7, the collector of the NPN transistor Q7 and one end of a resistor R4 are connected, the collector of the NPN transistor Q1 is connected with the emitter of the NPN transistor Q7, the collector of the NPN transistor Q8 is connected with the negative electrode of the diode D1, the positive electrode of the diode D1 forms a control output end of the first bypass current generation circuit (2), and the other end of the resistor R4 forms a power supply control end of the first bypass current generation circuit (2);
The second bypass current generation circuit (3) comprises a PNP type transistor Q5, a PNP type transistor Q6, a PNP type transistor Q9, a PNP type transistor Q10, a bypass control end power supply V6, a diode D2 and a resistor R7, wherein the negative electrode of the bypass control end power supply V6 is grounded, the positive electrode of the bypass control end power supply V6, the emitter of the PNP type transistor Q5 and the emitter of the PNP type transistor Q6 are connected, the base of the PNP type transistor Q6, the base of the PNP type transistor Q5, the collector of the PNP type transistor Q5 and the emitter of the PNP type transistor Q9 are connected, the base of the PNP type transistor Q10, the collector of the PNP type transistor Q10 and one end of the resistor R7 are connected, the emitter of the PNP type transistor Q10 is connected with the collector of the PNP type transistor Q6, the positive electrode of the butt joint diode D2 of the PNP type transistor Q9 forms the positive electrode of the PNP type transistor Q6, the negative electrode of the PNP type transistor D2 forms the second bypass current generation circuit (3), and the other end of the PNP type current generation circuit forms the second bypass current generation circuit (3) forms the second bypass current generation circuit;
The first mirror current source control switch circuit (4) comprises a voltage-controlled switch circuit SW1, a bypass control end power supply V7, a capacitor C2 and a resistor R10, wherein the voltage-controlled switch circuit SW1 comprises an NMOS tube M1, a voltage comparator U5 and a resistor R8; the negative electrode of the bypass control end power supply V7 is grounded, the positive electrode of the bypass control end power supply V7 is connected with the drain electrode of the NMOS tube M1 in a butt joint mode, the source electrode of the NMOS tube M1 is connected with one end of the capacitor C2, the grid electrode of the NMOS tube M1 is connected with one end of the resistor R8 in a butt joint mode, the other end of the resistor R8 is connected with the output end of the voltage comparator U5 in a butt joint mode, and the positive input end of the voltage comparator U5 forms a detection end of the first mirror current source control switch circuit (4) and is used for being connected with the source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit (7); the negative input end of the voltage comparator U5 is used for accessing a preset reference voltage Vref; the other end of the capacitor C2 is connected with one end of the resistor R10, the connected end forms an output end of the first mirror current source control switch circuit (4), and the other end of the resistor R10 is grounded;
The second mirror current source control switch circuit (5) comprises a voltage-controlled switch circuit SW2, the voltage-controlled switch circuit SW2 comprises an NMOS tube M2, a voltage comparator U6 and a resistor R11, wherein the negative input end of the voltage comparator U6 is used for accessing a preset reference voltage Vref, and the positive input end of the voltage comparator U6 forms a detection end of the second mirror current source control switch circuit (5) and is used for butting the source electrode of the SiC MOSFET U1 to be tested in the double-pulse test circuit (7); the output end of the voltage comparator U6 is connected with one end of a resistor R11, the other end of the resistor R11 is connected with the grid electrode of an NMOS tube M2 in a butt joint mode, the source electrode of the NMOS tube M2 is grounded, and the drain electrode of the NMOS tube M2 forms the output end of a second mirror current source control switch circuit (5);
The current supply circuit (1) is a push-pull amplifying circuit and comprises a PNP type transistor Q3, an NPN type transistor Q4, a control power supply V3, a high-level power supply V4, a low-level power supply V5, an on resistor R5, an off resistor R6, a resistor R2 and a resistor R3, wherein the negative electrode of the control power supply V3 is grounded, the positive electrode of the control power supply V3, one end of the resistor R2 and one end of the resistor R3 are grounded, the other end of the resistor R2 is connected with the grid electrode of the NPN type transistor Q4 in a butt joint manner, the drain electrode of the NPN type transistor Q4 is connected with the positive electrode of the high-level power supply V4 in a butt joint manner, the negative electrode of the high-level power supply V4 is grounded, and the source electrode of the NPN type transistor Q4 is connected with the on resistor R5 in series to form a first current end of the current supply circuit (1); the other end of the resistor R3 is connected with the grid electrode of the PNP type transistor Q3 in a butt joint mode, the drain electrode of the PNP type transistor Q3 is connected with the positive electrode of the low-level power supply V5 in a butt joint mode, the negative electrode of the low-level power supply V5 is grounded, and the source electrode of the PNP type transistor Q3 is connected with the resistor R6 in series to form a second current end of the current supply circuit (1).
2. The wilson current mirror-based SiC MOSFET active gate driver circuit of claim 1, wherein: the dual-pulse test circuit is characterized by further comprising an overvoltage protection circuit (6), wherein the front end is connected with the front side end of the overvoltage protection circuit (6), the first control end of the overvoltage protection circuit (6) is connected with the grid electrode of the SiC MOSFET U1 to be tested in the dual-pulse test circuit (7), and the second control end of the overvoltage protection circuit (6) is connected with the source electrode of the SiC MOSFET U1 to be tested in the dual-pulse test circuit (7).
3. The wilson current mirror-based SiC MOSFET active gate driver circuit of claim 2, wherein: the overvoltage protection circuit (6) comprises a transient voltage suppression diode D3 and a transient voltage suppression diode D4, wherein the negative electrode of the transient voltage suppression diode D3 simultaneously forms a front side end and a first control end of the overvoltage protection circuit (6), the positive electrode of the transient voltage suppression diode D3 is abutted to the positive electrode of the transient voltage suppression diode D4, and the negative electrode of the transient voltage suppression diode D4 forms a second control end of the overvoltage protection circuit (6).
4. The wilson current mirror-based SiC MOSFET active gate driver circuit of claim 1, wherein: the circuit further comprises a resistor R1, a first current end of the current supply circuit (1) is connected with a control output end of the first bypass current generation circuit (2), a second current end of the current supply circuit (1) is connected with a control output end of the second bypass current generation circuit (3), and the two connected ends are further connected with each other and form a front end after being connected with the resistor R1 in series.
5. The wilson current mirror-based SiC MOSFET active gate driver circuit of claim 1, wherein: the double-pulse test circuit (7) further comprises a SiC MOSFET U2, a power supply V1, a power supply V2, a resistor R9, an inductor L9, a capacitor C1 and a power supply V8, wherein the negative electrode of the power supply V2, the drain electrode of the SiC MOSFET U1 to be tested, the source electrode of the SiC MOSFET U2 and one end of the inductor L9 are connected, the positive electrode of the power supply V2 is connected with the grid electrode of the SiC MOSFET U2, the drain electrode of the SiC MOSFET U2, the other end of the inductor L9, one end of the capacitor C1 and the positive electrode of the power supply V8 are connected, the source electrode of the SiC MOSFET U1 to be tested, the other end of the capacitor C1 and the negative electrode of the power supply V8 are connected and grounded, and the temperature control end of the SiC MOSFET U1 to be tested, the temperature control end of the SiC MOSFET U2 and the positive electrode of the power supply V1 are grounded.
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| US4559458A (en) * | 1984-04-06 | 1985-12-17 | Advanced Micro Devices, Inc. | Temperature tracking and supply voltage independent line driver for ECL circuits |
| US7439480B2 (en) * | 2004-03-05 | 2008-10-21 | Finisar Corporation | Regulated current mirror |
| CN100494926C (en) * | 2007-08-08 | 2009-06-03 | 中国航天时代电子公司第七七一研究所 | Temperature observation circuit |
| CN101621252B (en) * | 2009-08-07 | 2012-11-14 | 天津泛海科技有限公司 | Direct-current (DC) restoration and DC monitoring circuit |
| CN102385405B (en) * | 2010-08-27 | 2013-09-25 | 杭州中科微电子有限公司 | General band gap reference starting circuit |
| CN107770920A (en) * | 2017-12-05 | 2018-03-06 | 河南孚点电子科技有限公司 | A kind of LED drive circuit occurred based on dipulse |
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