CN118011343A - ZYNQ-based radar signal processing method and system - Google Patents
ZYNQ-based radar signal processing method and system Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
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Abstract
The invention relates to radar signal processing, in particular to a ZYNQ-based radar signal processing method and a ZYNQ-based radar signal processing system, wherein a radar receives an analog echo signal, converts the analog echo signal into a digital echo signal and sends the digital echo signal to a PL end of the ZYNQ; the PL terminal preprocesses the received digital echo signals; the PL end completes the distance dimension Fourier transform, the speed dimension Fourier transform and the received digital wave beam DBF formation, and generates speed dimension FFT data; the PS end of ZYNQ reads the speed dimension FFT data and carries out CFAR detection and angle detection; the PS end performs point trace condensation to generate a radar track, and sends the radar track to the upper computer; the technical scheme provided by the invention can effectively overcome the defects of lower signal processing efficiency and higher research and development cost in the prior art.
Description
Technical Field
The invention relates to radar signal processing, in particular to a radar signal processing method and system based on ZYNQ.
Background
Radar signal processing has a crucial impact on the performance of radar systems. Radar signal processing is a core link in a radar system, and extracts useful information by performing a series of complex processing and analysis on a received radar signal, thereby completing tasks such as target detection, tracking, recognition and the like.
However, the existing radar signal processing system has low signal processing efficiency, complex system structure and high research and development cost.
Disclosure of Invention
(One) solving the technical problems
Aiming at the defects existing in the prior art, the invention provides a ZYNQ-based radar signal processing method and a ZYNQ-based radar signal processing system, which can effectively overcome the defects of lower signal processing efficiency and higher research and development cost existing in the prior art.
(II) technical scheme
In order to achieve the above purpose, the invention is realized by the following technical scheme:
a radar signal processing method based on ZYNQ comprises the following steps:
S1, a radar receives an analog echo signal, converts the analog echo signal into a digital echo signal and sends the digital echo signal to a PL end of ZYNQ;
s2, the PL terminal preprocesses the received digital echo signals;
S3, the PL end completes the distance dimension Fourier transform, the speed dimension Fourier transform and the received digital wave beam DBF formation, and generates speed dimension FFT data;
s4, reading speed dimension FFT data at a PS end of the ZYNQ, and performing CFAR detection and angle detection;
s5, performing point trace aggregation on the PS end to generate a radar track, and transmitting the radar track to the upper computer.
Preferably, the radar in S1 receives an analog echo signal, converts the analog echo signal into a digital echo signal, and sends the digital echo signal to the PL end of the ZYNQ, which includes:
The radar receives the analog echo signal, converts the analog echo signal into a digital echo signal through the AD chip and sends the digital echo signal to the PL end of the ZYNQ;
the AD chip has L paths, each AD chip has 4 paths of receiving channels, and the total of 4*L paths of receiving channels are used for receiving analog echo signals.
Preferably, the PL end in S2 pre-processes the received digital echo signal, including:
And the PL terminal performs AD data extraction and low-pass filtering processing on the received digital echo signals, converts the filtered data from fixed point numbers to floating point numbers, and performs floating point number multiplication operation on the floating point numbers and the Hanning window function to obtain preprocessed data.
Preferably, the PL end performs AD data extraction and low-pass filtering processing on the received digital echo signal, converts the filtered data from fixed point numbers to floating point numbers, and performs floating point number multiplication operation on the floating point numbers and hanning window functions to obtain preprocessed data, where the processing includes:
The FPGA self-carried FIR Compiler instantiates 4*L paths of IP verification to realize 2 times extraction and low-pass filtering treatment, the instantiates 4*L paths of Floating-point core Fixed-to-float to convert the 16-bit Fixed point number into a 32-bit Floating point number, and the instantiates 4*L paths of Floating-point core multiplexing to carry out Floating point number multiplication operation on the 32-bit Floating point number and a Hanning window function to obtain preprocessed data.
Preferably, the PL end in S3 performs a distance dimension fourier transform, a velocity dimension fourier transform, and a received digital beam DBF forming, and generates velocity dimension FFT data, including:
S31, in single pulse time, intercepting M points for distance dimension Fourier transform to 4*L paths of preprocessed data to obtain distance dimension FFT data;
s32, performing parallel complex multiplication operation on the distance dimension FFT data and the sum and difference weighting coefficient, obtaining DBF and difference dimension data based on an operation result, and storing the DBF and the difference dimension data into a sum and difference data storage area;
S33, repeating the steps S31 and S32 until N pulse times are reached, wherein N.times.M.times.2 DBFs and difference dimension data are stored in the sum and difference data storage area;
s34, performing speed dimension Fourier transform on the DBF and the difference dimension data in the sum and difference data storage area to obtain speed dimension FFT data, and storing the speed dimension FFT data into the speed dimension FFT data storage area.
Preferably, in S34, performing a speed dimension fourier transform on the DBF and the difference dimension data in the sum and difference data storage area to obtain speed dimension FFT data, and storing the speed dimension FFT data in the speed dimension FFT data storage area, including:
when DBF and difference dimension data are stored in the first and the difference data storage areas, the DBF and the difference dimension data in the second and the difference data storage areas are read, N-point speed dimension Fourier transform is carried out after windowing function processing is completed, and M times of speed dimension Fourier transform are processed;
When the DBF and the difference dimension data are stored in the second and the difference data storage areas, the DBF and the difference dimension data in the first and the difference data storage areas are read, and speed dimension Fourier transformation is carried out;
And obtaining speed dimension FFT data after finishing the speed dimension Fourier transform, and storing the speed dimension FFT data into a speed dimension FFT data storage area through an AXI bus.
Preferably, the PS end of ZYNQ in S4 reads the speed-dimensional FFT data, and before performing CFAR detection and angle detection, the method includes:
After all the speed dimension FFT data storage is completed, the PL terminal sends an interrupt to the PS terminal.
Preferably, the PS end of ZYNQ in S4 reads the speed dimension FFT data, performs CFAR detection and angle detection, and includes:
S41, after a CPU1 core at the PS end receives the interrupt signal, reading speed dimension FFT data in a speed dimension FFT data storage area;
S42, performing CFAR detection to obtain the distance and the speed of the target, detecting the angle of the target by adopting a sum-difference angle measurement algorithm, and storing the distance, the speed and the angle of the target as point trace data into a point trace data storage area;
S43, the CPU1 core at the PS end sends a soft interrupt to the CPU0 core.
Preferably, in S5, the PS end performs point trace condensation to generate a radar track, and sends the radar track to an upper computer, including:
s51, after a CPU0 core at the PS end receives the soft interrupt signal, reading the trace point data in the trace point data storage area;
s52, performing point trace aggregation based on the point trace data to generate a radar track, and transmitting the radar track to an upper computer through a network chip.
A radar signal processing system based on ZYNQ comprises a ZYNQ, an AD chip, a first DDR memory, a second DDR memory and a network chip, wherein the ZYNQ comprises a PL end and a PS end, the PL end is connected with the AD chip and the first DDR memory, and the PS end is connected with the second DDR memory and the network chip;
The AD chip converts an analog echo signal received by the radar into a digital echo signal and then sends the digital echo signal to the PL terminal;
The PL terminal is used for preprocessing the received digital echo signals, completing distance dimension Fourier transform, speed dimension Fourier transform and received digital wave beam DBF formation, and generating speed dimension FFT data based on DBF and difference dimension data;
The PS end comprises a CPU1 core running in a CPU1 program area and a CPU0 core running in a CPU0 program area, wherein the CPU1 core reads speed dimension FFT data, performs CFAR detection and angle detection to generate trace data, performs trace condensation based on the trace data to generate a radar track, and sends the radar track to the upper computer through the network chip;
A first DDR memory including a first and a second and a difference data memory area for storing DBF and difference dimension data;
the second DDR memory includes a speed dimension FFT data storage area for storing speed dimension FFT data, a trace data storage area for storing trace data, and a CPU1 program area and a CPU0 program area.
(III) beneficial effects
Compared with the prior art, the radar signal processing method and system based on ZYNQ provided by the invention have the advantages that the FPGA is used for collecting multichannel data in parallel, the distance dimension Fourier transform, the speed dimension Fourier transform and the received digital wave beam DBF are completed, the CPU1 core in the dual-core ARM is used for completing CFAR detection and target angle extraction, the CPU0 core in the dual-core ARM is used for performing trace point condensation to generate a radar track, and the radar track is sent to an upper computer through a network chip; in addition, the whole radar signal processing process adopts floating point number operation, and compared with fixed point number operation, the precision of the floating point number operation is higher.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic flow chart of the present invention;
FIG. 2 is a schematic diagram of the system of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in FIG. 1, S1, the radar receives an analog echo signal, converts the analog echo signal into a digital echo signal and sends the digital echo signal to the PL end of ZYNQ, and the method specifically comprises the following steps:
The radar receives the analog echo signal, converts the analog echo signal into a digital echo signal through the AD chip and sends the digital echo signal to the PL end of the ZYNQ;
the AD chip has L paths, each AD chip has 4 paths of receiving channels, and the total of 4*L paths of receiving channels are used for receiving analog echo signals.
In this embodiment, the AD chip selects an AD8285 chip, and the AD chip has 2 channels, and a total of 8 channels of receiving channels are used for receiving the analog echo signals, and is suitable for the distance dimension fourier transform of 1024 points, and the velocity dimension fourier transform of 256 points.
S2, the PL terminal preprocesses the received digital echo signals, and specifically comprises the following steps:
And the PL terminal performs AD data extraction and low-pass filtering processing on the received digital echo signals, converts the filtered data from fixed point numbers to floating point numbers, and performs floating point number multiplication operation on the floating point numbers and the Hanning window function to obtain preprocessed data.
Specifically, the PL end performs AD data extraction and low-pass filtering processing on a received digital echo signal, converts filtered data from a fixed point number to a floating point number, and performs floating point multiplication operation on the floating point number and a hanning window function to obtain preprocessed data, where the processing includes:
The method comprises the steps of realizing 2 times extraction and low-pass filtering processing through an FPGA self-carried FIR Compiler instantiation 4*L (L=2) path IP card, converting 16-bit Fixed point numbers into 32-bit Floating point numbers through an instantiation 4*L path Floating-point core Fixed-to-float, and carrying out Floating point multiplication operation on the 32-bit Floating point numbers and a hanning window function through an instantiation 4*L path Floating-point core multiplexing to obtain preprocessed data.
S3, the PL end completes the distance dimension Fourier transform, the speed dimension Fourier transform and the received digital wave beam DBF formation, and generates speed dimension FFT data, which concretely comprises the following steps:
S31, in single pulse time, intercepting M (M=1024) points for distance dimension Fourier transform to 4*L (L=2) paths of preprocessed data to obtain distance dimension FFT data;
s32, performing parallel complex multiplication operation on the distance dimension FFT data and the sum and difference weighting coefficient, obtaining DBF and difference dimension data based on an operation result, and storing the DBF and the difference dimension data into a sum and difference data storage area;
s33, repeating S31 and S32 until N (n=256) pulse times are reached, where n×m×2 DBFs and difference dimension data are stored in the sum and difference data storage area;
s34, performing speed dimension Fourier transform on the DBF and the difference dimension data in the sum and difference data storage area to obtain speed dimension FFT data, and storing the speed dimension FFT data into the speed dimension FFT data storage area.
Specifically, performing a speed dimension fourier transform on the DBF and the difference dimension data in the sum and difference data storage area in S34 to obtain speed dimension FFT data, and storing the speed dimension FFT data in the speed dimension FFT data storage area, including:
when DBF and difference dimension data are stored in the first and the difference data storage areas, the DBF and the difference dimension data in the second and the difference data storage areas are read, N-point speed dimension Fourier transform is carried out after windowing function processing is completed, and M times of speed dimension Fourier transform are processed;
When the DBF and the difference dimension data are stored in the second and the difference data storage areas, the DBF and the difference dimension data in the first and the difference data storage areas are read, and speed dimension Fourier transformation is carried out;
And obtaining speed dimension FFT data after finishing the speed dimension Fourier transform, and storing the speed dimension FFT data into a speed dimension FFT data storage area through an AXI bus.
The PS end of ZYNQ in S4 reads the speed dimension FFT data, and before CFAR detection and angle detection, the method comprises the following steps:
After all the speed dimension FFT data storage is completed, the PL terminal sends an interrupt to the PS terminal.
S4, reading speed dimension FFT data by a PS end of ZYNQ, and performing CFAR detection and angle detection, wherein the method specifically comprises the following steps of:
S41, after a CPU1 core at the PS end receives the interrupt signal, reading speed dimension FFT data in a speed dimension FFT data storage area;
S42, performing CFAR detection to obtain the distance and the speed of the target, detecting the angle of the target by adopting a sum-difference angle measurement algorithm, and storing the distance, the speed and the angle of the target as point trace data into a point trace data storage area;
S43, the CPU1 core at the PS end sends a soft interrupt to the CPU0 core.
S5, performing point trace condensation on the PS end to generate a radar track, and transmitting the radar track to an upper computer, wherein the method specifically comprises the following steps of:
s51, after a CPU0 core at the PS end receives the soft interrupt signal, reading the trace point data in the trace point data storage area;
s52, performing point trace aggregation based on the point trace data to generate a radar track, and transmitting the radar track to an upper computer through a network chip.
In the technical scheme of the application, the application also discloses a radar signal processing system based on ZYNQ, which comprises a ZYNQ, an AD chip, a first DDR memory, a second DDR memory and a network chip, wherein the ZYNQ comprises a PL end and a PS end, the PL end is connected with the AD chip and the first DDR memory, and the PS end is connected with the second DDR memory and the network chip;
The AD chip converts an analog echo signal received by the radar into a digital echo signal and then sends the digital echo signal to the PL terminal;
The PL terminal is used for preprocessing the received digital echo signals, completing distance dimension Fourier transform, speed dimension Fourier transform and received digital wave beam DBF formation, and generating speed dimension FFT data based on DBF and difference dimension data;
The PS end comprises a CPU1 core running in a CPU1 program area and a CPU0 core running in a CPU0 program area, wherein the CPU1 core reads speed dimension FFT data, performs CFAR detection and angle detection to generate trace data, performs trace condensation based on the trace data to generate a radar track, and sends the radar track to the upper computer through the network chip;
A first DDR memory including a first and a second and a difference data memory area for storing DBF and difference dimension data;
the second DDR memory includes a speed dimension FFT data storage area for storing speed dimension FFT data, a trace data storage area for storing trace data, and a CPU1 program area and a CPU0 program area.
In this embodiment, ZYNQ selects XC7Z035-2FFG676I. The first sum and difference data storage area has a head address of 0x100_000 and a data length of 0x100_000; the first address of the second sum and difference data storage area is 0x200_000 and the data length is 0x100_000;
The first address of the speed dimension FFT data storage area is 0x3000_0000, and the data length is 0x0080_0000; the head address of the trace data storage area is 0x2000_0000, and the data length is 0x0010_0000; the head address of the CPU1 program area is 0x1000_0000, and the data length is 0x08ff_F000; the head address of the CPU0 program area is 0x0010_0000, and the data length is 0x0FE0_0000.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A radar signal processing method based on ZYNQ is characterized in that: the method comprises the following steps:
S1, a radar receives an analog echo signal, converts the analog echo signal into a digital echo signal and sends the digital echo signal to a PL end of ZYNQ;
s2, the PL terminal preprocesses the received digital echo signals;
S3, the PL end completes the distance dimension Fourier transform, the speed dimension Fourier transform and the received digital wave beam DBF formation, and generates speed dimension FFT data;
s4, reading speed dimension FFT data at a PS end of the ZYNQ, and performing CFAR detection and angle detection;
s5, performing point trace aggregation on the PS end to generate a radar track, and transmitting the radar track to the upper computer.
2. The ZYNQ-based radar signal processing method according to claim 1, wherein: in S1, the radar receives an analog echo signal, converts the analog echo signal into a digital echo signal, and sends the digital echo signal to a PL end of ZYNQ, and the method comprises the following steps:
The radar receives the analog echo signal, converts the analog echo signal into a digital echo signal through the AD chip and sends the digital echo signal to the PL end of the ZYNQ;
the AD chip has L paths, each AD chip has 4 paths of receiving channels, and the total of 4*L paths of receiving channels are used for receiving analog echo signals.
3. The ZYNQ-based radar signal processing method according to claim 2, wherein: the PL end in S2 pre-processes the received digital echo signal, including:
And the PL terminal performs AD data extraction and low-pass filtering processing on the received digital echo signals, converts the filtered data from fixed point numbers to floating point numbers, and performs floating point number multiplication operation on the floating point numbers and the Hanning window function to obtain preprocessed data.
4. A ZYNQ-based radar signal processing method according to claim 3, wherein: the PL end performs AD data extraction and low-pass filtering processing on the received digital echo signal, converts the filtered data from fixed point numbers to floating point numbers, and performs floating point number multiplication operation on the floating point numbers and hanning window functions to obtain preprocessed data, where the processing includes:
The FPGA self-carried FIR Compiler instantiates 4*L paths of IP verification to realize 2 times extraction and low-pass filtering treatment, the instantiates 4*L paths of Floating-point core Fixed-to-float to convert the 16-bit Fixed point number into a 32-bit Floating point number, and the instantiates 4*L paths of Floating-point core multiplexing to carry out Floating point number multiplication operation on the 32-bit Floating point number and a Hanning window function to obtain preprocessed data.
5. A ZYNQ-based radar signal processing method according to claim 3, wherein: the PL end in S3 completes the distance dimension fourier transform, the velocity dimension fourier transform, and the received digital beam DBF formation, and generates velocity dimension FFT data, including:
S31, in single pulse time, intercepting M points for distance dimension Fourier transform to 4*L paths of preprocessed data to obtain distance dimension FFT data;
s32, performing parallel complex multiplication operation on the distance dimension FFT data and the sum and difference weighting coefficient, obtaining DBF and difference dimension data based on an operation result, and storing the DBF and the difference dimension data into a sum and difference data storage area;
S33, repeating the steps S31 and S32 until N pulse times are reached, wherein N.times.M.times.2 DBFs and difference dimension data are stored in the sum and difference data storage area;
s34, performing speed dimension Fourier transform on the DBF and the difference dimension data in the sum and difference data storage area to obtain speed dimension FFT data, and storing the speed dimension FFT data into the speed dimension FFT data storage area.
6. The ZYNQ-based radar signal processing method according to claim 5, wherein: in S34, performing a speed dimension fourier transform on the DBF and the difference dimension data in the sum and difference data storage area to obtain speed dimension FFT data, and storing the speed dimension FFT data in the speed dimension FFT data storage area, including:
when DBF and difference dimension data are stored in the first and the difference data storage areas, the DBF and the difference dimension data in the second and the difference data storage areas are read, N-point speed dimension Fourier transform is carried out after windowing function processing is completed, and M times of speed dimension Fourier transform are processed;
When the DBF and the difference dimension data are stored in the second and the difference data storage areas, the DBF and the difference dimension data in the first and the difference data storage areas are read, and speed dimension Fourier transformation is carried out;
And obtaining speed dimension FFT data after finishing the speed dimension Fourier transform, and storing the speed dimension FFT data into a speed dimension FFT data storage area through an AXI bus.
7. The ZYNQ-based radar signal processing method according to claim 5, wherein: the PS end of ZYNQ in S4 reads the speed dimension FFT data, and before CFAR detection and angle detection, the method comprises the following steps:
After all the speed dimension FFT data storage is completed, the PL terminal sends an interrupt to the PS terminal.
8. The ZYNQ-based radar signal processing method according to claim 7, wherein: and S4, reading speed dimension FFT data by a PS end of ZYNQ, and performing CFAR detection and angle detection, wherein the method comprises the following steps:
S41, after a CPU1 core at the PS end receives the interrupt signal, reading speed dimension FFT data in a speed dimension FFT data storage area;
S42, performing CFAR detection to obtain the distance and the speed of the target, detecting the angle of the target by adopting a sum-difference angle measurement algorithm, and storing the distance, the speed and the angle of the target as point trace data into a point trace data storage area;
S43, the CPU1 core at the PS end sends a soft interrupt to the CPU0 core.
9. The ZYNQ-based radar signal processing method according to claim 8, wherein: s5, performing point trace condensation on the PS end to generate a radar track, and transmitting the radar track to an upper computer, wherein the method comprises the following steps:
s51, after a CPU0 core at the PS end receives the soft interrupt signal, reading the trace point data in the trace point data storage area;
s52, performing point trace aggregation based on the point trace data to generate a radar track, and transmitting the radar track to an upper computer through a network chip.
10. A ZYNQ-based radar signal processing system for performing the ZYNQ-based radar signal processing method according to any one of claims 1 to 9, characterized by: the ZYNQ comprises a PL end and a PS end, wherein the PL end is connected with the AD chip and the first DDR memory, and the PS end is connected with the second DDR memory and the network chip;
The AD chip converts an analog echo signal received by the radar into a digital echo signal and then sends the digital echo signal to the PL terminal;
The PL terminal is used for preprocessing the received digital echo signals, completing distance dimension Fourier transform, speed dimension Fourier transform and received digital wave beam DBF formation, and generating speed dimension FFT data based on DBF and difference dimension data;
The PS end comprises a CPU1 core running in a CPU1 program area and a CPU0 core running in a CPU0 program area, wherein the CPU1 core reads speed dimension FFT data, performs CFAR detection and angle detection to generate trace data, performs trace condensation based on the trace data to generate a radar track, and sends the radar track to the upper computer through the network chip;
A first DDR memory including a first and a second and a difference data memory area for storing DBF and difference dimension data;
the second DDR memory includes a speed dimension FFT data storage area for storing speed dimension FFT data, a trace data storage area for storing trace data, and a CPU1 program area and a CPU0 program area.
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