CN117998028A - Image acquisition controller structure based on hardware synchronization - Google Patents
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Abstract
The invention relates to an image acquisition controller structure based on hardware synchronization, which belongs to the technical field of digital camera image processing and comprises a data synchronization module, a data buffer module and a main control module. The controller is based on an AMBA system, and is mounted on a peripheral device on an AHB bus. The data synchronization module transmits the pixel data of the pixel clock domain of the external camera to the AHB bus clock domain, finishes 32bits ordering of the data and then sends the data to the data buffer module; the data buffer module is a FIFO with depth of 8 and bit width of 32bits and is used for buffering the data sent by the data synchronization module; the main control module mainly comprises a state machine and two sub-modules, and the jump of the state machine is completed by identifying the rising edge and the falling edge of the hardware synchronous signal; the data bit width and the ordering mode can be controlled by the AHB master device. The controller has simple structure and reliable transmission, and is suitable for the camera module supporting the hardware synchronization mode.
Description
Technical Field
The invention relates to the technical field of digital camera image processing, in particular to an image acquisition controller structure based on hardware synchronization.
Background
With the rapid development of imaging technologies, particularly camera modules, higher requirements are being placed on imaging quality, ease of use, and cost effectiveness. In the process of collecting image data, the microcontroller needs to receive the image data in the camera module supporting the hardware synchronization mode, and completes image data stream transmission according to the hardware synchronization signal.
The level of the vertical synchronization signal means the start and end of a frame of the image data, and the level of the horizontal synchronization signal means the start and end of a line of the image data. And during the effective period of the vertical synchronization and the horizontal synchronization signals, the AHB bus clock of the microcontroller is utilized to collect the image data of the pixel clock domain of the external camera module. How to correctly recognize the start and end of image data in the hardware synchronization mode and correctly transmit the image data is a problem that needs to be solved at present.
Disclosure of Invention
In order to solve the technical problems, the image acquisition controller structure based on hardware synchronization is used for acquiring digital camera pixel data supporting a hardware synchronization mode and comprises a data synchronization module, a data buffer module and a main control module;
The data synchronization module transmits the pixel data of the pixel clock domain to the AHB bus clock domain, finishes 32bits ordering of the data and then sends the data to the data buffer module;
The data buffer module buffers the data sent by the data synchronization module before the AHB bus reading instruction arrives;
The main control module adopts an AHB bus protocol, and configures a collected data bit width and a data ordering mode through an AHB interface; according to whether the hardware synchronous signal is effective or not, the control work of the hardware synchronous controller is completed;
the data synchronization module can perform bit width selection on the acquired data: 8bits, 10bits, 12bits, 14bits, and four sets of 8bits to form a 32-bit data register or two sets of 16bits to form a 32-bit data register according to different bit widths.
In one embodiment of the invention, the data buffer module is a depth 8, bit wide 32 bit FIFO that registers 32 bits of data from the data sync module.
In one embodiment of the present invention, the master control module includes a master state machine and two sub-modules; the two sub-modules are respectively: camera_reg and camera_irq;
The camera_reg module is used for analyzing an AHB bus protocol and comprises all configuration registers, state registers and data registers; the camera_irq module is used to generate interrupts.
In one embodiment of the present invention, the master state machine of the master control module includes 5 states:
IDLE, the main control module is in IDLE state, at this time, capture enabling capture_en is disabled, and when a capture opening enabling command is received, the main control module jumps to W_F_S;
the main control module is in a state of waiting for starting a frame, and jumps to an L_R state if detecting that the falling edge of a hardware vertical synchronization signal VSYNC, namely vsync_start is valid;
L_r: the main control module is in a row receiving state, at the moment, pixel data of the camera module are sequentially stored into the data register through the data synchronization module, and effective signals are generated and sent to the data buffer module; if the rising edge of the hardware horizontal synchronizing signal HSYNC is detected, namely hsync_end is valid, indicating that the line receiving is finished, and jumping to W_L_S; if the rising edge of the hardware synchronization vertical synchronization signal VSYNC is detected, namely vsync_end is valid, a frame is indicated to be ended, and the frame is jumped to F_E;
W_l_s: the main control module is in a waiting line starting state, and if the falling edge of the hardware horizontal synchronizing signal HSYNC is detected, namely hsync_start is valid, the line receiving is started, and the line is jumped to L_R; if the rising edge of the hardware synchronous vertical synchronous signal is detected, namely vsync_end is valid, a frame is indicated to be ended, and the frame is jumped to F_E;
F_e: the main control module is in a frame end state, and if the falling edge of the hardware vertical synchronization signal VSYNC is detected, namely vsync_start is valid, the main control module indicates that a new frame is continuously acquired and jumps to a W_F_S state; if capture_en disable is detected, jump to IDLE is made.
Compared with the prior art, the technical scheme of the invention has the following advantages: the image acquisition controller structure solves the problem that the camera module supporting the hardware synchronization mode transmits pixel data to the microcontroller, wherein the controller is simple in structure and reliable in transmission, and is suitable for the camera module hardware supporting the hardware synchronization mode to form benign software-hardware combination ecology.
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In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings.
FIG. 1 is a functional block diagram of an image acquisition controller based on hardware synchronization of the present invention;
FIG. 2 is a state diagram of a jump of the master state machine according to the present invention;
FIG. 3 is a master state machine jump timing diagram according to the present invention;
FIG. 4 is a bit width control timing diagram of the data synchronization module according to the present invention.
Detailed Description
As shown in a block diagram of an image acquisition controller based on hardware synchronization in fig. 1, the invention provides an image acquisition controller structure based on hardware synchronization, which is used for identifying a hardware synchronization signal, a pixel clock and pixel data of a camera module and comprises a data synchronization module, a data buffer module and a main control module.
And the data synchronization module transmits the pixel data of the pixel clock domain of the camera to the AHB bus clock domain, finishes 32bits ordering of the data and then sends the data to the data buffer module.
The data buffer module is a FIFO with depth of 8 and bit width of 32 bits and is used for buffering the data sent by the data synchronization module.
The main control module adopts an AHB bus protocol, and configures a transmission mode and a bit width through an AHB interface. And according to whether the hardware synchronous signal is effective or not, the control work of the hardware synchronous controller is completed.
Optionally, the data synchronization module shares four kinds of pixel data with bit width: 8bits, 10bits, 12bits and 14bits.
Optionally, the data synchronization module sends the data to the data buffer module in two modes: 4 groups of 8bits and 2 groups of 16bits.
The data synchronization module is used for completing data synchronization and data sequencing of pixel data with different bit widths according to the configuration information of the register. The data ordering mode is as follows: the first pixel data is arranged at the lower order of the data register, and the last pixel data is arranged at the upper order of the data register. When the register is full of 32-bit data, a data request is generated and sent to the data caching module. After receiving the data request, the host generates a reading instruction and reads the data in the cache module.
The main control module mainly comprises a main state machine and two sub-modules; the two sub-modules are divided into camera_reg and camera_irq.
The camera_reg module is used for analyzing an AHB bus protocol and comprises all configuration registers, state registers and data registers; the camera_irq module is used to generate interrupts.
FIG. 2 is a state diagram of a master state machine jump, comprising 5 states:
IDLE, the main control module is in IDLE state, at this time, capture enabling capture_en is disabled, and when a capture opening enabling command is received, the main control module jumps to W_F_S;
The main control module is in a state of waiting for starting a frame, and jumps to an L_R state if detecting that the falling edge of the hardware vertical synchronization signal VSYNC, namely vsync_start is valid.
L_r: the main control module is in a row receiving state, at this time, pixel data of the camera module are sequentially stored in the data register through the data synchronization module, and effective signals are generated and sent to the data buffer module. If the rising edge of the hardware horizontal synchronizing signal HSYNC is detected, namely hsync_end is valid, indicating that the line receiving is finished, and jumping to W_L_S; if a rising edge of the hardware sync vertical sync signal VSYNC, i.e., vsync_end is detected, it indicates that one frame is ended and jumps to f_e.
W_l_s: the main control module is in a waiting line starting state, and if the falling edge of the hardware horizontal synchronizing signal HSYNC is detected, namely hsync_start is valid, the line receiving is started, and the line is jumped to L_R; if a rising edge of the hardware synchronization vertical synchronization signal, i.e., vsync_end is detected to be valid, it indicates that one frame is ended and jumps to f_e.
F_e: the main control module is in a frame end state, and if the falling edge of the hardware vertical synchronization signal VSYNC is detected, namely vsync_start is valid, the main control module indicates that a new frame is continuously acquired and jumps to a W_F_S state; if capture_en disable is detected, jump to IDLE is made.
In the structure of the image acquisition controller according to this embodiment, fig. 3 is a state machine jump timing chart. Before the image is not captured, the main state machine is in the IDLE state. At time T1 the falling edge of PIXCLK enables capture of the enable signal capture_en, the master state machine goes into w_f_s. At a rising edge of time PIXLK, a hardware horizontal synchronization HSYNC and a hardware vertical synchronization VSYNC of the external camera module are valid, a level is pulled down, a falling edge of two hardware synchronization signals is detected, a line start signal hsync_start and a frame start signal vsync_start are respectively generated, and the main state machine enters an l_r state. At the time of the rising edge of PIXCLK at the time of T5, after the transmission of the pixel data of the row is completed, the hardware horizontal synchronization HSYNC signal is pulled high, the rising edge is detected by the main control module, and the main state machine enters a W_L_S state. At the time of T6, the PIXCLK rising edge, the next line data comes, the hardware horizontal synchronization HSYNC signal is pulled down, the main control module detects the falling edge, the main state machine enters the L_R state, and the new line image data acquisition is started. At the rising edge of PIXCLK at time T13, after one frame of transmission of the current image is finished, the hardware vertical synchronization signal VSYNC signal is pulled high, the rising edge is detected by the main control module, vsync_end is valid, and the main state machine enters the F_E state. If the following image is to be continuously acquired at the rising edge of PIXCLK at the time T14, the hardware vertical synchronizing signal is pulled down, the main control module detects the falling edge of the following image, the main state machine enters the L_R state from the W_F_S state, and new image data acquisition is started.
FIG. 4 illustrates bit width control in a data synchronization module. Firstly, a main control module camera_reg module is used for configuring data_width, and the data_width is configured to be 00 at the moment T1, which means that the current pixel data bit width is 8bits. At the rising edge of PIXCLK at time T2, the external camera module starts to transmit pixel data cam_d. At time T3, the PIXCLK registers the incoming first pixel data in the inner word in order, places it in the lower 8bits, and the second pixel data arrives at the same time. At time T4, the rising edge of PIXCLK will accept the second pixel data to be sorted and registered in inner word, put it in the lower 9 bits to the lower 16 bits, while the third pixel data arrives. At time point PIXCLK rising edge, the accepted third pixel data arrives at inner word 17 bits high to 24 bits high, while the fourth pixel data arrives. At the rising edge of PIXCLK at time T6, the fourth pixel data received is sorted and registered in inner word, and is placed in the upper 25 to upper 32 bits. At the time of PIXCLK falling edge at the time of T6, 32bits of data are fully stored in the inner word, a data request data_req is generated, the inner word is photographed and stored in a data register dr_reg, and when a bus reading instruction arrives, the data in dr_reg is read and pulled low. At the rising edge of PIXCLK at time T8, data_width is configured to be 10 through the AHB bus, which indicates that the pixel data bit width of the current camera module is 12 bits, and at this time, 12-bit-width data is input. At the rising edge of PIXCLK at time T9, the first 12 bits of data are high-order 0 bits complemented with 16 bits, the low 16 bits are registered in the inner word, and the second pixel data arrives at the same time. At time T10, the rising edge of PIXCLK complements the upper bit of the second 12-bit pixel data by 0 bit and 16 bits, and registers the upper 16 bits in the inner word. At time T10, the PIXCLK falls on, 32bits of data are filled in the inner word, a data request is generated, and the inner word is photographed and stored in the data register dr_reg. At time T11, the PIXCLK rising edge, the AHB bus read instruction arrives, the data in dr_reg is read, and data_req is pulled low.
As described in fig. 4, the case of configuring the data bit width to 12bits is the same as the case of configuring the data bit width to 10bits and the data bit width to 14bits, and the same transmission mode and transmission timing are adopted, wherein the data_width is configured to 01, which indicates that the current pixel data bit width is 10bits, and the data_width is configured to 11, which indicates that the current pixel data bit width is 14bits.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.
Claims (4)
1. An image acquisition controller structure based on hardware synchronization is used for acquiring digital camera pixel data supporting a hardware synchronization mode and is characterized by comprising a data synchronization module, a data buffer module and a main control module;
The data synchronization module transmits the pixel data of the pixel clock domain to the AHB bus clock domain, finishes 32bits ordering of the data and then sends the data to the data buffer module;
The data buffer module buffers the data sent by the data synchronization module before the AHB bus reading instruction arrives;
The main control module adopts an AHB bus protocol, and configures a collected data bit width and a data ordering mode through an AHB interface; according to whether the hardware synchronous signal is effective or not, the control work of the hardware synchronous controller is completed;
the data synchronization module can perform bit width selection on the acquired data: 8bits, 10bits, 12bits, 14bits, and four sets of 8bits to form a 32-bit data register or two sets of 16bits to form a 32-bit data register according to different bit widths.
2. The image acquisition controller architecture of claim 1, wherein: the data buffer module is a depth 8, 32 bit wide FIFO, registering 32 bits of data from the data synchronization module.
3. The image acquisition controller architecture of claim 1, wherein: the main control module comprises a main state machine and two sub-modules; the two sub-modules are respectively: camera_reg and camera_irq;
The camera_reg module is used for analyzing an AHB bus protocol and comprises all configuration registers, state registers and data registers; the camera_irq module is used to generate interrupts.
4. The image acquisition controller architecture of claim 3, wherein: the main state machine of the main control module comprises 5 states:
IDLE, the main control module is in IDLE state, at this time, capture enabling capture_en is disabled, and when a capture opening enabling command is received, the main control module jumps to W_F_S;
the main control module is in a state of waiting for starting a frame, and jumps to an L_R state if detecting that the falling edge of a hardware vertical synchronization signal VSYNC, namely vsync_start is valid;
L_r: the main control module is in a row receiving state, at the moment, pixel data of the camera module are sequentially stored into the data register through the data synchronization module, and effective signals are generated and sent to the data buffer module; if the rising edge of the hardware horizontal synchronizing signal HSYNC is detected, namely hsync_end is valid, indicating that the line receiving is finished, and jumping to W_L_S; if the rising edge of the hardware synchronization vertical synchronization signal VSYNC is detected, namely vsync_end is valid, a frame is indicated to be ended, and the frame is jumped to F_E;
W_l_s: the main control module is in a waiting line starting state, and if the falling edge of the hardware horizontal synchronizing signal HSYNC is detected, namely hsync_start is valid, the line receiving is started, and the line is jumped to L_R; if the rising edge of the hardware synchronous vertical synchronous signal is detected, namely vsync_end is valid, a frame is indicated to be ended, and the frame is jumped to F_E;
F_e: the main control module is in a frame end state, and if the falling edge of the hardware vertical synchronization signal VSYNC is detected, namely vsync_start is valid, the main control module indicates that a new frame is continuously acquired and jumps to a W_F_S state; if capture enable capture_en disable is detected, jump to IDLE is made.
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| CN1901708A (en) * | 2006-06-26 | 2007-01-24 | 华为技术有限公司 | Device, method and chip and cell phone for realizing image data collection |
| CN101521744A (en) * | 2009-04-17 | 2009-09-02 | 东南大学 | Video capture controller |
| CN110933382A (en) * | 2019-12-31 | 2020-03-27 | 哈尔滨理工大学 | Vehicle-mounted video image picture-in-picture display method based on FPGA |
| CN115189981A (en) * | 2022-06-30 | 2022-10-14 | 东风汽车集团股份有限公司 | Lin bus interface based on master-slave reusability |
| US20230281152A1 (en) * | 2022-03-07 | 2023-09-07 | Synaptics Incorporated | Image data reception via non-video interface |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1901708A (en) * | 2006-06-26 | 2007-01-24 | 华为技术有限公司 | Device, method and chip and cell phone for realizing image data collection |
| CN101521744A (en) * | 2009-04-17 | 2009-09-02 | 东南大学 | Video capture controller |
| CN110933382A (en) * | 2019-12-31 | 2020-03-27 | 哈尔滨理工大学 | Vehicle-mounted video image picture-in-picture display method based on FPGA |
| US20230281152A1 (en) * | 2022-03-07 | 2023-09-07 | Synaptics Incorporated | Image data reception via non-video interface |
| CN115189981A (en) * | 2022-06-30 | 2022-10-14 | 东风汽车集团股份有限公司 | Lin bus interface based on master-slave reusability |
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