CN117995872A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN117995872A CN117995872A CN202211324531.7A CN202211324531A CN117995872A CN 117995872 A CN117995872 A CN 117995872A CN 202211324531 A CN202211324531 A CN 202211324531A CN 117995872 A CN117995872 A CN 117995872A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 135
- 238000002513 implantation Methods 0.000 claims abstract description 18
- 239000000945 filler Substances 0.000 claims abstract description 13
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 23
- 238000005468 ion implantation Methods 0.000 claims description 21
- 238000010438 heat treatment Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000000463 material Substances 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The invention relates to a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: an isolation tub having a first conductivity type; the injection auxiliary structure is a plurality of grooves filled with fillers; a first well region of a first conductivity type extending continuously downward from the bottom of the implantation aid structure, below the isolation tub; a second well region of the first conductivity type located below the isolation tub and above the first well region; the injection auxiliary structure penetrates through the second well region in the vertical direction, and the second well region is in direct contact with the first well region and the isolation basin. The invention can form the first well region with deeper depth by arranging the injection auxiliary structure, so that the depth of the vertical pressure-resistant structure (the isolation basin, the second well region and the first well region) is deeper, and the vertical pressure-resistant structure can resist higher voltage.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.
Background
A complete integrated circuit is typically fabricated with a number of different devices on the same semiconductor die, so isolation structures must be added to isolate the different device units in isolation.
An exemplary isolation structure is to isolate different device cells using PN junctions. It is desirable to have a device with a higher withstand voltage (i.e., higher breakdown voltage) through an optimized isolation structure design. In addition, shrinking semiconductor device dimensions (typically on the order of nanometers) while ensuring that semiconductor device performance is not affected has been a technical challenge and challenge addressed by the semiconductor industry.
Disclosure of Invention
Based on this, it is necessary to provide a semiconductor structure having an isolation structure and a method of manufacturing the same, which has a high withstand voltage.
A semiconductor structure, comprising: an isolation tub having a first conductivity type; the injection auxiliary structure is a plurality of grooves filled with fillers; a first well region of a first conductivity type extending continuously downward from the bottom of the implantation aid structure, below the isolation tub; a second well region of the first conductivity type located below the isolation tub and above the first well region; the injection auxiliary structure penetrates into the second well region in the vertical direction, and the second well region is in direct contact with the first well region and the isolation basin.
In the semiconductor structure, the first well region having a deeper depth can be formed by providing the implantation auxiliary structure, so that the vertical voltage-resistant structure (isolation tub, second well region and first well region) has a deeper depth and can withstand a higher voltage. And the first well region with deeper depth can increase the curvature radius of the depletion line in the semiconductor structure serving as the isolation structure, and reduce the electric field intensity in the body, thereby effectively improving the reliability of the device and enhancing the withstand voltage of the device. In addition, due to the variation of the depletion line, the size of the lateral drift region can be effectively reduced under the same device withstand voltage.
In one embodiment, the front projection of the isolation basin on the upper surface of the first well region completely covers the first well region.
In one embodiment, the orthographic projection of the isolation basin on the upper surface of the second well region completely covers the second well region.
In one embodiment, the first well region is an independent region corresponding to each of the trenches one to one.
In one embodiment, the first well region is a large area communicating with each other under each of the trenches.
In one embodiment, the first well region includes a plurality of small regions that are not in communication with each other, and each of the small regions is located below at least one of the trenches.
In one embodiment, the semiconductor structure further includes a buried region of the first conductivity type disposed in the second well region.
In one embodiment, the doping concentration of the first conductivity type buried region is greater than the doping concentrations of the isolation tub, the second well region, and the first well region.
In one embodiment, the semiconductor structure is a high voltage integrated circuit and the isolation tub is a high voltage isolation tub.
In one embodiment, the semiconductor structure further includes a high side drive circuit located in the isolation tub.
In one embodiment, the semiconductor structure further comprises: a low voltage well region having a second conductivity type adjacent to the isolation tub, the first and second conductivity types being opposite conductivity types; and the low-side driving circuit is positioned in the low-voltage well region.
In one embodiment, the semiconductor structure further comprises: and the insulating isolation structure is positioned at and near the junction of the isolation basin and the low-voltage well region.
In one embodiment, the semiconductor structure further comprises: and the second conduction type buried region is positioned below the low-voltage well region and is in direct contact with the low-voltage well region.
In one embodiment, the second conductivity type buried region has a doping concentration greater than that of the low voltage well region.
In one embodiment, the semiconductor structure further comprises: and the substrate is provided with a second conduction type, and the first well region, the second well region and the second conduction type buried region are positioned in the substrate.
In one embodiment, each of the channels extends downwardly from the bottom of the isolation basin.
In one embodiment, each of the channels extends downwardly from the top of the isolation basin.
A method of fabricating a semiconductor structure, comprising: acquiring a wafer with a plurality of grooves formed thereon; forming a first conductive type ion implantation region under the plurality of trenches by ion implantation; filling a filler in the plurality of trenches; performing heat treatment to diffuse the first conductive type ion implantation region to form a first well region; the wafer also comprises a second well region positioned on the first well region and an isolation basin positioned on the second well region, wherein the second well region is formed by diffusing a first conductive type doped region in the wafer through the heat treatment step, and each groove penetrates into the second well region; the isolation basin has a first conductivity type.
In the method for manufacturing the semiconductor structure, the first well region having a large depth can be formed without using a high-energy implantation device by performing the implantation through the trench, and therefore, the vertical withstand voltage structure (isolation tub, second well region, and first well region) has a deeper depth and can withstand a higher voltage. And the first well region with deeper depth can increase the curvature radius of the depletion line in the semiconductor structure serving as the isolation structure, and reduce the electric field intensity in the body, thereby effectively improving the reliability of the device and enhancing the withstand voltage of the device. In addition, due to the variation of the depletion line, the size of the lateral drift region can be effectively reduced under the same device withstand voltage.
In one embodiment, the first conductive type doped region is formed by ion implantation after the step of forming a first conductive type ion implanted region under the plurality of trenches by ion implantation and before the heat treatment step, and the heat treatment step diffuses the first conductive type ion implanted region to form a first well region, diffuses the first conductive type doped region to form a second well region, and further includes a step of forming an epitaxial layer on the second well region and forming the isolation tub in the epitaxial layer.
In one embodiment, in the step of obtaining a wafer with a plurality of trenches formed therein, isolation trenches are formed in the obtained wafer, and each trench extends downward from a top of the isolation trench.
In one embodiment, the semiconductor structure is a high voltage integrated circuit and the isolation tub is a high voltage isolation tub.
In one embodiment, the method further comprises forming a low-voltage well region adjacent to the isolation tub; the low-voltage well region has a second conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types; the isolation tub is for setting a high-side driving circuit therein, and the low-voltage well region is for setting a low-side driving circuit therein.
In one embodiment, the method further comprises forming an insulating isolation structure at and near the junction of the isolation tub and the low voltage well region.
In one embodiment, the step of forming the insulating isolation structure further comprises forming a buried region of a second conductivity type; the low-voltage well region is located on the second conductive type buried region.
In one embodiment, the step of forming the insulating isolation structure further comprises forming a buried region of the first conductivity type in the second well region.
Drawings
For a better description and illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of the disclosed invention, the presently described embodiments and/or examples, and any of the presently understood modes of carrying out the invention.
FIG. 1a is a layout of a portion of a semiconductor structure in one embodiment, FIG. 1b is a layout of the isolation structure 130 of FIG. 1a removed, and FIG. 1c is a layout of the isolation structure 130 of FIG. 1a after semitransparent;
FIG. 2 is a schematic cross-sectional view along line AA' in FIG. 1 c;
FIG. 3 is a schematic diagram of a trench in a strip shape in an embodiment;
FIG. 4a is a schematic cross-sectional view of a portion of a semiconductor structure in an embodiment in which the first well region is a large area that communicates with each other under each trench, and FIG. 4b is a schematic view of a depletion line of the structure shown in FIG. 4 a;
FIG. 5 is a schematic cross-sectional view of a portion of a semiconductor structure in another embodiment;
FIG. 6 is a flow chart of a method of fabricating a semiconductor structure in one embodiment;
FIGS. 7 a-7 i are schematic cross-sectional views of a semiconductor structure during fabrication in accordance with one embodiment;
Fig. 8 is a flow chart of a method of fabricating a semiconductor structure in another embodiment.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
The term "semiconductor" used herein is a technical term commonly used by those skilled in the art, for example, for P-type and N-type impurities, p+ type represents P type with heavy doping concentration, P type with medium doping concentration, P-type represents P type with light doping concentration, n+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents N type with light doping concentration.
BCD (bipolarcmos-DMOS technology) can be generally classified into high voltage BCD, high density BCD, and high power BCD according to industry standards. The high voltage BCD technology may also be referred to as HVIC (high voltage integrated circuit), and generally refers to BCD technology with a withstand voltage above 100V, and is widely used in the fields of AC-DC power supply, LED driving, high voltage gate driving (motor driving), and the like, where the withstand voltage of the corresponding power device may reach 500V to 800V.
HVICs are commonly used to drive motors, typically half-bridge drive circuits, in high voltage gate drive applications. The chip includes a low side (lowside) driver circuit and a high side (highside) driver circuit therein, wherein the high side driver circuit may be disposed in a high voltage region isolation tub.
It is desirable to have an isolation withstand voltage structure such as a high voltage isolation tub in a high voltage integrated circuit that can withstand a greater voltage. In addition, shrinking semiconductor device dimensions (typically on the order of nanometers) while ensuring that semiconductor device performance is not affected has been a technical challenge and challenge addressed by the semiconductor industry.
The application provides a novel isolation structure (semiconductor structure) for improving pressure resistance by deep trench injection, which can be applied to a high-voltage isolation basin of an HVIC (high-voltage integrated circuit) and other isolation structures, such as a low-voltage region isolation basin structure, an LDMOS isolation structure and the like. Fig. 1a is a Layout (Layout) of a portion of the semiconductor structure in an embodiment, and since the isolation structure 130 blocks a portion of the structure, the isolation structure 130 is removed in fig. 1b for comparison, fig. 1c is a Layout after the isolation structure 130 is semitransparent in fig. 1a, and fig. 2 is a schematic cross-sectional view along line AA' in fig. 1 c. In the embodiment shown in fig. 2, the semiconductor structure includes an isolation tub 118, an implant assist structure, a first well region 112, and a second well region 114. The isolation basin 118 has a first conductivity type. In one embodiment of the present application, the isolation tub 118 is used to provide a high side (highside) drive circuit in the half-bridge drive circuit, i.e., a high side drive circuit (not shown in FIG. 2) is provided in the isolation tub 118. The implantation aid structure is a plurality of trenches 110 filled with a filler, and is at least partially located in the second well region 114, and the first well region 112 is formed by ion implantation at the bottom of the trenches 110. In order for the well depth of first well region 112 to meet our requirements, trench 110 needs to have a sufficient depth. First well region 112 has a first conductivity type and extends continuously downward from the bottom of trench 110, below second well region 114. The second well region 114 has a first conductivity type and is located under the isolation tub 118. The trench 110 penetrates the second well region 114 in the vertical direction, and the second well region 114 is in direct contact with the first well region 112 and the isolation tub 118. In other embodiments, the grooves 110 may also be disposed obliquely. In the embodiment shown in fig. 2, the semiconductor structure further comprises a substrate 102. The substrate 102 has a second conductivity type, and the first well region 112 and the second well region 114 are located in the substrate 102. In one embodiment of the application, the semiconductor structure is a high voltage integrated circuit and the isolation tub 118 is a high voltage isolation tub. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.
In the semiconductor structure, since the first well region 112 having a deeper depth can be formed by providing the implantation auxiliary structure, the vertical withstand voltage structure (isolation tub 118, second well region 114, and first well region 112) has a deeper depth, and can withstand a higher voltage. And the first well region with deeper depth can increase the curvature radius of the depletion line in the semiconductor structure serving as an isolation structure (see fig. 4b below), and reduce the electric field intensity in the body, thereby effectively improving the reliability of the device and enhancing the withstand voltage of the device. In addition, due to the variation of the depletion line, the size of the lateral drift region can be effectively reduced under the same device withstand voltage.
In the embodiment shown in fig. 2, the semiconductor structure further comprises a buried region 116 of the first conductivity type provided in the second well region 114. In one embodiment of the present application, each trench 110 penetrates into the first conductivity type buried region 116 or penetrates through the first conductivity type buried region 116. In one embodiment of the present application, the doping concentration of the first conductivity type buried region 116 is greater than the doping concentrations of the isolation tub 118, the second well region 114, and the first well region 112.
In the embodiment shown in fig. 2, the semiconductor structure further includes a low-voltage well region 122. The low voltage well region 122 has a second conductivity type adjacent to the isolation tub 118. In one embodiment of the present application, low-voltage well region 122 is used to provide a low-side (lowside) drive circuit in the half-bridge drive circuit, i.e., a low-side drive circuit (not shown in fig. 2) is provided in low-voltage well region 122.
In the embodiment shown in fig. 2, the semiconductor structure further includes a buried region 124 of the second conductivity type, which is located below the low-voltage well region 122 and is in direct contact with the low-voltage well region 122. In the embodiment shown in fig. 2, a buried region 124 of the second conductivity type is located in the substrate 102. In one embodiment of the present application, the doping concentration of the second conductivity type buried region 124 is greater than the doping concentration of the low voltage well region 122.
In the embodiment shown in fig. 2, the semiconductor structure further includes an insulating isolation structure 130 located at and near the interface of isolation tub 118 and low voltage well region 122. The material of the insulating isolation structure 130 may be silicon oxide, such as silicon dioxide. Specifically, the structure may be a LOCOS (local oxidation of silicon isolation) structure or an STI (shallow trench isolation) structure.
In one embodiment of the present application, the orthographic projection of isolation tub 118 on the upper surface of first well region 112 completely covers first well region 112, i.e., isolation tub 118 is directly above first well region 112 and has a larger area than first well region 112; the isolation tub 118 is located on the upper surface of the second well region 114 in front projection to completely cover the second well region 114, and the isolation tub 118 is located directly above the second well region 114 and has a larger area than the second well region 114.
In the embodiment shown in fig. 1a, each trench 110 has a columnar structure with a cross-section of a hole shape. In other embodiments, the grooves 110 may have other shapes, such as a stripe shape as shown in fig. 3.
The material of the filler in the trench 110 may be one or more of polysilicon, silicon oxide, monocrystalline silicon, etc., and may be selected in combination with factors such as manufacturing cost. The filling material in the groove 110 can be a dielectric material embedded with a conductive structure, and the conductive structure can float or be externally connected with a potential. In the embodiment shown in fig. 2, the first well region 112 is an independent region, i.e., an independent globular well, in one-to-one correspondence with each trench 110. In another embodiment of the present application, the first well region 112 is a large area under each trench 110 communicating with each other, i.e., the first conductive type ions implanted through the trench 110 are integrated after thermal diffusion, as shown in fig. 4 a. Fig. 4b is a schematic diagram of the depletion line of the structure shown in fig. 4a, and the depletion line on the surface of the structure shown in fig. 4b is far away from the high voltage end (drain end), so that the size of the lateral drift region can be effectively reduced under the same device withstand voltage. In yet another embodiment of the present application, the first well region 112 includes a plurality of small regions that are not connected to each other, and each small region is located under at least one trench 110, for example, the trenches 110 are arranged in an array, the first conductive type ions implanted under each column of trenches 110 are connected together after thermal diffusion, but the first conductive type regions under the trenches 110 of different columns are not connected to each other, so that the first well region 112 has a multi-column structure.
Fig. 5 is a schematic cross-sectional view of a portion of the structure of a semiconductor structure in another embodiment, which differs from the embodiment shown in fig. 4a mainly in that in the embodiment shown in fig. 4a (and fig. 2) the trench 110 extends downwards from the bottom of the isolation basin 118, whereas in the embodiment shown in fig. 5 the trench 110 extends downwards from the top of the isolation basin 118.
The application correspondingly provides a manufacturing method of the semiconductor structure. Fig. 6 is a flow chart of a method of fabricating a semiconductor structure in one embodiment, comprising the steps of:
s610, a wafer with a plurality of trenches formed therein is obtained.
In one embodiment of the present application, a deep trench serving as an injection auxiliary structure may be formed in the substrate, and then an isolation basin is formed on the deep trench, so that the deep trench extends downward from the bottom of the isolation basin; an epitaxial layer may be formed on the substrate (the isolation tub is formed in the epitaxial layer) and then the deep trench may be formed so that the deep trench extends downward from the top of the isolation tub. Fig. 7a to 7i illustrate an embodiment in which a deep trench is formed first and then an isolation tub is formed on the deep trench. Referring to fig. 7a, a plurality of trenches 710 are first formed in a substrate 702, and specifically, after a mask layer 792 is formed, the trenches 710 extending downward from a first surface (front surface) of the substrate 702 are formed by etching (the mask layer 792 serves as an etching barrier), and the mask layer 792 may be a photoresist layer formed by photolithography. In one embodiment of the application, the sidewalls of the deep trenches are perpendicular to the bottom wall, or the sidewalls of the deep trenches are oblique to the bottom wall.
In one embodiment of the present application, the substrate 702 is a semiconductor substrate, and the material may be undoped monocrystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like, and may be at least one of the following materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors. In the embodiment shown in fig. 7a, the substrate 702 is formed from a single crystal silicon of the second conductivity type.
S620, forming a first conductive type ion implantation region under each trench by ion implantation.
Referring to fig. 7b, by using the trench 710 as an implantation aid, a small implantation energy is required to obtain a deep depth of the first conductive type ion implantation region 711, thereby eliminating the need for using an expensive high energy ion implantation device. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.
S630, filling the filling material into each trench.
Referring to fig. 7c, in one embodiment of the present application, a filler may be formed in the trench 710 by a deposition process after removing the mask layer 792, and the filler may be made of a wide range of materials, such as polysilicon, silicon oxide, monocrystalline silicon, etc., and may be specifically selected in combination with factors such as manufacturing cost.
And S640, performing heat treatment to diffuse the first conductive type ion implantation region to form a first well region.
In one embodiment of the present application, step S640 is preceded by the step of forming the first conductive-type doped region 713. In the embodiment shown in fig. 7d, the photoresist layer 794 is formed by photolithography, and then the first conductive type ions are implanted into the front surface of the substrate 702 to form the first conductive type doped region 713. The first conductivity type doped region 713 diffuses to form a second well region 714 and the first conductivity type ion implanted region 711 diffuses to form a first well region 712 after the heat treatment (push well). In the embodiment shown in fig. 7d, a pad oxide layer (not labeled in fig. 7 d) may also be formed on the front side of the substrate 702 prior to photolithography.
An epitaxial layer may be formed on the second well region 714 after step S640, and then isolation tub 718 is formed in the epitaxial layer. The second well region 714 is in direct contact with the first well region 712 and the isolation tub 718.
In the method for manufacturing the semiconductor structure, since the first well region 712 having a large depth is formed by implanting the trench 710 without using a high-energy implantation device, the vertical withstand voltage structure (isolation tub 718, second well region 714, and first well region 712) has a greater depth, and can withstand a higher voltage. And the first well region 712 with a deeper depth can increase the curvature radius of the depletion line in the semiconductor structure as an isolation structure, and reduce the electric field intensity in the body, thereby effectively improving the reliability of the device and improving the withstand voltage of the device. In addition, due to the variation of the depletion line, the size of the lateral drift region can be effectively reduced under the same device withstand voltage.
In an embodiment of the present application, step S630 is followed by a step of forming a buried region 724 of the second conductivity type. In one embodiment of the present application, after forming the first conductive type doped region 713, the photoresist layer 794 may be removed, and then the photoresist layer 796 may be formed again by photolithography, followed by implantation of second conductive type ions in the front surface of the substrate 702 to form the second conductive type doped region 723, see fig. 7e. Thus, after the heat treatment at step S640, the second conductivity-type doped region 723 is diffused to form the second conductivity-type buried region 724. In the embodiment shown in fig. 7f, the front surface of the substrate 702 is further formed with an oxide layer (not shown in fig. 7 f) during the heat treatment in step S640.
In one embodiment of the present application, step S640 is followed by a step of forming a first conductivity-type buried region 716 in the second well region 714. Referring to fig. 7g, in one embodiment of the present application, a photoresist layer 798 may be formed by photolithography, and then first conductivity-type ions are implanted into the second well region 714 to form the first conductivity-type buried region 716. A liner oxide layer (not shown in fig. 7 g) may be formed on the front side of substrate 702 prior to forming photoresist layer 798.
In one embodiment of the application, the semiconductor structure is a high voltage integrated circuit and the isolation tub is a high voltage isolation tub. In one embodiment of the present application, the step of forming the epitaxial layer 704 on the second well region 714 is further included after forming the first conductive-type buried region 716, referring to fig. 7h. Isolation tub 718 and low-voltage well region 722 may then be formed in epitaxial layer 704 by two photolithography and ion implantation. Isolation tub 718 is for high side drive circuitry to be located therein and low voltage well region 722 is for low side drive circuitry to be located therein. An insulating isolation structure 730 may then be formed at and near the interface of isolation tub 718 and low-voltage well region 722. The material of the insulating isolation structure 730 may be silicon oxide, such as silicon dioxide. Specifically, the structure may be a LOCOS (local oxidation of silicon isolation) structure or an STI (shallow trench isolation) structure.
Fig. 8 is a flow chart of a method for fabricating a semiconductor structure in an embodiment of forming an epitaxial layer on a substrate and then forming a deep trench, comprising the steps of:
S810, a wafer with a first conductivity type doped region formed thereon is obtained.
In one embodiment of the application, the first conductivity type ions are implanted in the front surface of the substrate after photoetching to form a first conductivity type doped region.
In one embodiment of the present application, the step of forming the second conductivity type doped region is further included. Specifically, the second conductive type doping region is formed by photoetching and implanting second conductive type ions into the front surface of the substrate. The second conductive type doped region is spaced apart from the first conductive type doped region.
In one embodiment of the present application, the method further comprises the step of forming a first conductivity type buried region in the first conductivity type doped region.
And S820, forming an isolation basin on the first conductive type doped region.
In one embodiment of the present application, an epitaxial layer is formed on the first conductivity type doped region (and the second conductivity type doped region), and then an isolation tub is formed in the epitaxial layer by implanting ions of the first conductivity type.
In one embodiment of the present application, the method further comprises the step of forming a low voltage well region in the epitaxial layer over the second conductivity type doped region. The low pressure well region is disposed adjacent to the isolation basin. The isolation tub is for setting a high-side driving circuit therein, and the low-voltage well region is for setting a low-side driving circuit therein.
S830, forming a plurality of grooves extending downwards from the top of the isolation basin.
In one embodiment of the present application, a plurality of trenches extending downward from the top of the isolation tub are formed by etching (the mask layer serves as an etch stop layer) after forming the mask layer, which may be a photoresist layer formed by photolithography.
S840, a first conductivity type ion implantation region is formed under each trench by ion implantation.
By using the trench as an implantation aid, a very deep depth of the first conductivity type ion implantation region can be obtained with a small implantation energy, so that expensive high-energy ion implantation equipment is not required.
S850, filling the trenches with a filler.
In one embodiment of the present application, the filler may be formed in each trench by a deposition process, and the material of the filler may be selected from a wide range of materials, such as polysilicon, silicon oxide, monocrystalline silicon, etc., and may be specifically selected in combination with factors such as manufacturing cost.
S860, heat treatment forms a first well region and a second well region.
After heat treatment (push well), the first conductive type doped region is diffused to form a second well region, the first conductive type ion implantation region is diffused to form a first well region, and the second conductive type doped region is diffused to form a second conductive type buried region.
And S870, forming an insulating isolation structure at and near the junction of the isolation basin and the low-voltage well region.
The material of the insulating isolation structure may be silicon oxide, such as silicon dioxide. Specifically, the structure may be a LOCOS (local oxidation of silicon isolation) structure or an STI (shallow trench isolation) structure.
After step S870 is completed, the HVIC structure may refer to fig. 5, which includes isolation tub 118, trench 110, first well region 112, second well region 114, first conductivity-type buried region 116, second conductivity-type buried region 124, low voltage well region 122, and insulating isolation structure 130.
It should be understood that, although the steps in the flowcharts of the present application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts of this application may include a plurality of steps or stages that are not necessarily performed at the same time but may be performed at different times, the order in which the steps or stages are performed is not necessarily sequential, and may be performed in rotation or alternately with at least a portion of the steps or stages in other steps or others.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. A semiconductor structure, comprising:
an isolation tub having a first conductivity type;
the injection auxiliary structure is a plurality of grooves filled with fillers;
A first well region of a first conductivity type extending continuously downward from the bottom of the implantation aid structure, below the isolation tub;
a second well region of the first conductivity type located below the isolation tub and above the first well region; the implantation aid structure is at least partially located in the second well region, which is in direct contact with the first well region and the isolation tub.
2. The semiconductor structure of claim 1, wherein an orthographic projection of the isolation tub on an upper surface of the first well region completely covers the first well region, and an orthographic projection of the isolation tub on an upper surface of the second well region completely covers the second well region;
the first well region is an independent region corresponding to each groove one by one, or the first well region is a large region communicated with each other below each groove, or the first well region comprises a plurality of small regions which are not communicated with each other, and each small region is positioned below at least one groove.
3. The semiconductor structure of claim 1, further comprising a buried region of a first conductivity type disposed in the second well region.
4. The semiconductor structure of claim 1, wherein the semiconductor structure is a high voltage integrated circuit, the isolation tub is a high voltage isolation tub, the high voltage integrated circuit further comprising:
The high-side driving circuit is positioned in the high-voltage area isolation basin;
A low voltage well region having a second conductivity type adjacent to the high voltage region isolation tub, the first and second conductivity types being opposite conductivity types;
and the low-side driving circuit is positioned in the low-voltage well region.
5. The semiconductor structure of claim 4, further comprising:
the insulating isolation structure is positioned at and near the junction of the high-voltage region isolation basin and the low-voltage well region;
A second conductivity type buried region located under the low voltage well region and in direct contact with the low voltage well region;
And the substrate is provided with a second conduction type, and the first well region, the second well region and the second conduction type buried region are positioned in the substrate.
6. The semiconductor structure of claim 1, wherein each of the trenches extends downward from a bottom of the isolation tub; or (b)
Each of the channels extends downwardly from the top of the isolation basin.
7. A method of fabricating a semiconductor structure, comprising:
Acquiring a wafer with a plurality of grooves formed thereon;
Forming a first conductive type ion implantation region under the plurality of trenches by ion implantation;
Filling a filler in the plurality of trenches;
performing heat treatment to diffuse the first conductive type ion implantation region to form a first well region;
the wafer also comprises a second well region positioned on the first well region and an isolation basin positioned on the second well region, wherein the second well region is formed by diffusing a first conductive type doped region in the wafer through the heat treatment step, and each groove penetrates into the second well region; the isolation basin has a first conductivity type.
8. The method of manufacturing a semiconductor structure according to claim 7, wherein the first-conductivity-type-doped region is formed by ion implantation after the step of filling the plurality of trenches with a filler, before the heat treatment step, and further comprising the step of forming an epitaxial layer on the second well region after the heat treatment diffuses the first-conductivity-type-ion-implanted region to form a first well region and the first-conductivity-type-doped region to form a second well region, and forming the isolation tub in the epitaxial layer; or (b)
In the step of obtaining a wafer with a plurality of grooves formed, isolation basins on the first conductive type doped regions and the first conductive type doped regions are formed in the obtained wafer, and each groove extends downwards from the top of each isolation basin.
9. The method of manufacturing a semiconductor structure of claim 7, wherein the semiconductor structure is a high voltage integrated circuit and the isolation tub is a high voltage isolation tub, the method further comprising:
Forming a low-voltage well region adjacent to the high-voltage region isolation basin; the low-voltage well region has a second conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types;
Forming an insulating isolation structure at and near the junction of the high-voltage region isolation basin and the low-voltage well region;
The high-voltage region isolation basin is used for arranging a high-side driving circuit therein, and the low-voltage well region is used for arranging a low-side driving circuit therein.
10. The method of manufacturing a semiconductor structure of claim 9, wherein the step of forming an insulating isolation structure is preceded by the step of:
Forming a second conductivity type buried region; the low-voltage well region is positioned on the second conductive type buried region;
a first conductivity type buried region is formed in the second well region.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211324531.7A CN117995872A (en) | 2022-10-27 | 2022-10-27 | Semiconductor structure and manufacturing method thereof |
| PCT/CN2023/098220 WO2024087634A1 (en) | 2022-10-27 | 2023-06-05 | Semiconductor structure and manufacturing method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211324531.7A CN117995872A (en) | 2022-10-27 | 2022-10-27 | Semiconductor structure and manufacturing method thereof |
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| KR102140358B1 (en) * | 2016-12-23 | 2020-08-03 | 매그나칩 반도체 유한회사 | Integrated semiconductor device having isolation structure for reducing noise |
| CN107403839B (en) * | 2017-07-25 | 2023-06-06 | 无锡新洁能股份有限公司 | Power semiconductor device structure suitable for deep trench and manufacturing method |
| CN111354677B (en) * | 2020-03-09 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Preparation method of deep trench isolation structure and semiconductor device |
| CN216624288U (en) * | 2021-12-28 | 2022-05-27 | 无锡华润华晶微电子有限公司 | Semiconductor structure |
| CN114823872B (en) * | 2022-04-26 | 2023-10-03 | 电子科技大学 | Full-isolation substrate voltage-resistant power semiconductor device and manufacturing method thereof |
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