CN117995781A

CN117995781A - Semiconductor packaging structure and packaging method

Info

Publication number: CN117995781A
Application number: CN202211349957.8A
Authority: CN
Inventors: 杨威源
Original assignee: SIPLP Microelectronics Chongqing Ltd
Current assignee: SIPLP Microelectronics Chongqing Ltd
Priority date: 2022-10-31
Filing date: 2022-10-31
Publication date: 2024-05-07

Abstract

The invention provides a semiconductor packaging structure and a packaging method, wherein an air medium is filled between a cap structure and a rewiring structure, the dielectric constant (DIELECTRIC CONSTANT) of air is 1, the loss factor (Loss Tangent) of the air is 0, and compared with a dielectric material commonly used in the prior art, the air medium has smaller dielectric constant and loss factor, so that the rewiring structure is positioned in the air medium, the semiconductor packaging structure can have lower signal delay, and the quality of the semiconductor packaging structure is improved. In addition, the interface layering problem caused by the difference of thermal expansion Coefficients (CTE) or modulus between the rewiring structure and the same-layer medium is avoided; and, can avoid the problem of metal migration, thus can avoid BHAST to test the failure, has improved the quality of the said semiconductor packaging structure.

Description

Semiconductor packaging structure and packaging method

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging structure and a packaging method.

Background

The semiconductor integrated circuit (INTEGRATED CIRCUIT; IC) industry has experienced rapid growth. Technological advances in IC fabrication have resulted in several generations of ICs, and each generation produces smaller and more complex semiconductor chips than the previous generation. The semiconductor chip needs to be packaged to form a semiconductor package structure to protect the semiconductor chip and further realize the functions of the semiconductor chip. With the development and progress of semiconductor chip structures, those skilled in the art are also required to develop packaging techniques for semiconductor chips to improve the quality of the semiconductor package structures.

Disclosure of Invention

The invention aims to provide a semiconductor packaging structure and a packaging method, which are used for improving the quality of the semiconductor packaging structure.

To this end, the present invention provides a semiconductor package structure including:

A semiconductor die;

the plastic sealing layer covers the side face of the semiconductor bare chip and exposes the bonding pad on the front face of the semiconductor bare chip;

a rewiring structure electrically connected with the bonding pad on the front surface of the semiconductor bare chip;

a cap structure that encapsulates the rewiring structure, and between which an air medium is filled; and

And the pins penetrate through the cap structure and are electrically connected with the rewiring structure.

Optionally, in the semiconductor packaging structure, the semiconductor packaging structure further includes an insulating protection layer, the insulating protection layer covers the surface of the rewiring structure, and the insulating strength of the insulating protection layer is greater than that of the air medium.

Optionally, in the semiconductor packaging structure, the material of the insulating protection layer includes polyimide.

Optionally, in the semiconductor packaging structure, the material of the cap structure includes at least one of plastic molding compound, glass, ceramic, metal and organic material.

Optionally, in the semiconductor packaging structure, a material of the cap structure includes metal, and the semiconductor packaging structure further includes: the insulation isolation layer is located between the pin and the cover cap structure, so that the pin and the cover cap structure are electrically insulated, and the heat dissipation structure is located on the cover cap structure.

Optionally, in the semiconductor package structure, the semiconductor package structure further includes an adhesion layer, the cap structure has an inner surface facing the rewiring structure, and the adhesion layer is located on the inner surface.

Optionally, in the semiconductor package structure, the semiconductor package structure further includes a support structure, and the support structure is used for supporting the rewiring structure.

The invention also provides a semiconductor packaging method, which comprises the following steps:

providing a chip unit, wherein the chip unit comprises a semiconductor bare chip, a plastic sealing layer covering the side surface of the semiconductor bare chip and a bonding pad exposing the front surface of the semiconductor bare chip;

Forming a rewiring structure on the chip unit through the photoresist layer, wherein the rewiring structure is electrically connected with a bonding pad on the front side of the semiconductor bare chip;

removing the photoresist layer to make the rewiring structure independent in an air medium;

forming a cap structure on the chip unit, wherein the cap structure covers the rewiring structure, and the air medium is filled between the cap structure and the rewiring structure;

Forming an opening in the cap structure to expose a portion of the rewiring structure; and

And forming a pin in the opening, wherein the pin is electrically connected with the rewiring structure.

Optionally, in the semiconductor packaging method, a rewiring structure is formed on the chip unit through a photoresist layer, and the electrical connection between the rewiring structure and the bonding pad on the front surface of the semiconductor die includes:

forming a first photoresist layer on the chip unit, wherein a first slot is formed in the first photoresist layer, and a part of the bonding pad is exposed out of the first slot;

Filling the first rewiring layer in the first groove, wherein the first rewiring layer is electrically connected with the bonding pad;

Forming a second photoresist layer on the first rewiring layer, wherein a second groove is formed in the second photoresist layer, and the second groove exposes part of the first rewiring layer; and

Forming a first conductive post in the second slot, the first conductive post being electrically connected to the first rewiring layer;

wherein the rewiring structure comprises the first rewiring layer and the first conductive post, and the photoresist layer comprises the first photoresist layer and the second photoresist layer.

Optionally, in the semiconductor packaging method, a rewiring structure is formed on the chip unit through a photoresist layer, and the electrical connection between the rewiring structure and the bonding pad on the front surface of the semiconductor die further includes:

forming a third photoresist layer on the second photoresist layer, wherein a third slot is formed in the third photoresist layer, and the third slot exposes the first conductive post;

filling the third slot with the second rewiring layer, wherein the second rewiring layer is electrically connected with the first conductive post;

Forming a fourth photoresist layer on the second rewiring layer, wherein a fourth groove is formed in the fourth photoresist layer, and the fourth groove exposes part of the second rewiring layer; and

Forming a second conductive post in the fourth slot, the second conductive post being electrically connected to the second rewiring layer;

Wherein the rewiring structure further comprises the second rewiring layer and the second conductive post, and the photoresist layer further comprises the third photoresist and the fourth photoresist layer.

Optionally, in the semiconductor packaging method, the second photoresist layer further has a channel therein, and the channel exposes a part of the first rewiring layer or a part of the chip unit;

a support structure is formed in the channel before forming the first conductive post in the second slot or after forming the first conductive post in the second slot or while forming the first conductive post in the second slot.

Optionally, in the semiconductor packaging method, after removing the photoresist layer to make the rewiring structure independent in an air medium, before forming a cap structure on the chip unit, the semiconductor packaging method further includes:

and forming an insulating protection layer, wherein the insulating protection layer covers the surface of the rewiring structure, and the insulating strength of the insulating protection layer is larger than that of the air medium.

Optionally, in the semiconductor packaging method, the insulating protection layer is formed by a spraying process or a spin-coating process.

Optionally, in the semiconductor packaging method, forming a cap structure on the chip unit, the cap structure covering the rewiring structure, and filling the air medium between the cap structure and the rewiring structure includes:

Providing a cap material layer, and forming a containing space in the cap material layer to form the cap structure; and

And adhering the cap structure on the chip unit, wherein the cap structure covers the rewiring structure, and the air medium is filled between the cap structure and the rewiring structure.

Optionally, in the semiconductor packaging method, providing a cap material layer, after forming a receiving space in the cap material layer to form the cap structure, forming the cap structure on the chip unit further includes: forming an adhesion layer on an inner surface of the cap structure; wherein when the cap structure is attached to the chip unit, an inner surface of the cap structure faces the rewiring structure.

Optionally, in the semiconductor packaging method, the material of the cap structure includes metal, after forming an opening in the cap structure to expose a portion of the rewiring structure, a pin is formed in the opening, and before the pin is electrically connected to the rewiring structure, the semiconductor packaging method further includes:

An insulating isolation layer is formed on the sidewalls of the opening to electrically isolate the leads from the cap structure.

Optionally, in the semiconductor packaging method, after forming the pins in the openings or while forming the pins in the openings, the semiconductor packaging method further includes:

and forming a heat dissipation structure on the cap structure.

In the semiconductor packaging structure and the packaging method provided by the invention, the air medium is filled between the cap structure and the rewiring structure, the dielectric constant (DIELECTRIC CONSTANT) of air is 1, the loss factor (Loss Tangent) of the air is 0, and compared with the dielectric material commonly used in the prior art, the air medium has smaller dielectric constant and loss factor, so that the rewiring structure is positioned in the air medium, the semiconductor packaging structure has lower signal delay, and the performance of the semiconductor packaging structure is improved.

Further, the air medium is filled between the cap structure and the rewiring structure, namely, the rewiring structure is located in the air medium, so that the problems of interface delamination and the like caused by the difference of thermal expansion Coefficients (CTE) or modulus between the rewiring structure and the same-layer medium are avoided, and the quality of the semiconductor packaging structure can be improved. Meanwhile, as the rewiring structure is positioned in an air medium, the problem of metal migration can be avoided correspondingly, so that BHAST test failure can be avoided, and the quality of the semiconductor packaging structure is improved.

Drawings

Fig. 1 to 6 are schematic views illustrating a process of forming a semiconductor package according to a first embodiment of the present invention.

Fig. 7 to 12 are schematic views illustrating a process of forming a semiconductor package structure according to a second embodiment of the present invention.

Fig. 13 is a flow chart of a semiconductor packaging method according to an embodiment of the invention.

Wherein reference numerals are as follows:

10-chip units; 100-semiconductor die; 102-bonding pads; 110-plastic sealing layer; 120-rewiring structure; 122-a first rewiring layer; 124-first conductive pillars; 126-a second rewiring layer; 128-second conductive pillars; 130-cap structure; 132-opening; 140-air medium; 150-pins; 160-an insulating protective layer; 170-a photoresist layer; 171-a first photoresist layer; 1710-first slotting; 172-a second photoresist layer; 1720-second slot; 173-a third photoresist layer; 1730-third slotting; 174-a fourth photoresist layer; 1740-fourth slotting; 180-adhesion layer.

30-Chip units; 300-semiconductor die; 302-bonding pads; 310-plastic sealing layer; 320-rewiring structure; 322-a first rewiring layer; 324-first conductive pillars; 326-a second rewiring layer; 328-second conductive pillars; 330-cap structure; 332-opening; 340-air medium; 350-pin; 360-an insulating protective layer; 370-a photoresist layer; 371-a first photoresist layer; 3710-first slotting; 372-a second photoresist layer; 3720-second slotting; 3722-channel; 373-a third photoresist layer; 3730 third slot; 374-a fourth photoresist layer; 3740-fourth slotting; 380-an adhesion layer; 390-support structure; 400-insulating isolation layer; 410-heat dissipation structure.

Detailed Description

The semiconductor packaging structure and the packaging method provided by the invention are further described in detail below with reference to the accompanying drawings and the specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise in the present document, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms first, second and the like in the description and in the claims, are not used for any order, quantity or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "upper" and/or "lower," "top" and/or "bottom" and the like are used for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

The core idea of the invention is to provide a semiconductor packaging structure and a packaging method, wherein the semiconductor packaging structure comprises: a semiconductor die; a plastic layer covering the side surface of the semiconductor bare chip; a rewiring structure electrically connected with the bonding pad on the front surface of the semiconductor bare chip; a cap structure that encapsulates the rewiring structure, and between which an air medium is filled; and a pin electrically connected with the rewiring structure through the cap structure. The air dielectric constant (DIELECTRIC CONSTANT) is 1, the loss factor (Loss Tangent) is 0, and compared with the dielectric materials commonly used in the prior art, the air dielectric constant and the loss factor are smaller, therefore, the rewiring structure is located in the air dielectric, the semiconductor packaging structure can have lower signal delay, and the quality of the semiconductor packaging structure is improved.

And the air medium is filled between the cap structure and the rewiring structure, namely the rewiring structure is positioned in the air medium, so that the problems of interface delamination and the like caused by the difference of thermal expansion Coefficients (CTE) or modulus between the rewiring structure and the same-layer medium are avoided, and the quality of the semiconductor packaging structure can be improved. Meanwhile, as the rewiring structure is positioned in an air medium, the problem of metal migration can be avoided correspondingly, so that BHAST test failure can be avoided, and the quality of the semiconductor packaging structure is improved.

Correspondingly, the invention also provides a semiconductor packaging method, please refer to fig. 13, which is a flow chart of the semiconductor packaging method according to the embodiment of the invention. The semiconductor packaging method specifically comprises the following steps:

Step S10: providing a chip unit, wherein the chip unit comprises a semiconductor bare chip, a plastic sealing layer covering the side surface of the semiconductor bare chip and a bonding pad exposing the front surface of the semiconductor bare chip;

Step S11: forming a rewiring structure on the chip unit through the photoresist layer, wherein the rewiring structure is electrically connected with a bonding pad on the front side of the semiconductor bare chip;

Step S12: removing the photoresist layer to make the rewiring structure independent in an air medium;

Step S13: forming a cap structure on the chip unit, wherein the cap structure covers the rewiring structure, and the air medium is filled between the cap structure and the rewiring structure;

step S14: forming an opening in the cap structure to expose a portion of the rewiring structure; and

Step S15: and forming a pin in the opening, wherein the pin is electrically connected with the rewiring structure.

Next, the semiconductor package structure and the packaging method according to the present application will be described in further detail with reference to the following two embodiments.

[ Embodiment one ]

Next, the semiconductor package structure and the packaging method according to the present application will be described in further detail with reference to fig. 1 to 6 and fig. 13, wherein fig. 1 to 6 are schematic views of the forming process of the semiconductor package structure according to the first embodiment of the present application, and fig. 13 is a schematic flow chart of the semiconductor package method according to the embodiment of the present application.

First, please refer to fig. 6, which illustrates a semiconductor package structure according to an embodiment of the present application. As shown in fig. 6, in an embodiment of the present application, the semiconductor structure includes: a semiconductor die 100; a plastic layer 110, wherein the plastic layer 110 covers the side surface of the semiconductor bare chip 100 and exposes the bonding pad 102 on the front surface of the semiconductor bare chip 100; a rewiring structure 120, wherein the rewiring structure 120 is electrically connected with the bonding pad 102 on the front surface of the semiconductor die 100; a cap structure 130, wherein the cap structure 130 covers the rewiring structure 120, and an air medium 140 is filled between the cap structure 130 and the rewiring structure 120; and a pin 150, wherein the pin 150 is electrically connected with the rewiring structure 120 through the cap structure 130. In the embodiment of the present application, the plastic layer 110 also covers the back surface of the semiconductor die 100; in other embodiments of the present application, the molding layer 110 may cover only the sides of the semiconductor die 100 and expose the front and back sides of the semiconductor die 100.

With continued reference to fig. 6, in an embodiment of the present application, the semiconductor package structure further includes an insulating protection layer 160, where the insulating protection layer 160 covers the surface of the rewiring structure 120, and an insulating strength (DIELECTRIC STRENGTH) of the insulating protection layer 160 is greater than an insulating strength of the air medium 140. Thus, the rewiring structure 120 can be better isolated by the insulating protective layer 160, and the occurrence of a high voltage discharge phenomenon can be prevented. Preferably, the material of the insulating protection layer 160 includes Polyimide (PI). The insulating strength of PI is between 150×10 ³V/mm～500×10³ V/mm and the insulating strength of air is about 3×10 ³ V/mm, and it can be seen that the insulating strength of PI is much greater than that of air, so that the rewiring structure 120 can be better insulated. In other embodiments of the present application, the surface of the rewiring structure 120 may not be covered with an insulating protective layer. Alternatively, the insulating protective layer 160 may be made of other materials, such as polystyrene, so long as the insulating strength of the insulating protective layer 160 is greater than that of the air medium 140, and it may further function to isolate the rewiring structure 120.

Next, the process of forming the semiconductor package will be described in further detail, with reference to fig. 1 to 6 and fig. 13.

As shown in fig. 1, in an embodiment of the present application, a chip unit 10 is provided, the chip unit 10 includes a semiconductor die 100 and a molding layer 110 covering the back and side surfaces of the semiconductor die 100 and exposing a pad 102 on the front surface of the semiconductor die 100. The front surface of the semiconductor die 100 may be covered with a passivation layer (not shown in the figure), where the passivation layer exposes the pad 102, and the front surface of the semiconductor die 100 is protected by the passivation layer.

Next, as shown in fig. 2, a rewiring structure 120 is formed on the chip unit 10 through the photoresist layer 170, and the rewiring structure 120 is electrically connected to the bonding pad 102 on the front surface of the semiconductor die 100. In the embodiment of the present application, the rewiring structure 120 is a multi-layer structure, and specifically includes a first rewiring layer 122, a first conductive pillar 124 electrically connected to the first rewiring layer 122, a second rewiring layer 126 electrically connected to the first conductive pillar 124, and a second conductive pillar 128 electrically connected to the second rewiring layer 126. The photoresist layer 170 includes a first photoresist layer 171, a second photoresist layer 172 on the first photoresist layer 171, a third photoresist layer 173 on the second photoresist layer 172, and a fourth photoresist layer 174 on the third photoresist layer 173.

With continued reference to fig. 2, specifically, a first photoresist layer 171 may be formed on the chip unit 10, where the first photoresist layer 171 has a first slot 1710 therein, and the first slot 1710 exposes a portion of the pad 102. Next, the first rewiring layer 122 is filled in the first trench 1710, and the first rewiring layer 122 is electrically connected to the pad 102. Wherein, before forming the first photoresist layer 171, a first copper seed layer (not shown) may be formed on the chip unit 10, and the first photoresist layer 171 covers the first copper seed layer. The formation of the first rewiring layer 122 may be facilitated by the first copper seed layer.

Next, a second photoresist layer 172 is formed over the first rewiring layer 122, the second photoresist layer 172 having a second trench 1720 therein, the second trench 1720 exposing a portion of the first rewiring layer 122. Next, a first conductive pillar 124 is formed in the second trench 1720, and the first conductive pillar 124 is electrically connected to the first rewiring layer 122.

In the embodiment of the present application, the second rewiring layer 126 and the second conductive pillars 128 are further formed, that is, a two-layer rewiring layer structure is formed, and in other embodiments of the present application, only one layer of rewiring layer structure may be formed.

With continued reference to fig. 2, a third photoresist layer 173 is formed on the second photoresist layer 172, wherein the third photoresist layer 173 has a third trench 1730 therein, and the third trench 1730 exposes the first conductive pillar 124. Next, the third trench 1730 is filled with the second rewiring layer 126, and the second rewiring layer 126 is electrically connected to the first conductive pillar 124. A second copper seed layer (not shown) may be formed on the second photoresist layer 172 before the third photoresist layer 173 is formed, and the third photoresist layer 173 covers the second copper seed layer, through which the second rewiring layer 126 may be formed.

A fourth photoresist layer 174 is formed over the second rewiring layer 126, the fourth photoresist layer 174 having a fourth trench 1740 therein, the fourth trench 1740 exposing a portion of the second rewiring layer 126. Next, a second conductive pillar 128 is formed in the fourth trench 1740, the second conductive pillar 128 being electrically connected to the second rewiring layer 126.

In an embodiment of the present application, after the second conductive pillars 128 are formed, a polishing process is performed on the surface of the device to obtain a planarized device surface. That is, a polishing process is performed on the second conductive pillars 128 and the fourth photoresist layer 174 to planarize a plane formed by the second conductive pillars 128 and the fourth photoresist layer 174 together. In other embodiments of the present application, a polishing process may be performed to planarize the device surface after each layer of the conductive structure of the re-wiring structure 120 is formed, i.e., after each layer of the re-wiring layer or each layer of the conductive pillars is formed, which is not limited in this application.

Referring to fig. 3, in an embodiment of the present application, the photoresist layer 170 and the exposed copper seed layer (including the first copper seed layer and the second copper seed layer) are then removed so that the rewiring structure 120 is independent of the air-dielectric 140. That is, after the photoresist layer 170 is removed, the sidewall of the rewiring structure 120 is connected to air and placed in the air medium 140. In the embodiment of the present application, air is used as the dielectric layer for isolating the rewiring structure 120, the dielectric constant (DIELECTRIC CONSTANT) of air is 1, the loss factor (Loss Tangent) of air is 0, and compared with the dielectric material commonly used in the prior art, the air dielectric has smaller dielectric constant and loss factor, so that the rewiring structure is located in the air dielectric, and the formed semiconductor packaging structure has lower signal delay, so that the quality of the semiconductor packaging structure is improved. Because the air medium 140 is in a gaseous form, the problem of interfacial delamination between the rewiring structure 120 and the same layer medium due to differences in Coefficient of Thermal Expansion (CTE) or modulus can be avoided, and the quality of the formed semiconductor package structure can be improved.

Referring to fig. 4, in the embodiment of the present application, an insulating protection layer 160 is formed, the insulating protection layer 160 covers the surface of the re-wiring structure 120, and the insulating protection layer 160 has an insulating strength greater than that of the air medium 140. Specifically, the insulating protection layer 160 may be formed through a spray process or a spin coating process. Here, a thin insulating protective layer 160 is formed to be attached to the surface of the re-wiring structure 120. Thus, the rewiring structure 120 can be better isolated by the insulating protective layer 160, and the occurrence of a high voltage discharge phenomenon can be prevented. Preferably, the material of the insulating protection layer 160 includes Polyimide (PI).

Next, as shown in fig. 5, a cap structure 130 is formed on the chip unit 10, the cap structure 130 covers the rewiring structure 120, and the space between the cap structure 130 and the rewiring structure 120 is filled with the air medium 140. The material of the cap structure 130 may include at least one of plastic molding compound, glass, ceramic, metal, and organic material.

In an embodiment of the present application, a cap material layer (not shown) is provided, and then a receiving space (not shown) is formed in the cap material layer by using a stamping die, so as to form the cap structure 130. In which a non-penetrating receiving space (not shown) is formed in the cap material layer, i.e. in this case, the cap structure 130 comprises a top wall (in the opposite sense, also referred to as bottom wall) and a side wall connected to the top wall.

Preferably, after the cap structure 130 is formed, an adhesion layer 180 is formed on the inner surface of the cap structure 130, and the reliability of the subsequent connection of the cap structure 130 to the chip unit 10 may be improved by the adhesion layer 180, thereby improving the quality and reliability of the formed semiconductor package structure. The adhesion layer 180 may be formed on the inner surface of the cap structure 130 by spraying or dispensing.

Next, the cap structure 130 is attached to the chip unit 10, the cap structure 130 covers the rewiring structure 120, and the space between the cap structure 130 and the rewiring structure 120 is filled with the air medium 140. When the cap structure 130 is adhered to the chip unit 10, the inner surface of the cap structure 130 faces the rewiring structure 120, and the rewiring structure 120 is located in the accommodating space of the cap structure 130.

In the embodiment of the present application, it is preferable that the adhesion layer 180 is connected to the top surface of the re-wiring structure 120, so that the re-wiring structure 120 and the cap structure 130 may be supported by each other to improve the quality and reliability of the formed semiconductor package structure. In other embodiments of the present application, the adhesion layer 180 or the cap structure 130 (without an adhesion layer) may also have a gap with the rewiring structure 120, i.e., the top surface of the rewiring structure 120 may also be exposed to the air medium 140.

Next, referring to fig. 6, an opening 132 is formed in the cap structure 130 to expose a portion of the rewiring structure 120. Specifically, the openings 132 may be formed through the cap structure 130 in the cap structure 130 by a laser process.

Then, a pin 150 is formed in the opening 132, and the pin 150 is electrically connected to the rewiring structure 120. Here, the pins 150 also extend over a portion of the surface of the cap structure 130. Preferably, the surface of the pin 150 is a solder layer, so that the formed semiconductor package structure is connected with the PCB and other structures.

In summary, in the semiconductor packaging structure and the packaging method provided in this embodiment, the air medium is filled between the cap structure and the rewiring structure, so that the semiconductor packaging structure has lower signal delay, and the quality of the semiconductor packaging structure is improved. In addition, the interface layering problem caused by the difference of thermal expansion Coefficients (CTE) or modulus between the rewiring structure and the same-layer medium is avoided; and, can avoid the problem of metal migration, thus can avoid BHAST to test the failure, has improved the quality of the said semiconductor packaging structure.

[ Example two ]

Next, the semiconductor package structure and the packaging method according to the present application will be described in further detail with reference to fig. 7 to 12 and fig. 13, wherein fig. 7 to 12 are schematic views of the forming process of the semiconductor package structure according to the second embodiment of the present application, and fig. 13 is a schematic flow chart of the semiconductor package method according to the embodiment of the present application.

First, please refer to fig. 12, which illustrates a semiconductor package structure according to an embodiment of the present application. As shown in fig. 12, in an embodiment of the present application, the semiconductor structure includes: a semiconductor die 300; a plastic layer 310, wherein the plastic layer 310 covers the side surface of the semiconductor bare chip 300 and exposes the bonding pad 302 on the front surface of the semiconductor bare chip 300; a rewiring structure 320, wherein the rewiring structure 320 is electrically connected with the bonding pad 302 on the front surface of the semiconductor die 300; a cap structure 330, wherein the cap structure 330 covers the rewiring structure 320, and an air medium 340 is filled between the cap structure 330 and the rewiring structure 320; and, a pin 350, wherein the pin 350 passes through the cap structure 330 and is electrically connected with the rewiring structure 320. In the embodiment of the present application, the plastic layer 310 further covers the back surface of the semiconductor die 300; in other embodiments of the present application, the molding layer 310 may cover only the sides of the semiconductor die 300 to expose the front and back sides of the semiconductor die 300.

In an embodiment of the present application, the semiconductor package structure further includes an insulating protection layer 360, the insulating protection layer 360 covers the surface of the rewiring structure 320, and an insulating strength (DIELECTRIC STRENGTH) of the insulating protection layer 360 is greater than an insulating strength of the air medium 340. Thus, the rewiring structure 320 can be better isolated by the insulating protection layer 360, and the high voltage discharge phenomenon can be prevented. Preferably, the material of the insulating protection layer 360 includes Polyimide (PI). The insulating strength of PI is between 150×10 ³V/mm～500×10³ V/mm and the insulating strength of air is about 3×10 ³ V/mm, and it can be seen that the insulating strength of PI is much greater than that of air, so that the rewiring structure 320 can be better insulated. In other embodiments of the present application, the surface of the rewiring structure 320 may not be covered with an insulating protective layer. Alternatively, the insulating protection layer 360 may be made of other materials, such as polystyrene, so long as the insulating strength of the insulating protection layer 360 is greater than that of the air medium 340, and the insulating protection layer may further function as an insulation rewiring structure 320.

In an embodiment of the present application, the semiconductor package structure further includes a support structure 390, where the support structure 390 is used to support the rewiring structure 320. With continued reference to fig. 12, in an embodiment of the present application, the rewiring structure 320 includes a first rewiring layer 322, a first conductive pillar 324 electrically connected to the first rewiring layer 322, a second rewiring layer 326 electrically connected to the first conductive pillar 324, and a second conductive pillar 328 electrically connected to the second rewiring layer 326. Here, one end of the support structure 390 is connected to the second rewiring layer 326, and the other end of the support structure 390 may be disposed on the first rewiring layer 322, on the semiconductor die 300, or on the plastic sealing layer 310. Preferably, the material of the support structure 390 is the same as that of the rewiring structure 320, more specifically, the material of the support structure 390 is the same as that of the first conductive pillar 324, and the support structure 390 and the first conductive pillar 324 are formed simultaneously, so that the manufacturing process of the semiconductor package structure can be simplified. In other embodiments of the present application, the material of the support structure 390 may be different from the material of the rewiring structure 320, for example, the material of the support structure 390 may be a dielectric material.

In the embodiment of the present application, the material of the cap structure 330 includes metal, so as to facilitate heat dissipation of the semiconductor package structure. Further, the semiconductor package structure further includes a heat dissipation structure 400, and the heat dissipation structure 400 is located on the cap structure 330, so that heat dissipation of the semiconductor package structure can be further improved.

Next, the process of forming the semiconductor package will be described in further detail, with reference to fig. 7 to 12 and fig. 13.

As shown in fig. 7, in an embodiment of the present application, a chip unit 30 is provided, the chip unit 30 includes a semiconductor die 300 and a molding layer 310 covering the back and side surfaces of the semiconductor die 300 and exposing a pad 302 on the front surface of the semiconductor die 300. The front surface of the semiconductor die 300 may be covered with a passivation layer (not shown in the figure), where the passivation layer exposes the bonding pad 302, and the front surface of the semiconductor die 300 is protected by the passivation layer.

Next, as shown in fig. 8, a rewiring structure 320 is formed on the chip unit 30 through a photoresist layer 370, and the rewiring structure 320 is electrically connected to the bonding pad 302 on the front surface of the semiconductor die 300. In the embodiment of the present application, the rewiring structure 320 is a multi-layer structure, and specifically includes a first rewiring layer 322, a first conductive pillar 324 electrically connected to the first rewiring layer 322, a second rewiring layer 326 electrically connected to the first conductive pillar 324, and a second conductive pillar 328 electrically connected to the second rewiring layer 326. The photoresist layer 370 includes a first photoresist layer 371, a second photoresist layer 372 on the first photoresist layer 371, a third photoresist layer 373 on the second photoresist layer 372, and a fourth photoresist layer 374 on the third photoresist layer 373.

Specifically, a first photoresist layer 371 may be formed on the chip unit 30, where the first photoresist layer 371 has a first slot 3710 therein, and the first slot 3710 exposes a portion of the pad 302. Next, the first rewiring layer 322 is filled in the first trench 3710, and the first rewiring layer 322 is electrically connected to the pad 302. A first copper seed layer (not shown) may be formed on the chip unit 30 before the first photoresist layer 371 is formed, and the first photoresist layer 371 covers the first copper seed layer. The formation of the first rewiring layer 322 may be facilitated by the first copper seed layer.

Next, a second photoresist layer 372 is formed on the first rewiring layer 322, the second photoresist layer 372 having a second trench 3720 therein, the second trench 3720 exposing a portion of the first rewiring layer 322. In the embodiment of the present application, the second photoresist layer 372 further has a channel 3722 therein, and the channel 3722 exposes a portion of the first rewiring layer 322 or a portion of the chip unit 10.

Next, a first conductive pillar 324 is formed in the second trench 3720, and the first conductive pillar 324 is electrically connected to the first rewiring layer 322. In an embodiment of the present application, a support structure 390 is also formed in the channel 3722.

In other embodiments of the application, the channel 3722 and the second slot 3720 may be formed in steps, and the support structure 390 and the first conductive post 324 may be formed in steps. Wherein the channel 3722 may be formed before the second slot 3720, or may be formed after the second slot 3720; the support structure 390 may be formed before the first conductive post 324 or after the first conductive post 324.

In the embodiment of the present application, a third photoresist layer 373 is formed on the second photoresist layer 372, wherein the third photoresist layer 373 has a third trench 3730 therein, and the third trench 3730 exposes the first conductive post 324 and the support structure 390. Next, the third trench 3730 is filled with the second rewiring layer 326, the second rewiring layer 326 is electrically connected to the first conductive pillar 324, and the second rewiring layer 326 is also connected to the support structure 390. A second copper seed layer (not shown) may be formed on the second photoresist layer 372 before the third photoresist layer 373 is formed, and the third photoresist layer 373 covers the second copper seed layer, by which the formation of the second rewiring layer 326 may be facilitated.

A fourth photoresist layer 374 is formed on the second rewiring layer 326, the fourth photoresist layer 374 having a fourth trench 3740 therein, the fourth trench 3740 exposing a portion of the second rewiring layer 326. Next, a second conductive pillar 328 is formed in the fourth trench 3740, and the second conductive pillar 328 is electrically connected to the second rewiring layer 326.

In an embodiment of the present application, after the second conductive post 328 is formed, a polishing process is performed on the surface of the device to obtain a planarized device surface. That is, a polishing process is performed on the second conductive pillars 328 and the fourth photoresist layer 374 to planarize a plane formed by the second conductive pillars 328 and the fourth photoresist layer 374 together. In other embodiments of the present application, a polishing process may be performed to planarize the device surface after each layer of the conductive structure of the re-wiring structure 320 is formed, i.e., after each layer of the re-wiring layer or each layer of the conductive pillars is formed, which is not limited in this application.

Referring to fig. 9, in an embodiment of the present application, the photoresist layer 370 is then removed to make the rewiring structure 320 independent of the air medium 340. That is, after the photoresist layer 370 is removed, the sidewall of the rewiring structure 320 is exposed to air and is located in the air medium 340. In the embodiment of the present application, air is used as the dielectric layer for isolating the rewiring structure 320, the dielectric constant (DIELECTRIC CONSTANT) of air is 1, the loss factor (Loss Tangent) of air is 0, and compared with the dielectric material commonly used in the prior art, the air dielectric has smaller dielectric constant and loss factor, so that the rewiring structure is located in the air dielectric, and the formed semiconductor packaging structure has lower signal delay, so that the quality of the semiconductor packaging structure is improved. Because the air medium 340 is in a gaseous form, the problem of interfacial delamination between the rewiring structure 320 and the same layer medium due to a difference in Coefficient of Thermal Expansion (CTE) or a difference in modulus can be avoided, and the quality of the formed semiconductor package structure can be improved.

Referring to fig. 10, in the embodiment of the present application, an insulating protection layer 360 is formed, the insulating protection layer 360 covers the surface of the re-wiring structure 320, and the insulating strength of the insulating protection layer 360 is greater than the insulating strength of the air medium 340. Wherein the insulating protective layer 360 also covers the surface of the support structure 390. Specifically, the insulating protection layer 360 may be formed through a spray process or a spin coating process. Here, a thin insulating protective layer 360 is formed to be attached to the surface of the re-wiring structure 320. Thus, the rewiring structure 320 can be better isolated by the insulating protection layer 360, and the high voltage discharge phenomenon can be prevented. Preferably, the material of the insulating protection layer 360 includes Polyimide (PI).

Next, as shown in fig. 11, a cap structure 330 is formed on the chip unit 30, the cap structure 330 covers the rewiring structure 320, and the space between the cap structure 330 and the rewiring structure 320 is filled with the air medium 340. In the embodiment of the present application, the cap structure 330 is made of metal, so that heat dissipation of the formed semiconductor package structure can be improved.

Specifically, a cap material layer (not shown) is provided, and then a receiving space (not shown) may be formed in the cap material layer by using a stamping die, so as to form the cap structure 330.

In the embodiment of the present application, after the cap structure 330 is formed, an adhesion layer 380 is formed on the inner surface of the cap structure 330, and the adhesion layer 380 can improve the connection reliability of the cap structure 330 on the chip unit 30, thereby improving the quality and reliability of the formed semiconductor package structure. The adhesive layer 380 may be formed on the inner surface of the cap structure 330 by spraying or dispensing.

Next, the cap structure 330 is attached to the chip unit 30, the cap structure 330 covers the rewiring structure 320, and the space between the cap structure 330 and the rewiring structure 320 is filled with the air medium 340. Wherein the inner surface of the cap structure 330 faces the rewiring structure 320 when the cap structure 330 is attached to the chip unit 30.

Preferably, the adhesion layer 380 is connected to the top surface of the re-wiring structure 320, so that the re-wiring structure 320 and the cap structure 330 can be supported by each other to improve the quality and reliability of the formed semiconductor package structure.

Next, referring to fig. 12, an opening 332 is formed in the cap structure 330 to expose a portion of the rewiring structure 320. Specifically, the openings 332 may be formed through the cap structure 330 in the cap structure 330 by a laser process.

In the embodiment of the present application, the cap structure 330 is made of metal, and after the opening 332 is formed, an insulating isolation layer 400 is formed on the sidewall of the opening 332. Next, a pin 350 is formed in the opening 332, and the pin 350 is electrically connected to the rewiring structure 320. The insulating spacer 400 is positioned between the pins 350 and the sidewalls of the openings 332 to electrically insulate the pins 350 from the cap structure 330. Here, the lead 350 also extends to cover a part of the surface of the cap structure 330, and accordingly, the insulating isolation layer 400 also extends to cover a part of the surface of the cap structure 330 to be located between the lead 350 and the cap structure 330, so that the lead 350 and the cap structure 330 are electrically insulated. Preferably, the surface of the pin 350 is a solder layer, so that the formed semiconductor package structure is connected with the PCB board or other structure.

In an embodiment of the present application, the surface of the rewiring structure 320 is covered with an insulating protection layer 360, and the cap structure 330 is electrically insulated from the rewiring structure 320 by the insulating protection layer 360. Wherein the opening 332 further penetrates the insulating protection layer 360 to expose a portion of the rewiring structure 320, so that the pin 350 can be electrically connected to the rewiring structure 320. Here, an adhesive layer 380 is formed on the inner surface of the cap structure 330, which also serves to isolate the cap structure 330 from the rewiring structure 320. Accordingly, the openings 332 also extend through the adhesion layer 380, i.e., in an embodiment of the present application, the pins 350 are electrically connected to the rewiring structure 320 through the cap structure 330, the adhesion layer 380, and the insulating protection layer 360.

In other embodiments of the present application, the surface of the rewiring structure 320 may not be covered with an insulating protective layer, and the cap structure 330 and the rewiring structure 320 may be isolated by the adhesive layer 380. Further, an insulating layer may also be formed on the surface of the rewiring structure 320 closest to the cap structure 330, here the top surface of the second conductive post 328, before the cap structure 330 is attached to the chip unit 30, so as to better isolate the cap structure 330 from the rewiring structure 320.

In the embodiment of the present application, the heat dissipation structure 410 is further formed on the cap structure 330 while the leads 350 are formed, so that the heat dissipation of the formed semiconductor package structure can be further improved. Also, the surface of the heat dissipation structure 410 is a solder layer, so that the formed semiconductor package structure is connected with the PCB board and other structures. In other embodiments of the present application, the heat dissipation structure 410 may also be formed after the pins 350, wherein the heat dissipation structure 410 is made of metal.

Claims

1. A semiconductor package structure, the semiconductor package structure comprising:

A semiconductor die;

2. The semiconductor package structure of claim 1, further comprising an insulating protective layer covering a surface of the rewiring structure, the insulating protective layer having an insulating strength greater than an insulating strength of the air medium.

3. The semiconductor package according to claim 2, wherein the insulating protective layer comprises polyimide.

4. The semiconductor package according to any one of claims 1 to 3, wherein the cap structure comprises at least one of a plastic compound, glass, ceramic, metal, and an organic material.

5. The semiconductor package according to any one of claims 1 to 3, wherein the cap structure comprises a metal, and the semiconductor package further comprises: the insulation isolation layer is located between the pin and the cover cap structure, so that the pin and the cover cap structure are electrically insulated, and the heat dissipation structure is located on the cover cap structure.

6. The semiconductor package according to any one of claims 1 to 3, further comprising an adhesive layer, the cap structure having an inner surface facing the rewiring structure, the adhesive layer being located on the inner surface.

7. The semiconductor package according to any one of claims 1 to 3, further comprising a support structure for supporting the rewiring structure.

8. A semiconductor packaging method, characterized in that the semiconductor packaging method comprises:

9. The semiconductor package method of claim 8, wherein forming a rewiring structure on the chip unit through a photoresist layer, the rewiring structure electrically connected to a pad on the front side of the semiconductor die comprises:

10. The semiconductor package method of claim 9, wherein forming a rewiring structure on the chip unit through a photoresist layer, the rewiring structure electrically connected to a pad on the front side of the semiconductor die further comprises:

11. The semiconductor packaging method of claim 9, wherein the second photoresist layer further has a via therein exposing a portion of the first rewiring layer or a portion of the chip unit;

12. The semiconductor packaging method according to any one of claims 8 to 11, wherein after removing the photoresist layer so that the rewiring structure is independent in an air medium, before forming a cap structure on the chip unit, the semiconductor packaging method further comprises:

13. The semiconductor packaging method according to any one of claims 8 to 11, wherein a cap structure is formed on the chip unit, the cap structure covers the rewiring structure, and filling the space between the cap structure and the rewiring structure with the air medium includes:

14. The semiconductor package method of claim 13, wherein providing a layer of cap material, after forming a receiving space in the layer of cap material to form the cap structure, forming a cap structure on the chip unit further comprises: forming an adhesion layer on an inner surface of the cap structure; wherein when the cap structure is attached to the chip unit, an inner surface of the cap structure faces the rewiring structure.

15. The semiconductor packaging method according to any one of claims 8 to 11, wherein a material of the cap structure includes a metal, and after forming an opening in the cap structure to expose a portion of the rewiring structure, a pin is formed in the opening, and before the pin is electrically connected to the rewiring structure, the semiconductor packaging method further comprises:

16. The semiconductor packaging method according to claim 15, wherein after forming a pin in the opening or while forming a pin in the opening, the semiconductor packaging method further comprises:

and forming a heat dissipation structure on the cap structure.