CN117976705A - 高电子迁移率晶体管及其制作方法 - Google Patents

高电子迁移率晶体管及其制作方法 Download PDF

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CN117976705A
CN117976705A CN202410020225.7A CN202410020225A CN117976705A CN 117976705 A CN117976705 A CN 117976705A CN 202410020225 A CN202410020225 A CN 202410020225A CN 117976705 A CN117976705 A CN 117976705A
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hard mask
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李凯霖
李志成
陈威任
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United Microelectronics Corp
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Abstract

本发明公开一种高电子迁移率晶体管及其制作方法，其中该制作高电子迁移率晶体管(high electron mobility transistor,HEMT)的方法为，首先形成一缓冲层于一基底上，然后形成一阻障层于该缓冲层上，形成一硬掩模于该阻障层上，去除该硬掩模以形成一凹槽暴露出该阻障层，去除该凹槽旁的该硬掩模以形成一第二凹槽，再形成一P型半导体层于该第一凹槽以及该第二凹槽内。

Description

高电子迁移率晶体管及其制作方法
本申请是中国发明专利申请(申请号：201911044101.8，申请日：2019年10月30日，发明名称：高电子迁移率晶体管及其制作方法)的分案申请。
技术领域
本发明涉及一种高电子迁移率晶体管及其制作方法。
背景技术
以氮化镓基材料(GaN-based materials)为基础的高电子迁移率晶体管具有于电子、机械以及化学等特性上的众多优点，例如宽带隙、高击穿电压、高电子迁移率、大弹性模数(elasticmodulus)、高压电与压阻系数(high piezoelectric and piezoresistivecoefficients)等与化学钝性。上述优点使氮化镓基材料可用于如高亮度发光二极管、功率开关元件、调节器、电池保护器、面板显示驱动器、通讯元件等应用的元件的制作。
发明内容
本发明一实施例揭露一种制作高电子迁移率晶体管(high electron mobilitytransistor,HEMT)的方法。首先形成一缓冲层于一基底上，然后形成一阻障层于该缓冲层上，形成一硬掩模于该阻障层上，去除该硬掩模以形成一凹槽暴露出该阻障层，去除该凹槽旁的该硬掩模以形成一第二凹槽，再形成一P型半导体层于该第一凹槽以及该第二凹槽内。
本发明另一实施例揭露一种高电子迁移率晶体管，其主要包含一缓冲层设于一基底上、一阻障层设于该缓冲层上、一P型半导体层设于该阻障层上且该P型半导体层包含L形、一栅极电极设于该P型半导体层上以及一源极电极以及一漏极电极设于该栅极电极两侧的该缓冲层上。
本发明又一实施例揭露一种高电子迁移率晶体管，其主要包含一缓冲层设于一基底上、一阻障层设于该缓冲层上、一P型半导体层设于该阻障层上且P型半导体层包含T形、一栅极电极设于该P型半导体层上以及一源极电极以及一漏极电极设于该栅极电极两侧的该缓冲层上。
附图说明
图1至图5为本发明一实施例制作一高电子迁移率晶体管的方法示意图；
图6至图7为本发明一实施例制作一高电子迁移率晶体管的方法示意图。
主要元件符号说明
12 基底 14 缓冲层
16 阻障层 18 MESA区域
20 硬掩模 22 凹槽
24 凹槽 26 凹槽
28 源极电极 30 漏极电极
32 凹槽 34 P型半导体层
36 栅极材料层 38 栅极结构
40 栅极电极 42 场极板
44 第一部分 46 第二部分
48 凹槽 50 第三部分
具体实施方式
请参照图1至图5，图1至图5为本发明一实施例制作一高电子迁移率晶体管的方法示意图。如图1所示，首先提供一基底12，例如一由硅、碳化硅或氧化铝(或可称蓝宝石)所构成的基底，其中基底12可为单层基底、多层基底、梯度基底或上述的组合。依据本发明其他实施例基底12又可包含一硅覆绝缘(silicon-on-insulator,SOI)基底。
然后于基底12表面形成一缓冲层14。在一实施例中，缓冲层14包含III-V族半导体例如氮化镓，其厚度可介于0.5微米至10微米之间。在一实施例中，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemicalvapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于基底12上形成缓冲层14。
接着形成一阻障层16于缓冲层14表面。在本实施例中阻障层16较佳包含III-V族半导体例如氮化铝镓(AlxGa1-xN)，其中0<x<1，x较佳小于等于20％，且阻障层16较佳包含一由外延成长制作工艺所形成的外延层。如同上述形成缓冲层14的方式，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemicalvapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于缓冲层14上形成阻障层16。需注意的是，本实施例中阻障层16虽直接设置于缓冲层14表面，但依据本发明另一实施例又可选择于缓冲层14与阻障层16之间额外形成一金属氮化层(图未示)包含例如但不局限于氮化铝，此变化型也属本发明所涵盖的范围。
随后进行一平台隔离(MESA isolation)制作工艺定义出MESA区域18与主动区域，使元件之间可独立运作而不致受到彼此交互影响。在本实施例中，平台隔离制作工艺可利用一光刻暨蚀刻制作工艺图案化或以蚀刻去除部分阻障层16以及部分缓冲层14，其中被图案化的阻障层16以及缓冲层14较佳具有相同宽度且两者之间的边缘较佳相互切齐，而剩余且未被图案化的部分缓冲层14则与基底12包含相同宽度。
接着图2所示，形成一硬掩模20于阻障层16及缓冲层14表面，再进行一道或一道以上光刻暨蚀刻制作工艺去除部分硬掩模20以及部分阻障层16以形成多个凹槽22、24、26，其中设于中央的凹槽24底部较佳暴露出阻障层16且凹槽24较佳于后续制作工艺中用来形成栅极电极，设于两侧的凹槽22、26则暴露出缓冲层14并较佳用来形成源极电极以及漏极电极。需注意的是，除了上述图案化方式，依据本发明另一实施例又可于形成硬掩模20之前先进行一道光刻暨蚀刻制作工艺去除部分阻障层16形成凹槽22、26，覆盖硬掩模20于阻障层16上，再进行另一道光刻暨蚀刻制作工艺去除部分硬掩模20形成22、24、26，此变化型也属本发明所涵盖的范围。在本实施例中，硬掩模20较佳包含氮化硅且其厚度约略5纳米，但不局限于此。
如图3所示，然后形成源极电极28与漏极电极30于两侧的凹槽22、26内，其中源极电极28与漏极电极30较佳由欧姆接触金属所构成。依据本发明一实施例，源极电极28与漏极电极30可各自包含钛、铝、钨、钯或其组合。在一些实施例中，可先以光刻暨蚀刻制作工艺去除凹槽24两侧的部分硬掩模20及部分阻障层16形成凹槽22、26，利用电镀制作工艺、溅镀制作工艺、电阻加热蒸镀制作工艺、电子束蒸镀制作工艺、物理气相沉积(physical vapordeposition,PVD)制作工艺、化学气相沉积制作工艺(chemical vapor deposition,CVD)制作工艺、或上述组合于凹槽22、26内形成电极材料，然后再以蚀刻将电极材料图案化以形成源极电极28与漏极电极30。
接着如图4所示，进行另一光刻暨蚀刻制作工艺去除凹槽24旁的部分硬掩模20以形成另一凹槽32于凹槽24旁，其中凹槽32深度较佳小于先前所形成的凹槽24深度。更具体而言，相较于凹槽24底部暴露出阻障层16，凹槽32底部较佳暴露出蚀刻后剩余的硬掩模20，凹槽24底部低于凹槽32底部且凹槽24较佳直接连接凹槽32。
如图5所示，依序形成一P型半导体层34以及一栅极材料层36于阻障层16及硬掩模20表面并填入凹槽24、32内，再利用光刻暨蚀刻制作工艺去除部分栅极材料层36以形成一栅极结构38于阻障层16及硬掩模20上，其中栅极结构38较佳于图案化后包含一栅极电极40以及场极板(field plate)42设于栅极电极40一侧。更具体而言，设于之前凹槽24内的栅极材料层36较佳构成栅极电极40，而设于栅极电极40一侧硬掩模20正上方或凹槽32内的栅极材料层36则作为场极板42，其中栅极电极40较佳用来作为开启与关闭通道区的开关，而场极板42则负责将电场向上牵引并平衡与分散被牵引的大电流，进而提升元件可承受的最大电压。在本实施中，P型半导体层34较佳包含P型氮化镓(pGaN)，而栅极材料层36则较佳包含金属，例如可包含金、银或铂等萧特基(Schottky)金属。至此即完成本发明一实施例的高电子迁移率晶体管的制作。
请再参照图5，图5又揭露本发明一实施例的一高电子迁移率晶体管的结构示意图。如图5所示，高电子迁移率晶体管主要包含缓冲层14设于基底12上，阻障层16设于缓冲层14上，P型半导体层34设于阻障层16上，栅极电极40设于P型半导体层34上，硬掩模20设于阻障层16上并环绕P型半导体层34及栅极电极40且设于部分P型半导体层34下方，场极板42设于栅极电极40一侧的硬掩模20上以及源极电极28与漏极电极30设于栅极电极40两侧的缓冲层14上。
在本实施例中，P型半导体层34较佳包含一第一部分44设于阻障层16上以及一第二部分46设于硬掩模20上，其中第一部分44直接连接第二部分46且两者的组合较佳一同构成一L形，第一部分44顶部切齐第二部分46顶部且两者的顶部均低于硬掩模20顶部，第一部分44底部低于第二部分46底部，第二部分46厚度小于第一部分44厚度，以及第一部分44与第二部分46包含相同材料。
请再参照图6至图7，图6至图7为本发明一实施例制作一高电子迁移率晶体管的方法示意图。如图6所示，本发明可于进行图4的光刻暨蚀刻制作工艺时同时去除凹槽24两侧的部分硬掩模20形成凹槽32及凹槽48，其中凹槽32、48深度均较佳小于凹槽24深度，且所形成的三个凹槽24、32、48一同构成一约略T形的凹槽。更具体而言，相较于凹槽24底部暴露出阻障层16，凹槽32及凹槽48底部均暴露出硬掩模20，凹槽24底部低于凹槽32、48底部且凹槽24均直接连接凹槽32、48。需注意的是，本实施例的凹槽32宽度虽不同于凹槽48宽度，但依据本发明一实施例，凹槽32与凹槽48的宽度均可依据制作工艺需求调整，例如凹槽48宽度小于凹槽32宽度，凹槽48宽度大于凹槽32宽度，或凹槽48宽度等于凹槽32宽度，这些变化形均属本发明所涵盖的范围。
然后如图7所示，比照图5的制作工艺依序形成一P型半导体层34以及一栅极材料层36于阻障层16及硬掩模20表面并填入凹槽24、32、48内，再利用光刻暨蚀刻制作工艺去除部分栅极材料层36以形成一栅极结构38于阻障层16及硬掩模20上，其中栅极结构38较佳于图案化后包含一栅极电极40以及场极板(field plate)42设于栅极电极40两侧。至此即完成本发明一实施例的高电子迁移率晶体管的制作。
请再参照图7，图7又揭露本发明一实施例的一高电子迁移率晶体管的结构示意图。如图7所示，高电子迁移率晶体管主要包含缓冲层14设于基底12上，阻障层16设于缓冲层14上，P型半导体层34设于阻障层16上，栅极电极40设于P型半导体层34上，硬掩模20设于阻障层16上并环绕P型半导体层34及栅极电极40且设于部分P型半导体层34下方，场极板42设于栅极电极40两侧的硬掩模20上以及源极电极28与漏极电极30设于栅极电极40两侧的缓冲层14上。
在本实施例中，P型半导体层34较佳包含第一部分44设于阻障层16上、第二部分46设于第一部分44一侧的硬掩模20上以及第三部分50设于第一部分44另一侧的硬掩模20上，其中第一部分44直接连接第二部分46与第三部分50且三者的一同构成一T形，第一部分44顶部切齐第二部分46与第三部分50顶部且三者的顶部均低于硬掩模20顶部，第一部分44底部低于第二部分46与第三部分50底部，第二部分46与第三部分50厚度均小于第一部分44厚度，以及第一部分44、第二部分46及第三部分50包含相同材料。需注意的是，本实施例的第二部分46宽度虽不同于第三部分50宽度，但依据本发明一实施例，第二部分46与第三部分50的宽度均可依据制作工艺需求调整，例如第二部分46宽度小于第三部分50宽度，第二部分46宽度大于第三部分50宽度，或第二部分46宽度等于第三部分50宽度，这些变化形均属本发明所涵盖的范围。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (5)

1.一种高电子迁移率晶体管，其特征在于，包含：
缓冲层，设于基底上；
阻障层，设于该缓冲层上；
硬掩模，设于该阻障层上；
P型半导体层，设于该阻障层上，其中该P型半导体层包含：
第一部分，设于该阻障层上；以及
第二部分，设于该硬掩模上；
栅极电极，设于该P型半导体层上；以及
源极电极以及漏极电极，相邻于该栅极电极两侧设于该缓冲层上。
2.如权利要求1所述的高电子迁移率晶体管，其中该硬掩模环绕该P型半导体层以及该栅极电极。
3.如权利要求1所述的高电子迁移率晶体管，其中该硬掩模设于该P型半导体层下方。
4.如权利要求1所述的高电子迁移率晶体管，其中该第一部分直接连接该第二部分。
5.如权利要求1所述的高电子迁移率晶体管，其中该P型半导体层包含P型氮化镓(pGaN)。
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