CN117970990B - Multi-loop fully integrated low-voltage-drop linear voltage stabilizer - Google Patents

Abstract

The invention relates to a multi-loop fully integrated low-voltage drop linear voltage stabilizer, which comprises a main loop and a secondary loop, wherein the main loop comprises a high-gain error amplifier circuit, a large-bandwidth buffer circuit, a high-current power tube, a feedback network, a first compensation capacitor and a second compensation capacitor, the secondary loop comprises a load following dynamic bias circuit and a dynamic zero generating circuit, and a transient response enhancing circuit is introduced into the large-bandwidth buffer circuit; and the stability problem of the feedback system of the linear voltage stabilizer after the off-chip capacitor is removed, and the problem that the service life of the battery is reduced due to the additional static power consumption required for ensuring the performance of the chip.

Description

Multi-loop fully integrated low-voltage-drop linear voltage stabilizer

Technical Field

The invention relates to adjustment of an electric variable in hardware service of industrial Internet of things service, in particular to a multi-loop fully-integrated low-voltage-drop linear voltage stabilizer.

Background

Power management chips (PMICs) in current mobile electronic devices require many low dropout linear regulators (LDOs) to provide a variety of different output voltages and load currents for a variety of different applications such as: photographic, storage, universal Serial Bus (USB), etc. to provide power. Typically, the power supply of the overall device is a fixed voltage lithium battery to support all of these application requirements. LDOs distribute the voltage and current in the battery to each required module, and have the following performance requirements to meet the relevant application requirements. The main performance requirements include low drop voltage and low quiescent current, so that the standby time of the battery can be prolonged as much as possible; the small chip area improves the integration level of the chip as much as possible, and reduces the cost of the chip; a high power supply rejection ratio to ensure noise rejection capability of the output voltage; high linear regulation rate and load regulation rate to ensure the accuracy of the output voltage; the system stability of different load conditions, and the transient response capability when the load current is subjected to transient transformation are all performance requirements to be considered by the LDO for different application conditions, such as the condition of heavy load current.

The traditional LDO architecture consists of an error amplifier, a feedback network, a power tube and an output load, and as the load current required by application is continuously improved, a buffer is introduced into the LDO architecture to serve as a driving stage between the error amplifier and the power tube, and the buffer is beneficial to the stability of a feedback system, and in order to ensure the stability of the system under the condition of high current, the frequency compensation is generally carried out on a closed loop system by adopting an ESR zero point generated by an off-chip large capacitor so as to improve the phase margin and the stability of the system. However, off-chip large capacitors are disadvantageous for the chip integration of LDOs because the required off-chip large capacitance is large, which is unacceptable for the production costs of the chip if integrated in the chip and the effectiveness of the resulting ESR (equivalent series resistance) zero over the full load range is difficult to guarantee due to the process errors present, so for high performance LDOs it is necessary to meet the design requirements without off-chip capacitors and to have as low quiescent current consumption as possible and to guarantee the stability of the whole circuit system over the full load range.

Disclosure of Invention

The primary purpose of the invention is to provide a multi-loop fully integrated low-voltage-drop linear voltage stabilizer, which solves the problems that a large off-chip capacitor in the low-voltage-drop linear voltage stabilizer consumes chip area and causes chip integration degree, and the stability of a feedback system of the linear voltage stabilizer after the off-chip capacitor is removed, and the problem that the battery life is attenuated due to additional static power consumption required by the consumption for ensuring the performance of the chip by optimally designing a high-gain error amplifier circuit and a large bandwidth buffer circuit in a main loop and introducing a load following dynamic bias circuit, a dynamic zero generating circuit and a transient response enhancing circuit into a secondary loop.

The invention at least provides the following technical scheme:

The invention provides a multi-loop fully integrated low-voltage-drop linear voltage stabilizer, which comprises a main loop and a secondary loop, wherein the main loop comprises a high-gain error amplifier circuit, a large-bandwidth buffer circuit, a large-current power tube, a feedback network and a first compensation capacitor And a second compensation capacitorThe secondary loop comprises a load following dynamic bias circuit and a dynamic zero generating circuit;

The high-gain error amplifier circuit is used for comparing a feedback voltage with a reference voltage and controlling the output voltage of a high-current power tube, providing a voltage node EAOUT, and realizing large low-frequency gain, and comprises a bias voltage providing part and a common-source common-gate amplifier, wherein the bias voltage providing part provides voltage nodes VBP0, VBP1, VBN0 and VBN1, and the common-source common-gate amplifier is connected to the voltage nodes VBP0, VBP1, VBN0 and VBN1;

the high-bandwidth buffer circuit is used as a buffer part of the high-gain error amplifier circuit and the power tube, drives the power tube and is connected among the bias voltage supply part, the voltage node EAOUT and the grid electrode of the high-current power tube;

the high-current power tube is used for generating a high load current, the output voltage of the high-current power tube is controlled by the error amplifier, the grid electrode of the high-current power tube is connected to the output node G, the source electrode of the high-current power tube is connected to a voltage source, and the drain electrode of the high-current power tube is connected to a feedback network;

the feedback network is connected between the high-current power tube and the high-gain error amplifier and is used for providing feedback voltage VFB;

The load following dynamic bias circuit is used for dynamically adjusting the magnitude of bias current along with the change condition of load current, providing needed change voltage signals for each bias circuit, generating voltage nodes VBUFF and VPFZ which follow the change of load, and connecting the voltage nodes VBUFF and VPFZ between an output node G and an output node VOUT of the large-bandwidth buffer circuit to generate dynamic bias current IADD flowing into the output node G of the buffer;

the dynamic zero generating circuit is used for dynamically following the load change and generating a corresponding dynamic zero to realize the zero pole cancellation effect with the secondary pole when the load change, so that the phase margin of the loop is improved, and the dynamic zero generating circuit is connected between a voltage node EAOUT and an output node G of the high-gain error amplifier circuit and connected with a voltage signal VPFZ;

The first compensation capacitor The PLUS terminal of the high-gain error amplifier is connected to the drain terminal of the high-current power transistor; the second compensation capacitorThe terminal PLUS of the high-current power tube is connected to the drain electrode of the high-current power tube, and the terminal MINUS of the high-current power tube is connected to the feedback voltage VFB;

The large bandwidth buffer circuit comprises a fourteenth PMOS transistor MP13, a fifteenth PMOS transistor MP14, a sixteenth PMOS transistor MP15, a seventeenth PMOS transistor MP16 and an eighteenth PMOS transistor MP17, and a seventh NMOS transistor MN6, an eighth NMOS transistor MN7, a ninth NMOS transistor MN8 and a tenth NMOS transistor MN9, wherein the source of MP13 is connected with the body end of MP13 to form an output node G, the gate of MP13 is connected with a voltage node EAOUT, and the drain of MP13 is connected with the drain of MN 8; the source electrode of MP14 is connected with power supply voltage, the grid electrode of MP14 is connected with the grid electrode of MP15, and the drain electrode of MP14 is connected with the source electrode of MP 13; the source electrode of MP15 is connected with the power supply voltage, the grid electrode of MP15 is connected with the drain electrode of MN7 and the drain electrode of MP 15; the source of MP16 is connected with the drain of MP17, the gate of MP16 is connected with voltage node VBP1, and the drain of MP16 is connected with the drain of MN 9; the source electrode of MP17 is connected with the power supply voltage, and the grid electrode of MP17 is connected with a voltage node VBP0; the drain of MN6 connects the source of MN7, the gate of MN6 connects voltage VBN0, the source of MN6 connects to ground; the gate of MN7 is connected with voltage VBN1; the source electrode of the MN8 is grounded, the grid electrode of the MN8 is connected with the grid electrode of the MN9, and the drain electrode of the MN8 is connected with the drain electrode of the MP 13; the source of MN9 is grounded, and the gate of MN9 is connected with the drain of MN9 and the drain of MP 16.

Further, the circuit further comprises a transient response enhancing circuit for enhancing the transient response capability of the low-dropout linear regulator when the load current changes, wherein a third capacitor C3, a fourth capacitor C4, a third resistor R3, a fourth resistor R4, an eleventh NMOS transistor MN10, a twelfth NMOS transistor MN11, a thirteenth NMOS transistor MN12 are introduced on the basis of the large-bandwidth buffer circuit, the grid electrode of the MN10 is connected with a voltage node VBUFF, the source electrode of the MN10 is grounded, and the drain electrode of the MN10 is connected with the drain electrode of the MP 15; the source electrode of the MN11 is grounded, the grid electrode of the MN11 is connected with the PLUS end of the C4 and the MINUS end of the fourth resistor R4, and the drain electrode of the MN11 is connected with the drain electrode of the MP13 and the PLUS end of the fourth resistor R4; the source electrode of the MN12 is grounded, the grid electrode of the MN12 is connected with the PLUS end of the fourth resistor R4 and the drain electrode of the fourteenth PMOS transistor MP13, and the drain electrode of the MN12 is connected with the grid voltage G of the power tube MP; the PLUS of R3 terminates the gate of MP15, and the MINUS of R3 terminates the gate of MP 14; PLUS of C3 terminates the gate of MP14 and MINUS of C3 terminates the drain of MP 13.

Further, the load following dynamic bias circuit includes a nineteenth PMOS transistor MP18, a twentieth PMOS transistor MP19, a twenty first PMOS transistor MP20, a twenty second PMOS transistor MP21, a twenty third PMOS transistor MP22, a twenty fourth PMOS transistor MP23, a twenty fifth PMOS transistor MP24, a twenty sixth PMOS transistor MP25, a fourteenth NMOS transistor MN13, a fifteenth NMOS transistor MN14, a sixteenth NMOS transistor MN15, a seventeenth NMOS transistor MN16, an eighteenth NMOS transistor MN17, and a nineteenth NMOS transistor MN18;

The source electrode of MP18 is connected with the output node VOUT, and the grid electrode of MP18 is connected with the grid electrode of MP19 and the drain electrode of MP 18; the source electrode of MP19 is connected with the drain electrode of MP20, and the drain electrode of MP19 is connected with the drain electrode of MN 14; the source electrode of MP20 is connected with the power supply voltage, the grid electrode of MP20 is connected with the grid electrode of MP21 and the output node G; the source electrode of MP21 is connected with the power supply voltage, the drain electrode of MP21 is connected with the drain electrode of MN15 and the drain electrode of MN 16; the source electrode of MP22 is connected with the power supply voltage, the grid electrode of MP22 is connected with the grid electrode of MP23 and the drain electrode of MP 22; the source electrode of MP23 is connected with the power supply voltage, and the drain electrode of MP23 is connected with the drain electrode of MN 18; the source electrode of MP24 is connected with the power supply voltage, the grid electrode of MP24 is connected with the grid electrode of MP25 and the drain electrode of MP24, the drain electrode of MP24 is connected with the drain electrode of MN18 and generates voltage to form voltage node VPFZ; the source electrode of the MP25 is connected with the power supply voltage, and the drain electrode of the MP25 is connected with the gate voltage G of the power transistor MP; the source electrode of the MN13 is grounded, the gate electrode of the MN13 is connected with the gate electrode of the MN14, and the drain electrode of the MN13 is connected with the drain electrode of the MP 18; the source electrode of the MN14 is grounded, and the gate electrode of the MN14 is connected with the drain electrode of the MN14 and the drain electrode of the MP 19; the source electrode of the MN15 is grounded, the gate electrode of the MN15 is connected with the gate electrode of the MN14, and the drain electrode of the MN15 is connected with the drain electrode of the MP 21; the source electrode of the MN16 is grounded, the gate electrode of the MN16 is connected with the gate electrode of the MN17 and the drain electrode of the MN16, and the drain electrode of the MN16 is connected with the drain electrode of the MP 21; the source electrode of the MN17 is grounded, and the drain electrode of the MN17 is connected with the drain electrode of the MP 22; the source of MN18 is grounded, the gate of MN18 is connected to the gate of MN15 and generates a voltage to form a voltage node VBUFF, and the drain of MN18 is connected to the drain of MP 23.

Further, the dynamic zero generating circuit includes a fifth capacitor C5, a sixth capacitor C6, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a twenty-seventh PMOS transistor MP26, a twenty-eighth PMOS transistor MP27, a twenty-ninth PMOS transistor MP28, a thirty-first PMOS transistor MP29, a thirty-first PMOS transistor MP30, a twenty-first NMOS transistor MN19, a twenty-first NMOS transistor MN20, a twenty-second NMOS transistor MN21, a twenty-third NMOS transistor MN22, a twenty-fourth NMOS transistor MN23, and a twenty-fifth NMOS transistor MN24;

PLUS of C5 terminates voltage node EAOUT, MINUS of C5 terminates the gate of MN 22; the PLUS of C6 terminates the output node G, the MINUS of C6 terminates the gate of MN 23; PLUS of R5 terminates the drain of MP26, MINUS of R5 terminates the drain of MN 20; the PLUS of R6 terminates the gate of MN21 and the MINUS of R6 terminates the gate of MN 22; the PLUS of R7 terminates the gate of MN23 and the MINUS of R7 terminates the gate of MN 24; the source of MP26 is connected with the power voltage, the gate of MP26 is connected with the voltage VPFZ, and the drain of MP26 is connected with the gate of MN 20; the source electrode of MP27 is connected with the power supply voltage, the grid electrode of MP27 is connected with the drain electrode of MP27 and the drain electrode of MN 21; the source electrode of MP28 is connected with power supply voltage, the grid electrode of MP28 is connected with the grid electrode of MP27, and the drain electrode of MP28 is connected with the drain electrode of MN 22; the source electrode of MP29 is connected with power supply voltage, the grid electrode of MP29 is connected with drain electrode of MP29 and drain electrode of MN 23; the source electrode of MP30 is connected with the power supply voltage, the grid electrode of MP30 is connected with the grid electrode of MP29, and the drain electrode of MP30 is connected with the drain electrode of MN 24; the source electrode of the MN19 is grounded, the gate electrode of the MN19 is connected with the gate electrode of the MN24 and the MINUS end of the R5, and the drain electrode of the MN19 is connected with the source electrode of the MN 20; the grid electrode of the MN20 is connected with the grid electrode of the MN21 and the PLUS end of the R5, and the drain electrode of the MN20 is connected with the MINUS end of the R5; the source electrode of the MN21 is grounded, and the drain electrode of the MN21 is connected with the drain electrode of the MP 27; the source electrode of the MN22 is grounded, and the drain electrode of the MN22 is connected with the drain electrode of the MP 28; the source electrode of the MN23 is grounded, and the drain electrode of the MN23 is connected with the drain electrode of the MP 29; the source of MN24 is grounded, and the drain of MN24 is connected to the drain of MP 30.

Further, the bias voltage providing part includes a first resistor R1, a second resistor R2, a first PMOS transistor MP0, a second PMOS transistor MP1, a third PMOS transistor MP2, and a fourth PMOS transistor MP3, sources of the first NMOS transistor MN0 and the second NMOS transistor MN1, MP0, and MP2 are connected to a power supply voltage, gates of MP0 and MP2 are connected to a drain of MP1 and generate a voltage forming voltage node VBP0, a drain of MP0 is connected to a source of MP1, and a drain of MP2 is connected to a source of MP 3; the gates of MP1 and MP3 are connected with the MINUS end of R1 and generate voltage to form a voltage node VBP1, the MINUS end of R1 is connected with a current source, and the PLUS end of R1 is connected with the gates of MP0 and MP2 and the drain of MP 1; the drain electrode of MP3 is connected with the PLUS end of R2; the PLUS terminal of R2 is connected with the grid electrode generating voltage forming voltage node VBN1 of MN1, the MINUS terminal of R2 is connected with the grid electrode generating voltage forming voltage node VBN0 of MN0, the drain electrode of MN1 is connected with the MINUS terminal of R2, the source electrode of MN1 is connected with the drain electrode of MN0, and the source electrode of MN0 is grounded.

Further, the cascode amplifier includes a fifth PMOS transistor MP4, a sixth PMOS transistor MP5, a seventh PMOS transistor MP6, an eighth PMOS transistor MP7, a ninth PMOS transistor MP8, a tenth PMOS transistor MP9, an eleventh PMOS transistor MP10, a twelfth PMOS transistor MP11, a thirteenth PMOS transistor MP12, a third NMOS transistor MN2, a fourth NMOS transistor MN3, a fifth NMOS transistor MN4, and a sixth NMOS transistor MN5; the source electrode of MP4 is connected with the power supply voltage, the grid electrode of MP4 is connected with the voltage VBP0, the drain electrode of MP4 is connected with the source electrodes of MP5 and MP6, the grid electrode of MP5 is connected with the feedback voltage VFB, the drain electrode of MP5 is connected with the drain electrode of MN2, the grid electrode of MP6 is connected with the reference voltage VREF, and the drain electrode of MP6 is connected with the drain electrode of MN 3; the source electrode of MP7 is connected with the drain electrode of MP9, the grid electrode of MP7 is connected with the voltage node VBP1, the drain electrode of MP7 is connected with the grid electrode of MP9 and the drain electrode of MN4, the source electrode of MP8 is connected with the drain electrode of MP10, the grid electrode of MP8 is connected with the voltage node VBP1, the drain electrode of MP8 is connected with the drain electrode of MN5, and voltage is generated to form a voltage node EAOUT; the source electrode of MP9 is connected with the drain electrode of MP11, and the grid electrode of MP9 is connected with the grid electrode of MP10 and the drain electrode of MP 7; the source electrode of MP10 is connected with the drain electrode of MP 12; the source electrode of MP11 is connected with the power supply voltage, and the grid electrode of MP11 is connected with the grid electrode of MP12 and the grid electrode of MP 9; the sources of the MN2 and the MN3 are grounded, the drain electrode of the MN2 is connected with the drain electrode of the MP5, and the drain electrode of the MN3 is connected with the drain electrode of the MP 6; the source of MN4 is connected with the drain of MN2, the drain of MN4 is connected with the drain of MP7, the gate of MN4 is connected with the gate of MN5 and is connected with the voltage node VBN1, and the source of MN5 is connected with the drain of MN 3.

Further, the feedback network comprises a first feedback resistor RF1 and a second feedback resistor RF2; the PLUS terminal of RF1 is connected to the MINUS terminal of C _M1, the drain of the high-current power transistor MP and the output node VOUT, the MINUS terminal of RF1 is connected to the PLUS terminal of RF2, and the MINUS terminal of RF2 is grounded.

Further, a first compensation capacitorThe MINUS of the PLUS is connected with the output node VOUT of the high-power transistor MP; The PLUS terminal of the power transistor MP is connected to the PLUS terminals of the output node VOUT and RF1 of the power transistor MP, The terminal of the PLUS of the feedback voltages VFB and RF 2.

Further, MP13 is a low-threshold PMOS transistor with small channel length;

Further, MP24 and MP25 are low threshold small channel length PMOS transistors.

Further, the channel length of MP20 is identical to the channel length of the high current power transistor MP.

Further, MP20 is of uniform size and aspect ratio as MP 21.

Compared with the prior art, the invention has at least the following beneficial effects:

The invention ensures the requirement of the main performance index of the LDO through the high-performance LDO main loop, in particular to a high-gain error amplifier formed by a bias voltage supply part and a cascode amplifier and a buffer circuit matched with the high-gain error amplifier and having large driving capability and large bandwidth, realizes the large low-frequency gain and large bandwidth of the linear voltage regulator, ensures that the main loop of the linear voltage regulator is at a static working point of normal operation and can drive a large-current power tube with large transistor area and large grid parasitic capacitance; meanwhile, the load following dynamic bias circuit and the dynamic zero generating circuit are introduced into the secondary loop, so that the stability of the feedback circuit is improved, the dynamic bias current is provided, the transient response capability is improved, and the quiescent current consumption required by the low-voltage drop linear voltage stabilizer in the static operation is reduced; furthermore, the transient response enhancing circuit is introduced on the basis of the large-bandwidth buffer circuit, so that the charge and discharge speed and the response speed of the high-current power tube are improved, and the accuracy of an output voltage value is ensured. Finally, the fully integrated low-voltage-drop linear voltage stabilizer with high performance is realized.

Drawings

Fig. 1 is a diagram of a conventional LDO structure.

Fig. 2 is a circuit diagram of a high-performance multi-loop fully integrated LDO main loop according to the present invention.

Fig. 3 is a diagram of a load following dynamic bias circuit introduced by a secondary loop of the present invention.

Fig. 4 is a circuit diagram of dynamic zero generation introduced by the secondary loop of the present invention.

Fig. 5 is a circuit diagram of transient response enhancement introduced by the secondary loop of the present invention.

FIG. 6 is a block diagram of an overall architecture of a multi-loop fully integrated low dropout linear regulator of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. Based on the embodiments of the present invention, other embodiments that may be obtained by those of ordinary skill in the art without making any inventive effort are within the scope of the present invention.

The use of "having," "containing," "including," etc. in this specification is an open-ended term that indicates the presence of the stated element or feature, but does not preclude additional elements or features. Unless the context clearly dictates otherwise.

In the invention, the large bandwidth refers to the gain bandwidth product GBW reaching more than 1 MHz.

In a low-threshold small channel length PMOS transistor, the low threshold refers to a threshold voltage of about 400mV, and the small channel length refers to a minimum channel length in the process of about 130 nm.

The high current of the high current power tube is greater than or equal to 100mA.

An embodiment of the invention provides a multi-loop fully integrated low-dropout linear voltage regulator, which comprises a main loop and a secondary loop, wherein the main loop comprises a high-gain error amplifier circuit, a large-bandwidth buffer circuit, a large-current power tube, a feedback network and a first compensation capacitorAnd a second compensation capacitorThe secondary loop includes a load following dynamic bias circuit, a dynamic zero generation circuit, and a transient response enhancement circuit.

The high gain error amplifier circuit is composed of a bias voltage supply part and a common-source common-gate amplifier, and the large bandwidth buffer circuit is selected from buffer circuits with large driving capability and large bandwidth, so that the large current power tube with large transistor area and large gate parasitic capacitance can be driven. The design of the high-gain error amplifier circuit can realize maximum gain, the power supply rejection ratio is good, and the power consumption is small.

Fig. 2 is a circuit diagram of a high-performance multi-loop fully integrated LDO main loop according to an embodiment of the present invention, wherein the high-gain error amplifier comprises a bias voltage supply part and a cascode amplifier, and a reference voltage source (not shown) provides a reference voltage VREF for the high-gain error amplifier. In this embodiment, in order to realize a high gain error amplifier, a folded cascode amplifier is formed from transistors MP4 to MP12 and MN2 to MN5, and the bias voltage required for the amplifier is provided by transistors MP0 to MP3, MN0 to MN1 and resistors R1 and R2, and the required transistor size is obtained by determining the magnitude of the bias voltage and the magnitude of the saturation current flowing through the transistors, so as to ensure that the amplifier can realize a large low frequency gain, which can be as high as 80dB. In order to realize large bandwidth, the buffer adopts an improved source follower structure, and the structure can drive a large PMOS power tube while ensuring that the LDO main loop is at a static working point for normal operation. Because the load current of the LDO has a large variation range, the variation range of the grid voltage of the PMOS power tube is also large, and the output swing of the corresponding error amplifier is also large, but if the output swing of the error amplifier is too large, the static working point of the error amplifier is inevitably changed, and the gain of the error amplifier is obviously reduced. And since the input and output voltage difference of a general source follower is about its threshold voltage, to ensure that the LDO main loop works normally over the whole load range, the input and output voltage difference of the source follower, i.e. its threshold voltage, needs to be lowered.

In this embodiment, the large bandwidth buffer is composed of transistors MP13 to MP17, MN6 to MN9, the body terminal and the source terminal of the transistor MP13 are connected together to the output node G in order to reduce the threshold voltage, and the transistor MP13 is a low-threshold small channel length PMOS transistor in order to further reduce the threshold voltage. And the bandwidth of the entire loop is also increased due to the increase in the cut-off frequency of the transistor caused by the decrease in the channel length of the transistor, and the bandwidth can be further increased by controlling the magnitude of the bias current flowing through the source follower. A specific addition method will be described in the following transient response enhancement circuit. In addition to ensuring stability of the static operating point, the LDO loop acts as a negative feedback system, which ensures stability of the whole system, and frequency compensation is required. The frequency compensation of the main loop adopts a compensation capacitorOne end is connected to the source end of the transistor MP10 and the drain end of the transistor MP12, and the other end is connected to the output node VOUT of the LDO to realize indirect Miller compensation, so that the pole splitting of the main pole and the secondary pole is realized, and the bandwidth can be correspondingly improved. Compensation capacitorIs connected between the output node VOUT and the feedback voltage VFB, and acts together with the feedback resistor RF1 to generate a zero point to improve the phase margin, thereby improving the stability of the system.

The feedback network comprises a first feedback resistor RF1 and a second feedback resistor RF2; PLUS termination of RF1 to compensation capacitanceThe MINUS terminal of RF2, the drain of the high-current power transistor MP, and the output node VOUT, the MINUS terminal of RF1, and the MINUS terminal of RF 2.

The high current power tube MP generates a large load current and the magnitude of its output voltage is controlled by the error amplifier, its gate is connected to the output node G, its source is connected to the voltage source, and its drain is connected to the feedback network and the output load.

Fig. 3 is a diagram of an embodiment of a dynamic bias circuit for secondary loop load following, in which gates of transistors MP20 and MP21 are connected to an output node G of a main loop, a source of transistor MP18 is connected to an output node VOUT of an LDO, a current flowing through MP18 is a part of a load current, a drain voltage of transistor MP20 is clamped with a load current flowing through MP18 by transistors MP18 and MP19, MN13 and MN14, if a channel length of transistor MP20 is consistent with a channel length of a high current power transistor MP, a current flowing through MP20 is linearly proportional to a current flowing through the high current power transistor MP, and an additional quiescent current required to be consumed for realizing a function of tracking a load current is small and a response speed of tracking a load current is also fast due to a circuit structure composed of transistors MP18 and MP19 and transistors MN13 and MN14 being selected to be suitable. The transistors MP21 and MP20 are identical in size and aspect ratio, and when they operate in the saturation region as MP20, they generate a current flowing through the transistor MN16, and the current trend is identical to the load current trend, so that when the LDO is in light load, the current flowing through the MN16 is almost zero, and MN16 at this time can be regarded as off, so that the purpose of further reducing the quiescent current can be achieved. When the LDO is operated under heavy load, the current flowing through the transistor MN16 will increase, and the MN16 is operated in the saturation region, and the current mirror effect of the transistor MN17 will convert the increasing trend of the current to the transistor MP22. As the current through MP22 increases and the signal of transistor MP23 transitions, the small channel length low threshold transistors MP24 and MP25 begin to turn on and correspondingly change the gate voltage signals VPFZ of MP24 and MP25 as the load current continues to increase, and a dynamic bias current IADD will be generated through transistor MP25 into the buffer output node G. The voltage signal forming voltage nodes VBUFF and VBFZ and the dynamic bias current IADD that follow the load variations can be generated by the circuit, and the quiescent current that the whole circuit portion needs to consume under reasonable transistor size design is also small.

In this embodiment, the secondary loop dynamic zero generating circuit shown in fig. 4 is introduced at the voltage node EAOUT and the output node G, the gate of the transistor MP26 is connected to the generated voltage signal VPFZ following the load change, and since the voltage value of VPFZ is generated by the small channel length low threshold transistors MP24 and MP25, the voltage value does not reach the on voltage value of the transistor MP26, and the transistor MP26 at this time is in the subthreshold operation state, so that the current flowing through the transistor MP26 is small, but a voltage drop will be generated at the transistor MP26, and the voltage drop is applied to the gates of the transistors MN19 and MN20 through the resistor R5, respectively connected to the gates of the transistors MN21 and MN 24. The gate of transistor MN21 is connected to the gate of transistor MN22 through resistor R6, the gate of transistor MN24 is connected to the gate of transistor MN23 through resistor R7, and the gate of transistor MN22 is also connected to the voltage node EAOUT of the error amplifier through capacitor C5, while the gate of transistor MN23 is also connected to the buffer output node G through capacitor C6. By connecting the corresponding main loop nodes to form corresponding secondary loops, the dynamic zero generating circuit can realize phase compensation of the frequency response of the whole LDO loop under different load conditions. Through the change of the gate voltage signal VPFZ of the transistor MP26, the corresponding gate voltage value of each transistor is changed, and then through the combined action of the resistor R6, the resistor R7 and the capacitors C5 and C6, corresponding compensation zero points are generated at the secondary pole points to realize the offset effect of the zero points and the poles, so that the phase margin is improved, and the aim that the whole LDO feedback system has good stability in the full load range is fulfilled. And because the voltage value change is adopted to reflect the positions of the secondary poles under different load conditions needing compensation, the transistors of the circuit part are in a sub-threshold on state, so that the quiescent current required to be consumed by the whole secondary loop dynamic zero generating circuit is very small, and the quiescent current consumption of the proposed high-performance multi-loop full-integrated LDO is greatly reduced.

In the embodiment, the transient response enhancing circuit is introduced into the large-bandwidth buffer circuit, and the introduction of the buffer circuit accelerates the charge and discharge speed of the parasitic capacitance of the grid electrode of the high-current power tube, improves the response speed of the grid electrode voltage of the power tube, so that the power tube can adjust the output load current more quickly, the overshoot of the output voltage is reduced, and the accuracy of the output voltage value is ensured. As shown in fig. 5, transistors MN10, MN11 and MN12, resistors R3 and R4, and capacitors C3 and C4 are introduced on the basis of the original large bandwidth buffer circuit. The gate of transistor MN10 is connected to voltage node VBUFF, which is changed by the load, and the transistor will be turned on gradually as the load current increases, and thus will introduce additional bias current into transistor MP15, and the gate of transistor MP15 is connected to the gate of transistor MP14 through resistor R3 by the current mirror effect, so that the current flowing through MP14 will also increase accordingly, resulting in a corresponding increase in the current flowing through buffer transistor MP13, which will increase the bandwidth of the buffer due to the increase in bias current. The drain of the transistor MP13 is connected to the gate of the transistor MP14 through the capacitor C3, so that the current flowing through the transistor MP13 can be fed back to the transistor MP14 at high frequency, which is equivalent to forming a flip-flop voltage follower, so as to improve the small signal response capability of the original source follower, that is, the transient response capability. Through the alternating current small signal coupling of the resistor R3 and the capacitor C3, the transient response capability improvement on the basis of the original large-bandwidth buffer circuit is realized. In order to improve the driving capability of the large bandwidth buffer, the buffer is required to have a large slew rate and a small output impedance because of a large gate parasitic capacitance generated by a large transistor area of the high power transistor. The drain of the transistor MP13 is connected to the drain of the transistor MN11 and the gate of the transistor MN12, and the drain of the transistor MN12 is connected to the output node G of the buffer. Such a configuration achieves a reduction in equivalent output impedance by introducing transistor MN12 at the output node of the buffer, as this corresponds to a parallel connection of a size at the output nodeTo achieve an effect of reducing output impedance, in whichIs the transconductance value of transistor MN 12. And since MN12 can realize better transient response when light load becomes heavy load, since the gate voltage of the PMOS power transistor is higher when LDO is light load, the corresponding gate voltage will be smaller when heavy load is heavy load, so the gate voltage of MP13 will also have the same change trend, that is, the gate voltage becomes smaller, which will cause the current flowing through MP13 to increase, the increased current will flow into transistor MN11, but the gate voltage of MN11 will remain unchanged earlier due to the effect of capacitor C4, and since MN11 is in saturation region, the current flowing through it increases but the gate-source voltage is unchanged, the drain voltage thereof will increase, which will cause the gate voltage of MN12 to increase, the current flowing through transistor MN12 increases due to the increase of the gate voltage thereof, thereby improving the capability of flowing current from the large gate capacitor of the large current power transistor through MN12, so the speed of lowering the gate voltage of the large current power transistor is accelerated, so that it can be lowered to a low voltage value required by the large load current, thereby realizing the effect of raising transient response capability.

The whole LDO circuit structure diagram of the multi-loop fully integrated linear voltage regulator chip provided by the invention is shown in fig. 6, so that the feedback loop stability under the condition of ensuring the full load range of the LDO without large off-chip capacitance can be realized, the full on-chip integration of the linear voltage regulator chip can be realized, large quiescent current is not required to be consumed, and good linear adjustment rate, load adjustment rate and load change transient response can be realized.

The above examples are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above examples, and any other changes, modifications, substitutions, combinations, and simplifications that do not depart from the spirit and principle of the present invention should be made in the equivalent manner, and the embodiments are included in the protection scope of the present invention.

Claims (8)

1. The multi-loop fully integrated low-voltage drop linear voltage stabilizer is characterized by comprising a main loop and a secondary loop, wherein the main loop comprises a high-gain error amplifier circuit, a large-bandwidth buffer circuit, a large-current power tube, a feedback network and a first compensation capacitorAnd a second compensation capacitorThe secondary loop comprises a load following dynamic bias circuit and a dynamic zero generating circuit;

The high-gain error amplifier circuit is used for comparing feedback voltage with reference voltage and controlling output voltage of a high-current power tube, providing a voltage node EAOUT, realizing large low-frequency gain, and consists of a bias voltage providing part and a folding type common-source common-gate amplifier, wherein the bias voltage providing part provides voltage nodes VBP0, VBP1, VBN0 and VBN1, and the folding type common-source common-gate amplifier is connected to the voltage nodes VBP0, VBP1, VBN0 and VBN1; the folded cascode amplifier includes a fifth PMOS transistor MP4, a sixth PMOS transistor MP5, a seventh PMOS transistor MP6, an eighth PMOS transistor MP7, a ninth PMOS transistor MP8, a tenth PMOS transistor MP9, an eleventh PMOS transistor MP10, a twelfth PMOS transistor MP11, a thirteenth PMOS transistor MP12, a third NMOS transistor MN2, a fourth NMOS transistor MN3, a fifth NMOS transistor MN4, and a sixth NMOS transistor MN5;

The source electrode of MP4 is connected with the power supply voltage, the grid electrode of MP4 is connected with the voltage VBP0, the drain electrode of MP4 is connected with the source electrodes of MP5 and MP6, the grid electrode of MP5 is connected with the feedback voltage VFB, the drain electrode of MP5 is connected with the drain electrode of MN2, the grid electrode of MP6 is connected with the reference voltage VREF, and the drain electrode of MP6 is connected with the drain electrode of MN 3; the source of MP7 is connected with the drain of MP9, the grid of MP7 is connected with the voltage node VBP1, the drain of MP7 is connected with the grid of MP9, the source of MP8 is connected with the drain of MP10, and the grid of MP8 is connected with the voltage node VBP1; the source electrode of MP9 is connected with the drain electrode of MP11, and the grid electrode of MP9 is connected with the grid electrode of MP 10; the source electrode of MP10 is connected with the drain electrode of MP 12; the source electrode of MP11 is connected with the power supply voltage, and the grid electrode of MP11 is connected with the grid electrode of MP12 and the grid electrode of MP 9; the sources of the MN2 and the MN3 are grounded, the drain electrode of the MN2 is connected with the drain electrode of the MP5, and the drain electrode of the MN3 is connected with the drain electrode of the MP 6; the source of MN4 connects with the drain of MN2, the drain of MN4 connects with the drain of MP7, the gate of MN4 connects with the gate of MN5 and connects with voltage node VBN1, the source of MN5 connects with the drain of MN3, the drain of MN5 connects with the drain of MP8 and generates voltage to form voltage node EAOUT;

The high-bandwidth buffer circuit is used as a buffer part of the high-gain error amplifier circuit and the high-current power tube, drives the high-current power tube and is connected among the bias voltage supply part, the voltage node EAOUT and the grid electrode of the high-current power tube; the large bandwidth buffer circuit comprises a fourteenth PMOS transistor MP13, a fifteenth PMOS transistor MP14, a sixteenth PMOS transistor MP15, a seventeenth PMOS transistor MP16 and an eighteenth PMOS transistor MP17, and a seventh NMOS transistor MN6, an eighth NMOS transistor MN7, a ninth NMOS transistor MN8 and a tenth NMOS transistor MN9, wherein the source of MP13 is connected with the body end of MP13 to form an output node G, the grid electrode of MP13 is connected with a voltage node EAOUT, and the drain of MP13 is connected with the drain of MN 8; the source electrode of MP14 is connected with power supply voltage, the grid electrode of MP14 is connected with the grid electrode of MP15, and the drain electrode of MP14 is connected with the source electrode of MP 13; the source electrode of MP15 is connected with the power supply voltage, the grid electrode of MP15 is connected with the drain electrode of MN7 and the drain electrode of MP 15; the source of MP16 is connected with the drain of MP17, the gate of MP16 is connected with voltage node VBP1, and the drain of MP16 is connected with the drain of MN 9; the source electrode of MP17 is connected with the power supply voltage, and the grid electrode of MP17 is connected with a voltage node VBP0; the drain of MN6 connects the source of MN7, the gate of MN6 connects voltage VBN0, the source of MN6 connects to ground; the gate of MN7 is connected with voltage VBN1; the source electrode of the MN8 is grounded, and the gate electrode of the MN8 is connected with the gate electrode of the MN 9; the source electrode of the MN9 is grounded, and the gate electrode of the MN9 is connected with the drain electrode of the MN9 and the drain electrode of the MP 16;

the high-current power tube is used for generating a large load current, the output voltage of the high-current power tube is controlled by the high-gain error amplifier circuit, the grid electrode of the high-current power tube is connected to the output node G, the source electrode of the high-current power tube is connected to a voltage source, and the drain electrode of the high-current power tube is connected to a feedback network;

the feedback network is connected between the high-current power tube and the high-gain error amplifier circuit and is used for providing feedback voltage VFB;

The load following dynamic bias circuit is used for generating a dynamic bias current IADD flowing into an output node G of the large bandwidth buffer circuit according to the change condition of the load current, dynamically adjusting the magnitude of the dynamic bias current and providing a change voltage node VBUFF and VPFZ which are required to follow the load change for each bias circuit, and comprises a nineteenth PMOS transistor MP18, a twentieth PMOS transistor MP19, a twenty first PMOS transistor MP20, a twenty second PMOS transistor MP21, a twenty third PMOS transistor MP22, a twenty fourth PMOS transistor MP23, a twenty fifth PMOS transistor MP24, a twenty sixth PMOS transistor MP25, a fourteenth NMOS transistor MN13, a fifteenth NMOS transistor MN14, a sixteenth NMOS transistor MN15, a seventeenth NMOS transistor MN16, an eighteenth NMOS transistor MN17 and a nineteenth NMOS transistor MN18;

The source electrode of MP18 is connected with the output node VOUT, and the grid electrode of MP18 is connected with the grid electrode of MP19 and the drain electrode of MP 18; the source electrode of MP19 is connected with the drain electrode of MP20, and the drain electrode of MP19 is connected with the drain electrode of MN 14; the source electrode of MP20 is connected with the power supply voltage, the grid electrode of MP20 is connected with the grid electrode of MP21 and the output node G; the source electrode of MP21 is connected with the power supply voltage, the drain electrode of MP21 is connected with the drain electrode of MN15 and the drain electrode of MN 16; the source electrode of MP22 is connected with the power supply voltage, the grid electrode of MP22 is connected with the grid electrode of MP23 and the drain electrode of MP 22; the source electrode of MP23 is connected with the power supply voltage, and the drain electrode of MP23 is connected with the drain electrode of MN 18; the source electrode of MP24 is connected with the power supply voltage, the grid electrode of MP24 is connected with the grid electrode of MP25 and the drain electrode of MP24, the drain electrode of MP24 is connected with the drain electrode of MN18 and generates voltage to form voltage node VPFZ; the source electrode of the MP25 is connected with the power supply voltage, and the drain electrode of the MP25 is connected with the grid voltage G of the high-current power tube; the source electrode of the MN13 is grounded, the gate electrode of the MN13 is connected with the gate electrode of the MN14, and the drain electrode of the MN13 is connected with the drain electrode of the MP 18; the source electrode of the MN14 is grounded, and the gate electrode of the MN14 is connected with the drain electrode of the MN14 and the drain electrode of the MP 19; the source electrode of the MN15 is grounded, the gate electrode of the MN15 is connected with the gate electrode of the MN14, and the drain electrode of the MN15 is connected with the drain electrode of the MP 21; the source electrode of the MN16 is grounded, the gate electrode of the MN16 is connected with the gate electrode of the MN17 and the drain electrode of the MN16, and the drain electrode of the MN16 is connected with the drain electrode of the MP 21; the source electrode of the MN17 is grounded, and the drain electrode of the MN17 is connected with the drain electrode of the MP 22; the source electrode of the MN18 is grounded, the gate electrode of the MN18 is connected with the gate electrode of the MN15 and generates voltage to form a voltage node VBUFF, and the drain electrode of the MN18 is connected with the drain electrode of the MP 23;

the dynamic zero generating circuit is used for dynamically following the load change and generating a corresponding dynamic zero to realize the zero pole cancellation effect with the secondary pole when the load change, so that the phase margin of the loop is improved, and the dynamic zero generating circuit is connected between a voltage node EAOUT and an output node G of the high-gain error amplifier circuit and connected with a voltage signal VPFZ;

The first compensation capacitor The terminal PLUS of the transistor is connected to the source electrode of the MP10 and the drain electrode of the MP12, and the terminal MINUS of the transistor is connected to the drain electrode of the high-current power tube; the second compensation capacitorThe terminal PLUS of the transistor is connected to the drain of the high-current power transistor, and the terminal MINUS is connected to the feedback voltage VFB.

2. The linear voltage regulator of claim 1, further comprising a transient response enhancement circuit for enhancing a transient response capability of the low dropout linear voltage regulator when the load current is changed, introducing a third capacitor C3, a fourth capacitor C4, a third resistor R3, a fourth resistor R4, an eleventh NMOS transistor MN10, a twelfth NMOS transistor MN11, a thirteenth NMOS transistor MN12, a gate of MN10 being connected to the voltage node VBUFF, a source of MN10 being connected to ground, a drain of MN10 being connected to a drain of MP15 on the basis of the large bandwidth buffer circuit; the source electrode of the MN11 is grounded, the grid electrode of the MN11 is connected with the PLUS end of the C4 and the MINUS end of the fourth resistor R4, and the drain electrode of the MN11 is connected with the drain electrode of the MP13 and the PLUS end of the fourth resistor R4; the source electrode of the MN12 is grounded, the grid electrode of the MN12 is connected with the PLUS end of the fourth resistor R4 and the drain electrode of the fourteenth PMOS transistor MP13, and the drain electrode of the MN12 is connected with the grid voltage G of the high-current power tube; the PLUS of R3 terminates the gate of MP15, and the MINUS of R3 terminates the gate of MP 14; PLUS of C3 terminates the gate of MP14 and MINUS of C3 terminates the drain of MP 13.

3. The linear voltage regulator according to claim 1 or 2, wherein the dynamic zero generating circuit includes a fifth capacitor C5, a sixth capacitor C6, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a twenty-seventh PMOS transistor MP26, a twenty-eighth PMOS transistor MP27, a twenty-ninth PMOS transistor MP28, a thirty-seventh PMOS transistor MP29, a thirty-first PMOS transistor MP30, a twenty-first NMOS transistor MN19, a twenty-first NMOS transistor MN20, a twenty-second NMOS transistor MN21, a twenty-third NMOS transistor MN22, a twenty-fourth NMOS transistor MN23, a twenty-fifth NMOS transistor MN24;

PLUS of C5 terminates voltage node EAOUT, MINUS of C5 terminates the gate of MN 22; the PLUS of C6 terminates the output node G, the MINUS of C6 terminates the gate of MN 23; PLUS of R5 terminates the drain of MP26, MINUS of R5 terminates the drain of MN 20; the PLUS of R6 terminates the gate of MN21 and the MINUS of R6 terminates the gate of MN 22; the PLUS of R7 terminates the gate of MN23 and the MINUS of R7 terminates the gate of MN 24; the source of MP26 is connected with the power voltage, the gate of MP26 is connected with the voltage VPFZ, and the drain of MP26 is connected with the gate of MN 20; the source electrode of MP27 is connected with the power supply voltage, the grid electrode of MP27 is connected with the drain electrode of MP27 and the drain electrode of MN 21; the source electrode of MP28 is connected with power supply voltage, the grid electrode of MP28 is connected with the grid electrode of MP27, and the drain electrode of MP28 is connected with the drain electrode of MN 22; the source electrode of MP29 is connected with power supply voltage, the grid electrode of MP29 is connected with drain electrode of MP29 and drain electrode of MN 23; the source electrode of MP30 is connected with the power supply voltage, the grid electrode of MP30 is connected with the grid electrode of MP29, and the drain electrode of MP30 is connected with the drain electrode of MN 24; the source electrode of the MN19 is grounded, the gate electrode of the MN19 is connected with the gate electrode of the MN24 and the MINUS end of the R5, and the drain electrode of the MN19 is connected with the source electrode of the MN 20; the grid electrode of the MN20 is connected with the grid electrode of the MN21 and the PLUS end of the R5, and the drain electrode of the MN20 is connected with the MINUS end of the R5; the source electrode of the MN21 is grounded, and the drain electrode of the MN21 is connected with the drain electrode of the MP 27; the source electrode of the MN22 is grounded, and the drain electrode of the MN22 is connected with the drain electrode of the MP 28; the source electrode of the MN23 is grounded, and the drain electrode of the MN23 is connected with the drain electrode of the MP 29; the source of MN24 is grounded, and the drain of MN24 is connected to the drain of MP 30.

4. The linear voltage regulator according to claim 1 or 2, wherein the bias voltage supply section includes a first resistor R1, a second resistor R2, a first PMOS transistor MP0, a second PMOS transistor MP1, a third PMOS transistor MP2, a fourth PMOS transistor MP3, sources of the first NMOS transistor MN0 and the second NMOS transistor MN1, MP0 and MP2 are connected to a power supply voltage, gates of MP0 and MP2 are connected to a drain of MP1 and a voltage generating voltage forming voltage node VBP0, a drain of MP0 is connected to a source of MP1, and a drain of MP2 is connected to a source of MP 3; the gates of MP1 and MP3 are connected with the MINUS end of R1 and generate voltage to form a voltage node VBP1, the MINUS end of R1 is connected with a current source, and the PLUS end of R1 is connected with the gates of MP0 and MP2 and the drain of MP 1; the drain electrode of MP3 is connected with the PLUS end of R2; the PLUS terminal of R2 is connected with the grid electrode generating voltage forming voltage node VBN1 of MN1, the MINUS terminal of R2 is connected with the grid electrode generating voltage forming voltage node VBN0 of MN0, the drain electrode of MN1 is connected with the MINUS terminal of R2, the source electrode of MN1 is connected with the drain electrode of MN0, and the source electrode of MN0 is grounded.

5. The linear regulator of claim 4, wherein the feedback network comprises a first feedback resistor RF1 and a second feedback resistor RF2; the PLUS of RF1 is terminated to the MINUS terminal of C _M1, the drain of the high current power transistor, and the output node VOUT, the MINUS of RF1 is terminated to the PLUS terminal of RF2, and the MINUS of RF2 is grounded.

6. The linear voltage regulator of claim 5, wherein the first compensation capacitorThe MINUS of the (E) is connected with an output node VOUT of the high-current power tube; The PLUS terminal of the output node VOUT and RF1 of the high-current power tube, The MINUS termination RF2 PLUS terminal.

7. The linear voltage regulator of claim 1, 2, 5 or 6, wherein MP13 is a low threshold small channel length PMOS transistor;

MP24 and MP25 are low threshold small channel length PMOS transistors.

8. The linear voltage regulator of claim 7, wherein the channel length of MP20 is consistent with the channel length of the high current power tube; MP20 and MP21 are of the same size and aspect ratio.