CN117970407A - Digital nuclear pulse signal processor adopting neural network processor architecture - Google Patents

Abstract

The invention discloses a digital nuclear pulse signal processor adopting a neural network processor architecture, which relates to the field of radiation detection and comprises the following components: the radiation detector is used for receiving radiation rays and converting the radiation rays into voltage pulse signals; the conversion circuit is used for converting the voltage pulse signal into a digital signal; the FPGA circuit extracts pulse waveform data in the digital signals, sends the pulse waveform data to the SoC circuit, receives a data channel control signal and result data returned by the SoC circuit, selects target data from the pulse waveform data and the result data, extracts amplitude information and time information, and transmits the amplitude information and the time information to the SoC circuit; the result data is pulse waveform data after filtering and noise reduction; the SoC circuit receives pulse waveform data, amplitude information and time information, and applies a neural network model loaded by the NPU processor to obtain result data, and determines the position information and corresponding case information of the radiation rays. The invention can process and analyze the nuclear pulse signal on line in real time.

Description

Digital nuclear pulse signal processor adopting neural network processor architecture

Technical Field

The invention relates to the field of radiation detection, in particular to a digital nuclear pulse signal processor adopting a neural network processor architecture.

Background

In the field of radiation detection, the real-time online processing and analysis of nuclear pulse signals are of great significance. Due to different targets of nuclear physical experiments and different nuclear technology application occasions, embedded equipment with different functions, such as a multichannel analyzer for extracting amplitude information of pulse signals for recording and displaying energy spectrums, often need to be designed and developed at the rear end of the detector; the pulse width measuring instrument is used for measuring the width of the pulse signal, namely the pulse duration; the digital storage oscilloscope may capture and store waveform data of the high-speed pulse signal. Therefore, it is necessary to develop a digital pulse processor which can realize complete measurement of physical parameters of rays and even realize some complex measurement requirements aiming at high performance and general purpose type of different application occasions.

With the development of computer technology, artificial neural network technology has been applied to various industries, and advances in the industry are being promoted. Along with the rapid development, an SoC chip with a neural Network Processor (NPU) is developed, and an artificial neural network model is deployed in an embedded system, so that the real-time online data processing by using the artificial neural network model is a trend of the future artificial neural network technology development. At present, a mode of disposing an artificial neural network model in embedded equipment to perform online processing on data is mainly applied to the field of image processing, and related literature data using the method is not referred to in the field of nuclear physics, so that the technology is applied to the field of nuclear physics, a set of digital nuclear pulse signal processor based on a neural network processor architecture is developed, and the data processing and analysis of pulse signals in a nuclear physical experiment by utilizing the artificial neural network model disposed in an NPU are very significant for the development of nuclear technology.

Disclosure of Invention

The invention aims to provide a digital nuclear pulse signal processor adopting a neural network processor architecture, which can process and analyze nuclear pulse signals on line in real time.

In order to achieve the above object, the present invention provides the following solutions:

A digital nuclear pulse signal processor employing a neural network processor architecture, the processor comprising: the device comprises an SoC circuit, an FPGA circuit, a radiation detector and a conversion circuit;

The radiation detector is used for receiving radiation rays and converting the energy of the radiation rays into voltage pulse signals;

The conversion circuit is connected with the radiation detector; the conversion circuit is used for converting the voltage pulse signal into a digital signal;

The FPGA circuit is respectively connected with the conversion circuit and the SoC circuit; the FPGA circuit is used for extracting pulse waveform data from the digital signals, sending the pulse waveform data to the SoC circuit, receiving a data channel control signal and result data returned by the SoC circuit, selecting target data from the pulse waveform data and the result data according to the data channel control signal, extracting amplitude information and time information of the target data, and transmitting the amplitude information and the time information to the SoC circuit;

The SoC circuit comprises an NPU processor; the SoC circuit is used for receiving the pulse waveform data, the amplitude information and the time information, filtering the pulse waveform data by applying a first neural network model loaded by the NPU processor to obtain result data, determining the position information of the radiation rays from the result data by applying a second neural network model loaded by the NPU processor, determining the case information corresponding to the radiation rays by applying a third neural network model loaded by the NPU processor according to the result data, and storing the position information, the case information, the amplitude information and the time information.

Optionally, the conversion circuit includes an analog front-end circuit and an ADC conversion circuit;

The analog front-end circuit is connected with the radiation detector; the analog front-end circuit is used for filtering, amplifying and bias adjusting the voltage pulse signal to obtain a processed analog signal;

The ADC conversion circuit is connected with the analog front-end circuit; the ADC conversion circuit is used for converting the processed analog signals into digital signals.

Optionally, the FPGA circuit includes a data stitching module, a waveform extraction module, a selection module, and a digital algorithm module;

The splicing module is connected with the ADC conversion circuit; the splicing module is used for splicing the digital signals into data with sixteen-bit data length to obtain spliced data;

The waveform extraction module is respectively connected with the data splicing module and the SoC circuit; the waveform extraction module is used for extracting the pulse waveform data from the spliced data and transmitting the pulse waveform data to the SoC circuit;

The selection module is respectively connected with the SoC circuit and the waveform extraction module; the selection module receives a data channel control signal and result data returned by the SoC circuit, and selects target data from the pulse waveform data and the result data according to the data channel control signal;

The digital algorithm module is connected with the selection module; the digital algorithm module is used for extracting amplitude information and time information of the target data and transmitting the amplitude information and the time information to the SoC circuit.

Optionally, the FPGA circuit further comprises an output interface;

the output interface is connected with the digital algorithm module; the output interface is used for outputting the amplitude information and the time information of the target data.

Optionally, the output interface is a USB3.0 interface.

Optionally, the SoC circuit further comprises a CPU processor;

The CPU processor is respectively connected with the NPU processor and the FPGA circuit; the CPU processor is used for transmitting the result data to the FPGA circuit, receiving the amplitude information and the time information, receiving the position information and the case information, and storing the position information, the case information, the amplitude information and the time information.

Optionally, the SoC circuit further comprises an output module;

The output module is connected with the CPU processor; the output module is used for outputting the position information, the case information, the amplitude information and the time information.

Optionally, the output module includes an ethernet interface and a USB3.0 interface; the Ethernet interface and the USB3.0 interface are respectively connected with the CPU processor.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects:

The invention provides a digital nuclear pulse signal processor adopting a neural network processor architecture, which comprises the following components: the device comprises an SoC circuit, an FPGA circuit, a radiation detector and a conversion circuit; receiving radiation rays by using a radiation detector, and converting the energy of the radiation rays into a voltage pulse signal; by connecting the conversion circuit with the radiation detector; converting the voltage pulse signal into a digital signal by using a conversion circuit; the switching circuit is connected with the SoC circuit through the FPGA circuit; extracting pulse waveform data in the digital signal by using the FPGA circuit, sending the pulse waveform data to the SoC circuit, receiving a data channel control signal and result data returned by the SoC circuit, selecting target data from the pulse waveform data and the result data according to the data channel control signal, extracting amplitude information and time information of the target data, and transmitting the amplitude information and the time information to the SoC circuit; finally, the SoC circuit includes an NPU processor; the SoC circuit receives pulse waveform data, amplitude information and time information, performs filtering processing on the pulse waveform data by using a first neural network model loaded by the NPU processor to obtain result data, determines the position information of the radiation rays from the result data by using a second neural network model loaded by the NPU processor, determines case information corresponding to the radiation rays according to the result data by using a third neural network model loaded by the NPU processor, and stores the position information, the case information, the amplitude information and the time information. The invention realizes real-time on-line processing and analysis of the nuclear pulse signal through the SoC circuit, and obtains the position information, the case information, the amplitude information and the time information of the radiation ray in real time.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a hardware architecture of a nuclear pulse signal processor according to the present invention;

FIG. 2 is a block diagram of a hardware architecture of a nuclear pulse signal processor when a data selector selects waveform data 1 according to the present invention;

FIG. 3 is a block diagram of a hardware architecture of a nuclear pulse signal processor when the data selector selects waveform data 2 according to the present invention;

FIG. 4 is a schematic diagram of a convolutional neural network model (CNN) of the present invention for predicting case types based on pulse signal sequences;

FIG. 5 is a schematic diagram of white noise suppression and baseline restoration process according to the present invention;

FIG. 6 is a schematic diagram of the low frequency noise suppression process of the present invention;

FIG. 7 is a schematic diagram of the transient noise suppression process of the present invention;

FIG. 8 is a schematic diagram of a pile-up pulse recovery process according to the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The invention aims to provide a digital nuclear pulse signal processor adopting a neural network processor architecture, which can process and analyze nuclear pulse signals on line in real time.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

Example 1

As shown in fig. 1, the present invention provides a digital nuclear pulse signal processor employing a neural network processor architecture, the processor comprising: the device comprises an SoC circuit, an FPGA circuit, a radiation detector and a conversion circuit.

The radiation detector is used for receiving radiation rays and converting energy of the radiation rays into voltage pulse signals.

The conversion circuit is connected with the radiation detector; the conversion circuit is used for converting the voltage pulse signal into a digital signal.

The FPGA circuit is respectively connected with the conversion circuit and the SoC circuit; the FPGA circuit is used for extracting pulse waveform data from the digital signals, sending the pulse waveform data to the SoC circuit, receiving a data channel control signal and result data returned by the SoC circuit, selecting target data from the pulse waveform data and the result data according to the data channel control signal, extracting amplitude information and time information of the target data, and transmitting the amplitude information and the time information to the SoC circuit.

The SoC circuit comprises an NPU processor; the SoC circuit is used for receiving the pulse waveform data, the amplitude information and the time information, filtering the pulse waveform data by applying a first neural network model loaded by the NPU processor to obtain result data, determining the position information of the radiation rays from the result data by applying a second neural network model loaded by the NPU processor, determining the case information corresponding to the radiation rays by applying a third neural network model loaded by the NPU processor according to the result data, and storing the position information, the case information, the amplitude information and the time information.

Specifically, the conversion circuit includes an analog front-end circuit and an ADC conversion circuit.

The analog front-end circuit is connected with the radiation detector; the analog front-end circuit is used for filtering, amplifying and bias adjusting the voltage pulse signal to obtain a processed analog signal.

The ADC conversion circuit is connected with the analog front-end circuit; the ADC conversion circuit is used for converting the processed analog signals into digital signals.

Specifically, the FPGA circuit comprises a data splicing module, a waveform extraction module, a selection module and a digital algorithm module.

The splicing module is connected with the ADC conversion circuit; the splicing module is used for splicing the digital signals into data with sixteen-bit data length to obtain spliced data.

The waveform extraction module is respectively connected with the data splicing module and the SoC circuit; the waveform extraction module is used for extracting the pulse waveform data from the spliced data and transmitting the pulse waveform data to the SoC circuit.

The selection module is respectively connected with the SoC circuit and the waveform extraction module; the selection module receives a data channel control signal and result data returned by the SoC circuit, and selects target data from the pulse waveform data and the result data according to the data channel control signal.

The digital algorithm module is connected with the selection module; the digital algorithm module is used for extracting amplitude information and time information of the target data and transmitting the amplitude information and the time information to the SoC circuit.

Further, the FPGA circuit also includes an output interface.

The output interface is connected with the digital algorithm module; the output interface is used for outputting the amplitude information and the time information of the target data. The output interface is a USB3.0 interface.

As a specific embodiment, the SoC circuit further includes a CPU processor.

The CPU processor is respectively connected with the NPU processor and the FPGA circuit; the CPU processor is used for transmitting the result data to the FPGA circuit, receiving the amplitude information and the time information, receiving the position information and the case information, and storing the position information, the case information, the amplitude information and the time information.

As a specific embodiment, the SoC circuit further comprises an output module.

The output module is connected with the CPU processor; the output module is used for outputting the position information, the case information, the amplitude information and the time information.

Further, the output module comprises an Ethernet interface and a USB3.0 interface; the Ethernet interface and the USB3.0 interface are respectively connected with the CPU processor.

As shown in fig. 1, the NPU-based nuclear pulse signal processor provided by the present invention includes an SoC processor, an FPGA circuit, a radiation detector, an analog front-end circuit, and a high-speed ADC circuit.

The radiation detector is used for receiving radiation rays such as alpha beta particles, gamma rays, neutrons and the like, converting the energy of the rays into voltage pulse signals and outputting the voltage pulse signals.

The analog front-end circuit mainly carries out filtering square and bias adjustment on the pulse signals output from the detector, so that the amplitude of the pulse signals is as close to the full range of the high-speed ADC circuit as possible when the pulse signals are input to the high-speed ADC, the resolution of the high-speed ADC is fully utilized, and the quantization error is reduced.

The high-speed ADC circuit performs analog-to-digital conversion on the pulse signal, converts the analog signal into a digital signal, and inputs the digital signal to the back-end digital signal processing circuit for calculation and analysis. In order to obtain more accurate analysis results in the subsequent operational analysis of the FPGA and NPU, the sampling rate and resolution of the ADC should be as high as possible to obtain sufficient sampling points and sampling accuracy.

The FPGA circuit performs data splicing on digital signals output by the high-speed ADC, the level signals of the high-speed ADC are spliced into 16-bit data, then pulse waveform data are extracted from the original data, the pulse waveform is identified in a threshold triggering mode, when the arrival of the pulse signals is identified, data of a fixed number of sampling points are respectively recorded and stored forwards and backwards by taking the maximum value of the pulse signals as the center, the data of the sampling points cover the whole pulse waveform interval, the extracted pulse waveform data are used as input data of a subsequent FPGA digital algorithm and an SoC processor, and effective information is extracted by performing operation analysis on the data. The data selector (MUX) between the waveform extraction module and the digital algorithm provides a flexible configuration function for the processor, ctrl controls a data channel selected by the data selector, when waveform data 1 is selected as input data of the digital algorithm in the FPGA, the SoC processor and the FPGA are required to work cooperatively, the extracted pulse waveform data is filtered and noise reduced by a neural network self-encoder of the NPU through the SoC processor and then is transmitted to the FPGA again as original data of the digital algorithm. The data splicing module is used for splicing the data input from the ADC; the waveform extraction module is used for extracting pulse waveform data from a large amount of original sampling data according to a fixed time length; the data selector is used for selecting a signal source input to the back-end digital algorithm; the FIFO is used for data caching; the shaping algorithm module is used for carrying out digital shaping on the original pulse waveform, and the amplitude extraction module is used for extracting the waveform amplitude after shaping; the constant ratio time digitizing algorithm and the time extracting module are used for intercepting the count value of the duration of a certain section of the waveform and converting the count value into time information. The digital algorithm is not limited to the above two types, and the USB3.0 module is used for transmitting the extracted parameter data to the PC end upper computer through the USB 3.0.

The digital shaping algorithm, the amplitude extraction, the constant ratio timing digitization algorithm and the time extraction are all existing algorithms.

In particular, the digital shaping algorithm is to shape pulse waveforms, because noise is superimposed in the original pulse waveforms, the waveforms may be stacked together, and the amplitude of the original waveform is a peak, which is difficult to accurately measure, so that the signal is preferably shaped by the shaping algorithm before the amplitude of the pulse signal is obtained, which has the advantages of filtering the signal to suppress the noise, separating the stacked signals, and widening the peak of the signal, so as to conveniently extract the amplitude at the highest position. Common shaping algorithms include a trapezoidal shaping algorithm, a Gaussian shaping algorithm, a triangular shaping algorithm and the like, and the specific implementation process and principle of the algorithms are all in the prior art and are not repeated here.

The amplitude extraction module delays the sampling point of the formed signal after pulse forming to exceed a set threshold value for a fixed time length, so that the amplitude value at the highest position after forming can be obtained.

The constant ratio timing digitization algorithm is to take the number of sampling points with the pulse signal amplitude within a certain range; the time extraction module is known in sampling frequency, and can calculate the duration time in the interval range according to the number of sampling points extracted by the constant ratio timing digitization algorithm. The digital shaping algorithm and the amplitude extraction module are combined to extract the amplitude of the pulse signal; the constant ratio timing digitization algorithm and the time extraction module are combined to extract the duration time of the pulse signal amplitude within a certain range. These are all parameters used to extract some of the features on the pulse signal.

The essence of the nuclear pulse signal processor is that the characteristic parameters of the pulse signal are obtained by some methods, and the characteristic parameters include, but are not limited to: amplitude, signal duration, location information of energy deposition, instance type, etc. Wherein the amplitude and signal duration are relatively easy to extract and thus can be obtained using some conventional digitizing algorithms; deposit location information and instance type discrimination is often difficult to accurately identify and analyze, requiring analysis and extraction using neural network models. Thus, the digitizing algorithm deployed in the FPGA is used to extract simple amplitude and time information, and the neural network model deployed in the NPU is used to extract deposition location and case type information. The digital algorithm in the FPGA extracts characteristic information such as amplitude, duration and the like of the pulse signal, and the characteristic information is a part of the main functions of the nuclear pulse signal processor.

Ctrl is the control signal of the data selector, which determines the channel selected by the data selector. May be implemented in hardware or software. The software implementation mode is as follows: and configuring a Ctrl control interface of the data selector to be 0 or 1 in the program of the FPGA, and setting the data selector to select a corresponding channel after the FPGA burns the program. Hardware implementation mode: a Ctrl control interface of a data selector in the FPGA is configured and connected to an FPGA pin, the pin is connected with a power supply or a ground through a connector to endow the pin with high and low levels, the high level is correspondingly endowed with 1, the low level is correspondingly endowed with 0, and therefore a channel selected by the data selector is controlled. The control signal of the data selector is mainly configured according to the hardware requirement of the system, for example, in some simple application occasions, the control signal can be realized only by extracting some conventional parameters such as amplitude, rising time and the like of pulse waveforms, and can be realized only by an FPGA (field programmable gate array), and a neural network arranged in an NPU (network programmable logic unit) is not required to analyze, so that the cost is saved, the hardware structure of the system is simplified, an SoC (system on chip) processor module is not required to be installed, a Ctrl interface can be configured to be 0 through software or hardware configuration, the waveform data 2 output by a waveform extraction module is selected as input data of a digital algorithm of a rear-end FPGA (field programmable gate array), and the system is simplified to be a nuclear pulse signal processor as shown in fig. 3; for some application occasions of complex environments, such as poor quality of nuclear pulse signals, low signal to noise ratio or the situation types of energy deposition positions and interaction of rays in a detector to be analyzed, when a single digitization algorithm using an FPGA cannot accurately analyze and discriminate, a neural network model arranged in an NPU needs to be used for analysis in an SoC processor, a neural network self-encoder can filter and noise-reduce the nuclear pulse signals, at the moment, a Ctrl interface is configured as 1, the nuclear pulse signals subjected to noise reduction through the neural network self-encoder are selected as input data of a rear-end FPGA digitization algorithm, and the waveform characteristics such as amplitude, duration and the like can be extracted from the nuclear pulse signals more accurately through the digitization algorithm of the FPGA after the nuclear pulse signals are subjected to noise reduction and filtering.

The SoC processor adopts a heterogeneous architecture, and a CPU processing unit and an NPU processing unit of an ARM architecture are arranged in the processor. The CPU processing unit runs an application program written in a C language under a Linux environment, and loads an artificial neural network model trained in advance by calling an API (application program interface) of the NPU provided by a chip manufacturer, so that the artificial neural network model is deployed in the NPU, the CPU processing unit controls and dispatches data, dispatches pulse data in sequence and inputs the pulse data to the NPU for operation and analysis, and the NPU processing engine has different functions by deploying different models, for example, when the deployed models are neural network self-encoders, the pulse waveform data suppresses noise in waveform data after operation of the models in the NPU; when the deployed model is an artificial neural network model with a position screening or instance screening function, after the data is operated by the model in the NPU, the result is a coded probability value of the position or a probability value of an instance type, and after post-processing in the CPU, the position code and the instance type with the maximum probability value are taken, so that the position screening and the instance screening are realized. The function of the pulse processor designed by the invention can be expanded according to the function of the loaded artificial neural network model, so that the pulse processor has strong universality. The artificial neural network self-encoder is a neural network model loaded for the NPU and is used for filtering and reducing noise on waveform data; the artificial neural network model for position discrimination and instance type discrimination is used for calculating and analyzing the position codes and instance type codes of energy deposition according to the input pulse waveform data. The models and functions that the NPU can actually load are not limited to the above three models and functions.

The position discrimination refers to the position of energy deposition of particles or rays in the detector, for example, for a high-purity germanium detector, the position of energy deposition of gamma rays in the detector can influence the shape of a pulse waveform output by the detector, and the position information of energy deposition can be reversely deduced according to the shape characteristics of the pulse waveform; for the strip scintillator detector, the quantity of photon attenuation generated by energy deposition of gamma rays at different lengths of the detector is different in the transmission process of photons to the two electrodes, so that the pulse signal amplitude generated by the two electrodes is different, and the energy deposition position can be reversely deduced according to the amplitude information of the two signals. The analysis process of the pulse waveform can be realized by a neural network model deployed in the NPU, so that the position information of the energy deposition of particles or rays in the detector can be inferred and output, the position information can be encoded by carrying out space division on the detector, and the neural network model can determine the space information of the energy deposition of the rays in the detector by outputting an encoding value.

The case discrimination refers to discriminating particles, rays or case types interacted with the detector according to the shape characteristics of the pulse waveform output by the detector, for example, alpha and beta particles and gamma rays have different interaction mechanisms with a liquid scintillator (liquid flash), the shape and the amplitude of the pulse waveform output by the corresponding liquid flash are different, and the three types of particles are discriminated according to the shape characteristic differences of the waveform; in neutron-gamma screening applications, neutrons and gamma rays have different action mechanisms from the detector, the differences are represented on the falling edge of the output voltage pulse waveform of the detector, and the screening of the neutron gamma is realized according to the shape differences of the falling edge of the waveform. The analysis of waveform characteristics can also be implemented using neural network models deployed in the NPU to implement case type discrimination.

The waveform characteristic analysis and reasoning process is complex, the conventional PSD (Pulse shape discrimination ) method is difficult to accurately discriminate the energy deposition position and the instance type, and the discrimination algorithm can not be realized through a Pulse Shape Discrimination (PSD) algorithm deployed in the FPGA, so that the analysis is required to be performed by using an artificial neural network model deployed in an NPU processing engine, and the discrimination purpose is realized.

The following description of the function of the present invention in two modes of operation specifically includes:

the system framework of the pulse processor can be simplified to that shown in fig. 2 when the waveform data 1 is selected by the data selector. When the NPU processing unit is not required to work, the data selector selects the waveform data 2, and the pulse processor becomes a conventional digital pulse signal processor, so that the power consumption and the cost are reduced, and the system framework can be simplified into fig. 3. The pulse processor may thus be selectively configured as needed for the environment and function.

After the nuclear pulse signal processor is configured on the data selector, the nuclear pulse signal processor can be switched between a combined working mode of the SoC processor and the FPGA and an independent working mode of the FPGA, so that the flexibility of the function of the nuclear pulse signal processor is improved, and the nuclear pulse signal processor is more suitable for the change of a measuring environment and the requirement of a user. Two modes of operation are described in detail below:

SoC processor+FPGA combined working mode: in this mode the NPU and FPGA operate simultaneously. In the FPGA, a data selector (MUX) selects waveform data 1 as the input data of a shaping algorithm and constant ratio, the waveform data 1 has lower noise and higher signal-to-noise ratio after being filtered and noise reduced by an artificial neural network self-encoder, and the extracted pulse amplitude and time information have higher precision after being processed by the shaping algorithm and the constant ratio algorithm in the FPGA. In the NPU processing unit, the nuclear pulse signals filtered and noise reduced by the neural network self-encoder are simultaneously transmitted to the artificial neural network models 1 and 2 at the rear end to carry out energy deposition position screening and instance type screening, probability values corresponding to each position code and instance type code are stored in an output structure body variable, and the position number and instance type number with the maximum probability value are extracted after the post-processing of the CPU processing unit. The amplitude and time information of the nuclear pulse signals extracted by the FPGA are transmitted to the memory space applied by the CPU processing unit of the SoC processor in a parallel communication mode, and finally the amplitude, time information, position codes and instance type codes are cached in the particle instance data packet FIFO under the control of the CPU processing unit, and then the data is transmitted to the data acquisition terminal through Ethernet communication or transmitted to the upper computer software of the PC terminal through USB 3.0.

Fpga single operation mode: in the mode, only the FPGA works, the SoC processor does not work, and even the core board of the SoC processor can be removed to reduce the product cost, and the overall power consumption of the system can be correspondingly reduced. The data selector selects the waveform data 2 as a signal source of the FPGA back-end digitizing algorithm. In this mode, since the neural network model deployed in the NPU processing unit is not used by the SoC processor to perform the kernel pulse signal feature extraction and analysis, the pulse waveform information extracted by the system is derived only from the amplitude and time information extracted by the digitizing algorithm in the FPGA.

In the system, the neural network model needs to analyze and predict according to the discrete data of the nuclear pulse signal, so that the shape characteristics of the nuclear pulse signal are fully acquired by acquiring as many sampling points as possible of the nuclear pulse signal, and therefore, a high-speed high-precision analog-to-digital converter (ADC) is needed. Meanwhile, the functions of the artificial neural network model include, but are not limited to, filtering noise reduction, position screening and instance screening, and in the nuclear physics field, other problems which can be solved by using the artificial neural network technology can be solved by disposing the corresponding model in an NPU hardware platform so as to expand the functions and application range of the architecture.

The following connection relation, signal flow direction and cooperative working process of the nuclear pulse signal processor are as follows:

SoC processor+FPGA combined working mode.

The radiation rays deposit energy in the radiation detector, the radiation energy is converted into voltage pulse signals, the voltage pulse signals are output from the radiation detector, the voltage pulse signals are transmitted into an analog front-end circuit through the transmission of a coaxial line, after the processing of the analog front-end circuit, the nuclear pulse signals are directly transmitted to a high-speed ADC circuit through a signal wire of a PCB, the high-speed ADC circuit carries out analog-to-digital conversion on the nuclear pulse signals, the digital signals are transmitted to an FPGA circuit through the signal wire of the PCB, a data splicing module in the FPGA carries out bit splicing on data transmitted by the high-speed ADC, the bits are spliced into 16-bit nibbles according to the communication protocol of the high-speed ADC, a waveform extraction module in the FPGA carries out triggering screening on the nuclear pulse signals, if the screened data transmitted into the FPGA is nuclear pulse signal data, the nuclear pulse signal data with fixed length is intercepted and transmitted to a sending FIFO for caching, the data buffered in the FIFO is the fixed length nuclear pulse signal data, these data are transmitted to the SoC processor through parallel communication, under the control and coordination of CPU processing unit, the nuclear pulse signal data are loaded into the input structure variable of the neural network model as the input data of the model, firstly, the neural network self-encoder deployed in the NPU operates the nuclear pulse signal data in the input structure variable, after realizing filtering and noise reduction, the processed nuclear pulse signal data are stored in the output structure variable, the CPU processing unit takes out the nuclear pulse signal data from the output structure variable and divides into two paths for transmission, one path of nuclear pulse signal data is transmitted back to the receiving FIFO in the FPGA circuit through parallel communication, the digital algorithm deployed in the FPGA reads the nuclear pulse signal data from the receiving FIFO for characteristic parameter extraction, through the digital algorithm, for example, a trapezoidal shaping algorithm and a constant ratio timing digitization algorithm extract information such as the amplitude, the front edge time and the like of a nuclear pulse signal, and then the parameter information is transmitted to a memory space applied by a CPU processing unit in the SoC processor in a parallel communication mode; the other path of nuclear pulse signal data is loaded into a structural body variable input by a later stage neural network model under the control of a CPU processing unit, the other path of nuclear pulse signal data is used as input data of the later stage artificial neural network model deployed in the NPU, when the later stage artificial neural network model deployed in the NPU has the function of energy deposition position screening or particle and instance type screening, the radiation ray energy deposition position information or the type of radiation rays corresponding to the nuclear pulse signal can be obtained according to the model through the operation and reasoning of the nuclear pulse signal data of the input structural body variable, the probability value corresponding to the position code or instance type code is stored in an output structural body variable, and the CPU processing unit reads the result data of the output structural body variable, and obtains the position code or instance type code with the highest probability value after the post-processing of a program. Finally, the amplitude, the front time, the position code and the case type code of the nuclear pulse signal are packed into particle case data packets, the particle case data packets are buffered in the FIFO, and the particle case data packets are transmitted to PC end upper computer software or a data acquisition terminal in a USB3.0 or Ethernet communication mode.

The FPGA independent working mode specifically comprises the following steps:

Compared with a combined working mode of an SoC processor and an FPGA, the mode is mainly different in that an SoC processor circuit is canceled. In the FPGA circuit, the waveform data extracted by the waveform extraction module is directly transmitted to a digital algorithm of a next stage of the FPGA to extract nuclear pulse signal information. And finally, nuclear pulse signal information extracted by a digitizing algorithm in the FPGA is transmitted to an upper computer at a PC end through USB 3.0. The connection relation and signal flow direction of the analog circuit part are the same as those in the combined working mode of SoC processor and FPGA.

The invention relates to a nuclear pulse signal on-line processing and analyzing method based on an NPU hardware platform, which is characterized in that:

The nuclear pulse signal has the characteristics of randomness and short waveform duration, pulse accumulation phenomenon can occur in the measuring environment of the strong radioactive source, and the threshold triggering, the pulse signal shape screening and the energy resolution of the system can be influenced by electronic noise. Thus, a series of methods are developed to suppress noise, correct aliasing problems and realize case discrimination. Solving the above problems using conventional digital algorithms is not only very difficult to implement, requires a large amount of logic resources, but also has a general effect. The problems can be quickly and efficiently solved by using the artificial neural network technology, the artificial neural network model is deployed on an NPU hardware platform, and the pulse signals obtained by nuclear physical experiments or radiation detection can be effectively analyzed and processed on line by using the artificial neural network model, and more complex particle information on-line measurement can be realized. The deployment process mainly goes through the following stages: training and verifying the artificial neural network model, converting the format of the model file, optimizing and quantizing the new model file, and finally copying the quantized model file into a system related directory to be loaded by a main program.

The key points of the method mainly comprise two stages of model training and model deployment. The model training is to make related data sets according to the application occasion requirements to train the built neural network model, and the model file after training can be used for subsequent deployment. The model deployment process has a standard deployment flow, and the model deployment process has been briefly introduced in the previous section. Fig. 4 is a schematic diagram of a convolutional neural network model (CNN) for predicting case types according to a pulse signal sequence. The process of the neural network model in the NPU to process the signal data is similar to the flow shown in fig. 4. And finally, deploying the trained artificial neural network model on embedded equipment and a mobile terminal with a neural network processor to realize on-line analysis processing of the nuclear pulse signals.

The online processing and analyzing process of the invention is as follows:

The nuclear pulse signal processor performs pulse waveform processing and analysis and can be divided into three parts according to functionality, wherein the first part consists of a radiation detector, an analog front-end circuit and a high-speed ADC (analog to digital converter), the radiation energy is mainly converted into an analog voltage signal and then is converted into a digital signal, the detector firstly converts the radiation energy into the voltage pulse signal, the voltage pulse signal with proper amplitude is obtained through filtering, amplifying and biasing of the analog front-end circuit, and then the voltage pulse signal is input into the high-speed ADC circuit to convert the analog signal into a digital signal and input into the next part of circuit, so that the conversion from radiation rays to the analog voltage signal and then to the digital signal is realized. The second part is composed of FPGA circuits, mainly realizes bit splicing of digital signals, extraction of pulse waveform data and extraction of effective information on pulse waveforms by using a digitizing algorithm, and only can extract some simple pulse waveform characteristic information because the digitizing algorithm can only carry out some simple operation on the waveform data. The third part consists of SoC circuits integrated with NPU processing engines, after nuclear pulse signal data transmitted by an FPGA are processed by a neural network self-encoder deployed in the NPU, noise is restrained on the premise of retaining original waveform characteristics, one path of obtained new high-quality waveform data is transmitted back to a FIFO buffer area of the FPGA circuit through parallel communication, the other path of nuclear pulse signal data is stored in an input structure variable of a neural network model under the control of a CPU processing unit, the neural network model carries out operation reasoning on the nuclear pulse signal data in the input structure variable, more complex information is extracted from the nuclear pulse signal data, and different complex information data can be extracted from models with different functions. And finally, the pulse waveform information extracted by a digitizing algorithm in the FPGA circuit and the pulse waveform information extracted by an artificial neural network model in the NPU circuit are cached in a particle instance data packet FIFO under the control of a CPU processing unit in the SoC processor and then are sent to a data acquisition terminal or an upper computer at the PC end through a communication interface.

The characteristics and advantages of the NPU processing unit are as follows:

After deployment is completed, the digital pulse signals are firstly stored in the input structure variables of the model to wait for being loaded and operated by the NPU, white noise superposed on the signals is suppressed to a certain extent through the operation of the NPU, meanwhile, the NPU is used for carrying out baseline restoration on the signals, as shown in fig. 5, high-quality signals with high signal to noise ratio are obtained, then the processed signals are input into a post-stage FPGA for carrying out algorithm processing, and modules such as a baseline restorer and a digital filter are not required to be redesigned in the FPGA, so that the logic resource occupation and development difficulty of the FPGA are greatly reduced, the energy resolution of the system is improved, the threshold false triggering rate is reduced, and the performance of the system is improved. The functionality and application range of the nuclear pulse signal processor can also be expanded by deploying an artificial neural network model in some other application aspects of the nuclear physics field in the NPU. For the low-frequency noise and the transient noise superimposed on the signal, as shown in fig. 6 and 7, after the processing of the neural network model in the NPU, the noise part can be filtered out, and the signal part is reserved, so that the signal quality is improved; for the pulse stacking situation in the experimental process, a neural network model for resisting pulse stacking can be deployed in the NPU, and the stacked pulses are expanded into single independent pulses after NPU operation processing, as shown in fig. 8.

The invention has the following advantages:

1. The invention designs a nuclear pulse signal processor hardware architecture based on NPU, and the defects of single application occasion, difficult and complicated function change of the traditional nuclear pulse signal processor hardware architecture based on FPGA are overcome by deploying different neural network models in the NPU to adapt to different application occasions of complex particle information measurement.

2. The invention adopts NPU as hardware platform for deployment of artificial neural network model to process and analyze nuclear pulse signal on line, which overcomes the disadvantage that artificial neural network model in nuclear physical experiment and nuclear technology can only process pulse data off line due to oversized model scale and large deployment difficulty.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.

Claims (8)

1. A digital nuclear pulse signal processor employing a neural network processor architecture, the processor comprising: the device comprises an SoC circuit, an FPGA circuit, a radiation detector and a conversion circuit;

The radiation detector is used for receiving radiation rays and converting the energy of the radiation rays into voltage pulse signals;

The conversion circuit is connected with the radiation detector; the conversion circuit is used for converting the voltage pulse signal into a digital signal;

The FPGA circuit is respectively connected with the conversion circuit and the SoC circuit; the FPGA circuit is used for extracting pulse waveform data from the digital signals, sending the pulse waveform data to the SoC circuit, receiving a data channel control signal and result data returned by the SoC circuit, selecting target data from the pulse waveform data and the result data according to the data channel control signal, extracting amplitude information and time information of the target data, and transmitting the amplitude information and the time information to the SoC circuit;

The SoC circuit comprises an NPU processor; the SoC circuit is used for receiving the pulse waveform data, the amplitude information and the time information, filtering the pulse waveform data by applying a first neural network model loaded by the NPU processor to obtain result data, determining the position information of the radiation rays from the result data by applying a second neural network model loaded by the NPU processor, determining the case information corresponding to the radiation rays by applying a third neural network model loaded by the NPU processor according to the result data, and storing the position information, the case information, the amplitude information and the time information.

2. The digital nuclear pulse signal processor employing a neural network processor architecture of claim 1, wherein the conversion circuit comprises an analog front-end circuit and an ADC conversion circuit;

The analog front-end circuit is connected with the radiation detector; the analog front-end circuit is used for filtering, amplifying and bias adjusting the voltage pulse signal to obtain a processed analog signal;

The ADC conversion circuit is connected with the analog front-end circuit; the ADC conversion circuit is used for converting the processed analog signals into digital signals.

3. The digital nuclear pulse signal processor adopting a neural network processor architecture according to claim 2, wherein the FPGA circuit comprises a data stitching module, a waveform extraction module, a selection module and a digital algorithm module;

The splicing module is connected with the ADC conversion circuit; the splicing module is used for splicing the digital signals into data with sixteen-bit data length to obtain spliced data;

The waveform extraction module is respectively connected with the data splicing module and the SoC circuit; the waveform extraction module is used for extracting the pulse waveform data from the spliced data and transmitting the pulse waveform data to the SoC circuit;

The selection module is respectively connected with the SoC circuit and the waveform extraction module; the selection module receives a data channel control signal and result data returned by the SoC circuit, and selects target data from the pulse waveform data and the result data according to the data channel control signal;

The digital algorithm module is connected with the selection module; the digital algorithm module is used for extracting amplitude information and time information of the target data and transmitting the amplitude information and the time information to the SoC circuit.

4. The digital nuclear pulse signal processor employing a neural network processor architecture of claim 3, wherein the FPGA circuit further comprises an output interface;

the output interface is connected with the digital algorithm module; the output interface is used for outputting the amplitude information and the time information of the target data.

5. The digital nuclear pulse signal processor employing a neural network processor architecture according to claim 4, wherein the output interface is a USB3.0 interface.

6. The digital nuclear pulse signal processor employing a neural network processor architecture of claim 1, wherein the SoC circuit further comprises a CPU processor;

The CPU processor is respectively connected with the NPU processor and the FPGA circuit; the CPU processor is used for transmitting the result data to the FPGA circuit, receiving the amplitude information and the time information, receiving the position information and the case information, and storing the position information, the case information, the amplitude information and the time information.

7. The digital nuclear pulse signal processor employing a neural network processor architecture of claim 6, wherein the SoC circuit further comprises an output module;

The output module is connected with the CPU processor; the output module is used for outputting the position information, the case information, the amplitude information and the time information.

8. The digital nuclear pulse signal processor employing a neural network processor architecture according to claim 7, wherein the output module comprises an ethernet interface and a USB3.0 interface; the Ethernet interface and the USB3.0 interface are respectively connected with the CPU processor.