CN2781396Y

CN2781396Y - Nuclear signal collecting and buffer storage

Info

Publication number: CN2781396Y
Application number: CN 200520008808
Authority: CN
Inventors: 林延畅; 葛良全; 姜海静; 赖万昌; 程锋
Original assignee: Chengdu Univeristy of Technology
Current assignee: Chengdu Univeristy of Technology
Priority date: 2005-03-18
Filing date: 2005-03-18
Publication date: 2006-05-17
Anticipated expiration: 2015-03-18

Abstract

The utility model relates to a collecting buffer memory for a nuclear signal, which is mainly composed of a linear gate circuit, a peak-holding circuit, an ADC sampling circuit, a micro-control circuit, an RS232 interface circuit, a data memory, a data bus thereof and a low level discriminator. The utility model adopts a three-line high-speed SPI bus as a passage for data acquisition and buffer storage of the complete set of signal collectors, adopts a ferro-electric memory FRAM as a buffer memory for data, and adopts a microcontroller, and thus the utility model can be corrected by a combining software with internal timing in a dead time mode. The device which adopts the SPI bus has few pins and small size, and the expanding circuits of an external timing counter can be reduced. The benefit which is brought by that data lines and control lines are reduced is that a microcontroller which has fewer pins and smaller size can be adopted. Therefore, the utility model can increase the integration of the circuits of a nuclear signal collector, reducing connecting lines and size, and realizing the microminiaturized and embedded design of the nuclear signal collector.

Description

Nuclear signal is gathered and buffer

Technical field

The utility model relates to technical field of electronic equipment, relates in particular to nuclear signal collection and the buffer that use in nuclear electronics and Detection Techniques field.

Background technology

In fields such as environmental activity detection, oil geology well logging, ore body, celestial body live element content xrf analysis, be widely used based on gamma energy spectrometer, the X luminoscope of multiple tracks energy spectrum analysis technology.The nuclear signal collector is the core component of all kinds of microcomputer spectral measurement analysers.

The principle of microcomputer spectral measurement analyser is basic identical: radiation detector and prime amplifier are converted to voltage pulse signal (being nuclear signal) with different-energy incident ray or particle flux, the amplitude of potential pulse is directly proportional with the energy of incident ray or particle, and the pulsimeter digit rate is relevant with the intensity of ray or particle.The nuclear signal collector is pressed amplitude digitizing (can pass through the technical scheme realization of " peak value of pulse detection, peak value sampling keep and the A/D conversion ") with nuclear signal, thus acquisition energy-counting rate curve (being that differential is composed) data.The differential spectrum that signal picker obtains is for further processing by microcomputer (data data processing unit) again, draws the content or the radiation intensity of element to be measured (comprising radioactive nuclide).

Because nuclear signal occurs having randomness, and signal pulse is narrow, generally has only 1 * 10 ^-7Second is to 1 * 10 ^-6Second, therefore require the nuclear signal collector must possess wide frequency characteristic and higher picking rate.Simultaneously, for fear of and microcomputer between frequent exchanges data underspeed, signal picker generally is with buffer.Collector generally carries microcontroller, is used for measuring timing, circuit sequence control and exchanges data control.

In order to ensure the speed of signals collecting and metadata cache, between signal acquisition controller and the A/D transducer, adopt parallel (Parallel) interface of scale-of-two to link to each other between signal acquisition controller and the data buffer.Data buffer adopts static state or dynamic RAM (SRAM or DRAM).In addition, in order to realize " dead time " (the dead time: refer to finish single nuclear pulse signal and handle the time that takies, if there is pulse signal to arrive in this time again, system can not handle simultaneously and causes with Louing and count) calibration function, generally adopt external integrated timer conter timing circuit.

A/D transducer, SRAM or the DRAAM of parallel interface and data line, the control line of timer conter are many, and pin is many, and volume is big.Therefore, adopting the Circuits System characteristics of this scheme is that line is many, integrated level is lower.Shortcoming such as have that volume is big, reliability and antijamming capability are lower.

The utility model content

In view of above-mentioned existing in prior technology problem, the purpose of this utility model provides a kind of nuclear signal collection and buffer, can improve the circuit level of nuclear signal collector, reduces line, reduce volume, realize microminiaturization, the embedded design of nuclear signal collector.

The purpose of this utility model is achieved through the following technical solutions:

A kind of nuclear signal collection and buffer comprise linear gate, peak holding circuit, ADC sample circuit, micro-control circuit, RS232 interface circuit, data-carrier store and data bus thereof; Linear gate connects input end and peak holding circuit, and peak holding circuit connects the ADC sample circuit, and micro-control circuit connects linear gate, peak holding circuit, ADC sample circuit, data-carrier store and RS232 interface circuit; Micro-control circuit links to each other with data-carrier store with the ADC sample circuit by data bus.

Described data-carrier store adopts ferroelectric memory FRAM.

Described RS232 interface circuit can connect main control computer.

Described peak holding circuit also is connected to the low level discriminator.

It is MAX1062 that described ADC sample circuit adopts chip.

It is a microcontroller MCU able to programme that described micro-control circuit adopts chip.

The chip model of described microcontroller MCU able to programme is AT89C2051.

It is FM25640 that described ferroelectric memory adopts chip.

The technical scheme that provides by above-mentioned the utility model as can be seen, the utility model mainly is made up of linear gate, peak holding circuit, ADC sample circuit, micro-control circuit, RS232 interface circuit, data-carrier store and data bus thereof; Also comprise the low level discriminator.Owing to adopted three-way high speed SPI bus to obtain passage with buffer memory as the data of a whole set of signal picker, adopt ferroelectric memory FRAM as data buffer, and use microcontroller, can proofread and correct in conjunction with software " dead time " by internal timing.The device pin of employing spi bus is few, volume is little, can reduce external definition counter expanded circuit again.Reduce benefit that data line, control line bring and be can select for use pin still less, microcontroller that volume is littler.Therefore, can improve the circuit level of nuclear signal collector, reduce line, reduce volume.Realize microminiaturization, the embedded design of nuclear signal collector.

Description of drawings

Fig. 1 is a schematic block circuit diagram of the present utility model;

Fig. 2 is circuit theory diagrams of the present utility model.

Embodiment

The specific embodiment of nuclear signal collection described in the utility model and buffer as shown in Figure 1, a kind of nuclear signal collection and buffer comprise linear gate, peak holding circuit, ADC sample circuit, micro-control circuit, RS232 interface circuit, data-carrier store and data bus thereof.Linear gate connects input end and peak holding circuit, and peak holding circuit connects the ADC sample circuit, and micro-control circuit connects linear gate peak holding circuit, ADC sample circuit, data-carrier store and RS232 interface circuit; Micro-control circuit links to each other with data-carrier store with the ADC sample circuit by data bus.

In MCA (multichannel analyzer, i.e. multiple tracks nuclear signal collector) ready state, the nuclear pulse enters peak holding circuit through linear gate circuit, and peak impulse voltage is sampled quantification at the ADC sample circuit.It is MAX1062 that the ADC sample circuit here adopts chip.Micro-control circuit reads the result of ADC sample circuit sample quantization, and location, corresponding road counter is added 1, and the multiple tracks measurement result is temporary in the data-carrier store, and data-carrier store adopts ferroelectric memory, and ferroelectric memory chip model is FM25640.The RS232 interface circuit can connect main control computer.Main control computer sends the beginning analysis instruction by the RS232 interface to MCA, and receives the multi-channel analysis data from MCA.

Above-mentioned linear gate also is connected to the low level discriminator, is used to stop low spoke degree electronics noise to enter analyzer.

It is a MCU able to programme that above-mentioned micro-control circuit adopts chip.Be specially AT89C2051.

Owing to adopted three-way high speed SPI bus to obtain passage with buffer memory, adopted ferroelectric memory (FRAM) as data-carrier store, and can use the microcontroller internal timing and proofread and correct in conjunction with software " dead time " as the data of a whole set of signal picker.

The circuit structure of nuclear signal collection described in the utility model and buffer is as shown in Figure 2:

U1 is the RS232 interface circuit; U2 comprises peak holding circuit, linear gate and low level discriminator; U3 is a micro-control circuit; U4 is the ADC sample circuit; U5 is ferroelectric memory (FRAM).Data bus can be divided into two groups of SPI_1 and SPI_2.

The Tout mouth of U1 and Rin mouth connect the RS232 interface of main control computer; The RXD mouth of U1 connects P3.0 (RXD) pin of U3, and the TXD mouth of U1 connects P3.1 (TXD) pin of U3.

The Vin interface of U2 connects input end; The INT interface of U2 connects P3.2 (INTO) pin of U3, and the RST interface of U2 connects P3.3 (INT1) pin of U3; The Vout interface of U2 connects the AIN interface of U4 by a resistance in series.

The P1.5 of U3 (CS) pin connects the CS interface of U4 by data bus SPI_1; The P1.6 of U3 (SCLK) pin connects the SCLK interface of U4 by data bus SPI_1; The P1.7 of U3 (DOUT) pin connects the DOUT interface of U4 by data bus SPI_1.The P1.4 of U3 (SO) pin connects the SO interface of U5 by data bus SPI_2; The P1.3 of U3 (MCS) pin connects the CS interface of U5 by data bus SPI_2; The P1.2 of U3 (SCK) pin connects the SCK interface of U5 by data bus SPI_2; The P3.7 of U3 (SI) pin connects the SI interface of U5 by data bus SPI_2.The pin that other of U3 do not mentioned connects by the conventional connection of this chip.

The interface that other of U4 do not mentioned connects by the conventional connection of this chip.

The interface that other of U5 do not mentioned connects by the conventional connection of this chip.

The physical circuit of U1 is conventional RS232 interface circuit.

Peak holding circuit among the U2, linear gate and low level discriminator circuit are custom circuit.

The course of work of circuit is as follows:

1, after the opening power, nuclear signal collection and buffer enter holding state, wait for the analysis instruction of main control computer.

2, computing machine sends the beginning analysis instruction, and command signal is received by U3 after being transformed to Transistor-Transistor Logic level by U1.U3 control U5 empties the data of all storage unit.U3 sends the RST signal U2 that resets, and starts timer internal.Nuclear signal collection and buffer enter duty.

3, pulse enters U2, and U2 keeps peak value of pulse and sends the INT look-at-me to U3.After the look-at-me of U3 response U2, suspend regularly (playing the coincidence correction effect), and control U4 work, obtain the respective value of peak impulse voltage.U3 reads the count value in corresponding road among the U5 according to this magnitude of voltage, adds " 1 " back returning and deposits.Finish the analysis of a pulse.Again send reset signal to U2, start timer internal, wait for the analysis of next pulse, finish until Measuring Time.

4, the time finishes, and U3 reads data among the U5, sends to main control computer by U1.Nuclear signal collection and buffer enter holding state, wait for main control computer analysis instruction next time.

The above; it only is the preferable embodiment of the utility model; but protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the variation that can expect easily or replacement all should be encompassed within the protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with the protection domain of claim.

Claims

1, a kind of nuclear signal collection and buffer is characterized in that, comprise linear gate, peak holding circuit, ADC sample circuit, micro-control circuit, RS232 interface circuit, data-carrier store and data bus thereof; Linear gate connects input end and peak holding circuit, and peak holding circuit connects the ADC sample circuit, and micro-control circuit connects linear gate, peak holding circuit, ADC sample circuit, data-carrier store and RS232 interface circuit; Micro-control circuit links to each other with data-carrier store with the ADC sample circuit by data bus.

2, nuclear signal collection according to claim 1 and buffer is characterized in that, described data-carrier store adopts ferroelectric memory.

3, nuclear signal collection according to claim 1 and 2 and buffer is characterized in that, described RS232 interface circuit can connect main control computer.

4, nuclear signal collection according to claim 1 and 2 and buffer is characterized in that, described peak holding circuit also is connected to the low level discriminator.

5, nuclear signal collection according to claim 1 and 2 and buffer is characterized in that, it is MAX1062 that described ADC sample circuit adopts chip.

6, nuclear signal collection according to claim 1 and 2 and buffer is characterized in that, it is a microcontroller MCU able to programme that described micro-control circuit adopts chip.

7, nuclear signal collection according to claim 6 and buffer is characterized in that, the chip model of described microcontroller MCU able to programme is AT89C2051.

8, nuclear signal collection according to claim 1 and 2 and buffer is characterized in that, it is FM25640 that described ferroelectric memory adopts chip.