CN117956855A - Display substrate and display device - Google Patents

Abstract

The present disclosure provides a display substrate and a display device, including: the second area of the substrate comprises a flip chip film area, a fan-out area and a flip chip film corner area; the first terminal group and the second terminal group are arranged in the flip chip film region; a GOA circuit; a fan-out wiring; a plurality of PLG wires, wherein one part of the PLG wires is distributed in the first area and is electrically connected to the GOA circuit, and the other part of the PLG wires passes through the corner area of the flip chip film and is electrically connected to the output terminal of the second terminal group; the first terminal group has a first pitch P1 between two adjacent output terminals, the second terminal group has a second pitch P2 between two adjacent output terminals, the first pitch P1 is unequal to the second pitch P2, and the fan-out area is configured to be a target pattern, so that the ratio of the area of the corner area of the flip chip film to the area of the fan-out area is greater than or equal to 1:4. the display substrate and the display device can reduce PLG wiring temperature.

Description

Display substrate and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display substrate and a display device.

Background

In the related art, high PPI (Pixels Per Inch, pixel density units), high frequency narrow frame products are being aimed at showing the trend of product development. However, while meeting the high specification requirements, the product temperature also rises, and especially, the high temperature in the area where the wires such as PLG (Propel Link Gate, connected gate) wires are dense leads to many defects.

Disclosure of Invention

The embodiment of the disclosure provides a display substrate and a display device, which can improve the quality of display products.

The technical scheme provided by the embodiment of the disclosure is as follows:

In a first aspect, an embodiment of the present disclosure provides a display substrate, including:

the substrate comprises a display area and a peripheral area, wherein the peripheral area comprises a first area and a second area, the second area comprises a flip-chip film area, a fan-out area and a flip-chip film corner area, the fan-out area is positioned at one side, far away from the display area, of the flip-chip film area along a first direction pointing to the display area from the second area, and the flip-chip film corner area is an area formed by encircling edges of the flip-chip film area and the fan-out area;

The flip chip film unit comprises a first terminal group and a second terminal group which are arranged in the flip chip film region, wherein the first terminal group and the second terminal group comprise a plurality of output terminals which are arranged at intervals;

The GOA circuit is arranged in the first area;

a fan-out wiring which is arranged in the fan-out area and is connected to the output terminal of the first terminal group;

A plurality of PLG wires, one part of which is distributed in the first area and is electrically connected to the GOA circuit, and the other part of which passes through the corner area of the flip chip film and is electrically connected to the output terminal of the second terminal group;

and a first interval is arranged between two adjacent output terminals in the first terminal group, a second interval is arranged between two adjacent output terminals in the second terminal group, the first interval is unequal to the second interval, and the fan-out area can be formed into a target pattern, so that the ratio of the area of the corner area of the flip chip film to the area of the fan-out area is greater than or equal to 1:4.

Illustratively, the ratio of the area of the corner region of the flip chip film to the area of the fan-out region is 1:4-1: 2.

The portion of the PLG trace disposed in the corner region of the flip chip film includes a first trace portion and a second trace portion, where the first trace portion extends along the first direction and is connected to the second terminal group, the second trace portion intersects with the first trace portion, and the intersection is formed as a trace bending portion, and a ratio of a line width of the second trace portion to a line width of the first trace portion ranges from 1:2 to 1:6.

The fan-out area includes a first sub-wiring area and a second sub-wiring area, wherein the second sub-wiring area is located between the first sub-wiring area and the display area along the first direction, the area of the second sub-wiring area gradually increases from one side close to the first sub-wiring area to one side close to the display area, and a fan-out inflection point is formed at the edge transition of the first sub-wiring area and the second sub-wiring area; in the first direction, a distance between the fan-out inflection point and the flip chip film region is greater than a first threshold.

Illustratively, the first threshold is greater than or equal to 50 microns, the first pitch is 14-20 microns, the second pitch is 20-14 microns, the line width of the second trace portion is 25-100 microns, and the first pitch is greater than the second pitch.

The fan-out area includes a first sub-wiring area and a second sub-wiring area, wherein the second sub-wiring area is located between the first sub-wiring area and the display area along the first direction, the area of the second sub-wiring area gradually increases from one side close to the first sub-wiring area to one side close to the display area, and a fan-out inflection point is formed at the edge transition of the first sub-wiring area and the second sub-wiring area; wherein a width of the first sub-wiring region is smaller than a second threshold in a second direction perpendicular to the first direction.

The first pitch is 14-20 microns, the second pitch is 20-14 microns, the line width of the second wiring portion is 25-100 microns, and the first pitch is smaller than the second pitch.

Illustratively, the second terminal set is located on one side of the first terminal set in a second direction perpendicular to the first direction; the output terminals of the second terminal group comprise a first end and a second end which are oppositely arranged along the first direction, wherein the first end is closer to the display area relative to the second end, and the first end is offset towards the direction close to the first terminal group along the second direction relative to the second end, so that the output terminals in the second terminal group are obliquely arranged relative to the first direction, and the second direction is perpendicular to the first direction; and in the second direction, the second terminal group is directed from a side close to the first terminal group to a side far from the first terminal group, and the interval between the output terminals is gradually increased.

Illustratively, the minimum pitch between the output terminals in the second terminal set is 15 microns and the maximum pitch is 30.6 microns.

Illustratively, the second terminal set includes a first subunit and a second subunit respectively located on opposite sides of the first terminal set in a second direction, the second direction being perpendicular to the first direction; wherein the output terminals in the first and second sub-units are symmetrically distributed about a midpoint of the first terminal group in the second direction.

In a second aspect, embodiments of the present disclosure provide a display device including the display substrate as described above.

The beneficial effects brought by the embodiment of the disclosure are as follows:

In the display substrate and the display device provided in the embodiments of the present disclosure, in a peripheral area of the display substrate, a first area is provided with a GOA circuit, a second area is provided with a flip chip thin film area, a GOA signal is transmitted between the flip chip thin film area and the GOA circuit through a PLG wiring, a fan-out area is further provided in the second area, and the PLG wiring is arranged in a flip chip thin film corner area formed by surrounding edges of the flip chip thin film area and the fan-out area; the flip chip film region comprises a first terminal group connected with the fan-out wiring of the fan-out region and a second terminal group connected with the PLG wiring, wherein a first interval is arranged between two adjacent output terminals in the first terminal group, a second interval is arranged between two adjacent output terminals in the second terminal group, the first interval is unequal to the second interval, and the flip chip film region is configured to enable the fan-out region to be formed into a target pattern, so that the area ratio of the corner region of the flip chip film to the fan-out region is larger than or equal to 1:4.

In the above scheme, the first pitch P1 between the adjacent output terminals in the first terminal group and the second pitch between the adjacent output terminals in the second terminal group are unequal, and the fan-out area is configured to be capable of being formed into a target pattern, so that the area ratio of the flip-chip thin film corner area to the fan-out area is greater than or equal to 1:4, and therefore, by improving the pitch of the output terminals in the flip-chip thin film unit, the space of the flip-chip thin film corner area can be increased by limiting the pattern of the fan-out area, so that the area ratio of the flip-chip thin film corner area in the second area is increased, the wiring space of the PLG wiring in the flip-chip thin film corner area is released, the wiring line width of the PLG wiring in the flip-chip thin film corner area can be widened, the wiring unit resistance is reduced, and the heating temperature of the flip-chip thin film corner area is reduced.

Drawings

FIG. 1 is a schematic diagram showing a position of a LG trace temperature in a display substrate according to the related art;

Fig. 2 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure;

Fig. 3 is an enlarged view showing a partial structure of a dotted line box S in fig. 2;

FIG. 4 is a schematic diagram showing the structure of a display substrate according to a first and a second set of embodiments of the present disclosure;

Fig. 5 is a schematic diagram showing an arrangement structure of output terminals in a flip-chip thin film unit in a display substrate according to a first set of embodiments and a second set of embodiments of the present disclosure;

fig. 6 is a schematic structural diagram of a display substrate according to a first set of embodiments and a third set of embodiments of the present disclosure;

Fig. 7 is a schematic diagram showing an arrangement structure of output terminals in a flip-chip thin film unit in a display substrate according to a first embodiment and a third embodiment of the disclosure;

fig. 8 is a schematic diagram showing an arrangement structure of output terminals in a flip-chip thin film unit of a display substrate according to another embodiment of the disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

Before explaining the display substrate and the display device provided in the embodiments of the present disclosure in detail, the following description is made on related art:

With the development of display technology, display substrates are increasingly developed toward high integration and low cost. The array substrate row driving (GA Dricer on Array, GOA) technology integrates a TFT (Thin Film Transistor ) gate driving circuit on an array substrate of a display panel to form scanning driving of the display panel, so that wiring space of a binding (Bonding) area and a Fanout (Fanout) area of a gate Integrated Circuit (IC) can be omitted, product cost can be reduced in two aspects of material cost and manufacturing process, and the display panel can be designed in a two-sided symmetrical and narrow-frame attractive manner.

With the increasing of the product size, the increasing of the refresh frequency and the increasing of the resolution, the increasing of the number of Clock signal lines (CLK) connected with the gate driving circuit, and the limited space of the patterned traces (PATTERNED LINE on Glass, PLG) on the substrate between the Chip On Film (COF) and the GOA circuit, the large number of CLK traces are at the dense positions of the traces, the width of the traces is narrow, the current is rapidly increased, the heat is easily accumulated, the PLG trace temperature is too high, thereby affecting the high temperature and humidity reliability of the whole GOA circuit, and even generating defects such as burnt POL (polarizer), panel corner blackening, etc. In order to prevent the above-mentioned adverse phenomena, it is very important to control PLG routing temperature.

The inventor of the present application found through research that the position with the highest PLG routing temperature mainly comprises the following two parts: one is the COF corner region as shown by the dashed box A1 in fig. 1; the other is the Panel corner region as indicated by the dashed box A2 in fig. 1. Tests on PLG temperature profiles have found that COF corner regions are typically above 50 ℃ with a high risk, while Panel corner regions are at a lower temperature with a slightly lower risk.

One of the reasons why the temperature of COF corner regions is higher is that: as shown in fig. 1, a GOF corner region is located on a side close to the display region above the output terminal (lead) in the COF, a plurality of PLG traces 1 are disposed at the GOF corner region, one end of the PLG trace 1 is connected to the output terminal of the COF, and the periphery of the PLG trace 1 is surrounded by the fan-out region (Fanout). The PLG trace 1 laid in the corner region of the GOF has a smaller width and a maximum unit resistance due to the distance and the size of the included angle between the fan-out region and the output terminal of the COF, Q represents heat, I represents current, R represents resistance, and it is known that the PLG trace at the corner region of the GOF has serious heat generation and a high temperature.

Based on the above, in order to improve the quality of the display substrate, the embodiment of the application provides a display substrate and a display device, which can reduce the temperature at the corner region of the flip chip film.

The display substrate and the display device provided by the embodiments of the application will be described in detail below with reference to the accompanying drawings.

The display substrate may be applied as an LCD (Liquid CRYSTAL DISPLAY), an electroluminescent display substrate, or a photoluminescent display substrate. In the case where the display substrate is an electroluminescent display substrate, the electroluminescent display substrate may be an OLED (organic light-Emitting Diode) or a QLED (Quantum Dot Light EmittingDiodes, quantum dot electroluminescent display substrate). In the case where the display substrate is a photoluminescent display substrate, the photoluminescent display substrate may be a quantum dot photoluminescent display substrate.

Fig. 2 is a schematic diagram of a display substrate provided in an embodiment of the disclosure, where fig. 2 only illustrates a part of the structure of a peripheral area of the display substrate, and reference may be made to related art for a pixel structure of a display area of the display substrate, etc., which will not be described in detail herein.

As shown in fig. 2 and 3, a display substrate provided in an embodiment of the present disclosure includes:

A substrate board 100, wherein the substrate board 100 includes a display area AA and a peripheral area B, the peripheral area B includes a first area B1 and a second area B2, the second area B2 includes a flip chip film area (COF) B21, a fan-out area (Fanout) B22, and a flip chip film corner area B23, the fan-out area B22 is located at a side of the flip chip film area B21 away from the display area AA along a first direction X from the second area B2 toward the display area AA, and the flip chip film corner area B23 is located at an area surrounded by edges of the flip chip film area B21 and the fan-out area B22;

A flip chip unit 200, where the flip chip unit 200 includes a first terminal group 210 and a second terminal group 220 disposed in the flip chip area B21, and each of the first terminal group 210 and the second terminal group 220 includes a plurality of output terminals (COF lead) arranged at intervals, and for convenience of distinction, the output terminal of the first terminal group 210 is denoted by 211, and the output terminal of the second terminal group is denoted by 221;

a GOA circuit 300, wherein the GOA circuit 300 is disposed in the first region B1;

fan-out wirings (not shown) disposed in the fan-out area B22 and connected to the output terminals of the first terminal group 210;

A plurality of PLG traces 500, wherein one portion of the PLG traces 500 is disposed in the first region B1 and electrically connected to the GOA circuit 300, and the other portion passes through the flip chip corner region B23 and is electrically connected to the output terminals of the second terminal group 220; wherein,

A first pitch P1 is provided between two adjacent output terminals in the first terminal group 210;

a second pitch P2 is provided between two adjacent output terminals in the second terminal group 220;

The first pitch P1 and the second pitch P2 are unequal and configured to enable the fan-out region B22 to be formed into a target pattern such that the ratio of the area of the flip chip thin film corner region B23 to the area of the fan-out region B22 is greater than or equal to 1:4.

It should be noted that the fan-out trace may be led out from the display area AA and connected to the output terminal corresponding to the first terminal group 210.

Illustratively, the first terminal set 210 may be configured to convey a Source signal (Source) to the display area AA via at least a portion of the fan-out trace, and the first terminal set 210 is a Source signal terminal set. The second terminal set 220 may transmit a GOA signal to the GOA circuit 300 via the PLG trace 500.

For example, the GOA signal lines include a clock signal CLK, a frame start signal STV, a low level signal VGL, a high level signal VGH, a positive power supply voltage signal VDD, a negative power supply voltage signal VSS, and the like. The PLG trace 500 may include a CLK signal line, an STV signal line, a VGL signal line, a VGH signal line, a VDD signal line, a VSS signal line, and the like.

In the related art, the output terminals in the COF are configured to be arranged at equal intervals, the output terminals connected by the PLG traces are equal to the output terminals connected by the fan-out traces, and when the wires in the fan-out area and the COF corner area are routed, the output terminals are limited to the wires in the fan-out area, the occupied area of the fan-out area is larger, the pattern of the fan-out area is not easy to improve, the occupied area of the COF corner area can only be reduced, and therefore the PLG traces at the corner area of the GOF generate heat seriously.

In the display substrate provided by the embodiment of the application, the first pitch P1 between the adjacent output terminals in the first terminal group 210 and the second pitch P2 between the adjacent output terminals in the second terminal group 220 are designed to be unequal, in other words, the pitches of the output terminals of the first terminal group 210 and the second terminal group 220 are adjusted so that the pitches are unequal, and the fan-out area B22 is formed into a target pattern by changing the pitches of the output terminals in combination with the actual structure, so that the area ratio of the flip-chip film corner area B23 to the fan-out area B22 is improved to be greater than or equal to 1:4, thereby increasing the space of the flip-chip film corner area B23, that is, the wiring space of the PLG wiring 500 in the flip-chip film corner area B23 is released, so that the wiring line width of the PLG wiring 500 in the flip-chip film corner area B23 can be widened, the wiring unit resistance is reduced, and the heating temperature of the flip-chip film corner area B23 is reduced.

For different types of products, the product structure is different, the ratio of the areas of the fan-out area and the corner area of the flip chip film can be different by improving the first interval and the second interval, and the ratio of the areas of the corner area of the flip chip film to the fan-out area can be in the range of 1:4-1: 2.

For example, in one embodiment, the ratio of the area of the flip chip thin film corner region to the fan-out region is 1:4; in one embodiment, the ratio of the area of the flip chip thin film corner region to the fan-out region is 1:3, a step of; in one embodiment, the ratio of the area of the flip chip thin film corner region to the fan-out region is 1:2.

Specifically, in one embodiment, for a 75 inch 8K display product, by adjusting and improving the first pitch and the second pitch, the ratio of the area of the corner region of the flip chip film to the area of the fan-out region can be 26%; in another embodiment, for a 43 inch FHD (full high definition screen) display product, a ratio of 38% of the area of the flip chip corner area to the fan-out area can be achieved by modifying the first pitch to the second pitch.

As shown in fig. 4 (B), the portion of the PLG trace 500 disposed in the corner region B23 of the flip chip film includes a first trace portion 510 and a second trace portion 520, the first trace portion 510 extends along the first direction X and is connected to the second terminal group 220, and the second trace portion 520 intersects with the first trace portion 510 and forms a trace bending portion at the intersection.

In the embodiment of the disclosure, by changing the output terminal pitches of the first terminal group 210 and the second terminal group 220, the ratio of the line widths of the second wire trace portion 520 and the first wire trace portion 510 may be 1: 2-1:6. In the related art, the ratio of the line widths of the second trace portion 520 to the first trace portion 510 is only less than 1:2, which is limited by the distance and the included angle between the fan-out area B22 and the output terminal of the COF, and it is apparent that the display substrate provided by the embodiment of the application can increase the line width of the second trace portion 520 of the PLG trace 500 and reduce the heating temperature of the PLG trace 500.

For a display product, the design size of the second area B2 is already preset, in other words, the total space of the second area B2 is constant. Limited by the total space and product structure of the second region B2, in some embodiments, the output terminal pitch in the first terminal set 210 and the second terminal set 220 is adjusted to adjust the pattern of the fan-out region B22 to release more space for the Chip On Film (COF) corner region without increasing the space occupied by the COF unit in the second direction.

Specifically, in some embodiments of the present disclosure, the purpose of releasing more space for the COF corner region may be achieved by widening the output terminal pitch in the first terminal group 210, that is, increasing the first pitch P1, without increasing the space occupied by the Chip On Film (COF) unit in the second direction.

In some exemplary embodiments, referring to the drawings, the fan-out area B22 includes a first sub-wiring area B221 and a second sub-wiring area B222, wherein, along the first direction X, the second sub-wiring area B222 is located between the first sub-wiring area B221 and the display area AA, and the area of the second sub-wiring area B222 increases gradually from the side near the first sub-wiring area B221 to the side near the display area AA, and a fan-out inflection point C is formed at the edge transition of the first sub-wiring area B221 and the second sub-wiring area B222.

By increasing the first pitch P1 between the output terminals in the first terminal group 210, the purpose of reducing the fanout inflection point C in the fanout area B22 is achieved, so as to increase the distance between the output terminals and the fanout inflection point C in the second terminal group 220 in the first direction X, and to release more space for the corner region of the flip chip film to perform PLG routing 500.

Fig. 4 (a) is a schematic diagram showing a layout structure of the second region B2 in the display substrate in the first set of embodiments, and fig. 4 (B) is a schematic diagram showing a layout structure of the second region B2 in the display substrate in the second set of embodiments.

The total area of the fan-out area B22 may be equal to the sum of the areas of the first and second sub-wiring areas B221 and B222.

In the first embodiment, as shown in fig. 4 (a), the pitch between the output terminals in the first terminal group 210 is P10, the number of output terminals in the first terminal group 210 is M, the width of the first terminal group 210 in the second direction is L10, and the distance between the fan-out inflection point C of the fan-out area B22 and the flip-chip film area B21 in the first direction X is a first threshold H0.

In the second embodiment, as shown in fig. 4 (B), the pitch between the output terminals in the first terminal group 210 is P11, the number of the output terminals in the first terminal group 210 is M, the width of the first terminal group 210 along the second direction is L11, the distance between the fanout inflection point C of the fanout area B22 and the flip-chip film area B21 is H1, and H1 is greater than the first threshold H0, that is, the fanout inflection point C of the fanout area B22 in the second embodiment is lower than the fanout inflection point C of the fanout area B22 in the first embodiment.

Since the output terminal pitch of the first terminal group 210 is increased, that is, P1 is greater than P10, L11 is greater than L10, and H1 is greater than the first threshold H0, the area of the first sub-wiring region B221 in the second embodiment is necessarily greater than the area of the first sub-wiring region B221 in the first embodiment, so that if the total area of the fan-out regions B22 in the two embodiments is substantially unchanged, the area of the second sub-wiring region B222 in the second embodiment is smaller than the area of the second sub-wiring region B222 in the first embodiment, the fan-out inflection point C in the second embodiment is lowered compared with the fan-out inflection point C in the first embodiment, and the distance between the output terminal and the fan-out inflection point C in the second terminal group 220 is increased in the first direction X, so as to release more space to give the flip-chip film corner region, and at the same time, the total area of the fan-out regions B22 is ensured, so that the wiring space size needs are ensured, and the uniformity of the resistance of the fan-out regions B22 is ensured.

Referring to fig. 4 and fig. 5, in the second embodiment, in the COF corner area, in the case where the number of traces of the PLG trace 500 is the same, since the interval between the output terminal of the second terminal group 220 and the fan-out inflection point C is increased compared with that in the first embodiment, the line width of the second trace portion 520 in the second embodiment may be greater than that of the second trace portion 520 in the first embodiment, so that the trace unit resistance of the COF corner area may be reduced, and the heating temperature may be reduced.

It should be noted that, the specific size of the first pitch P1 may be reasonably selected according to the size and the product structure of the actual product, and the size of the first threshold H0 may also be calculated according to the actual product layout.

The first pitch P1 and the second pitch P2 refer to pitches between two adjacent output terminals.

In some embodiments, the value range of the first pitch P1 may be 14-20 micrometers, the second pitch is 20-14 micrometers, and the line width range of the second routing portion is 25-100 micrometers; the first threshold H0 is greater than or equal to 50 microns and the first pitch is greater than the second pitch.

If the second set of embodiments is to be satisfied, the total width of the first terminal set 210 and the second terminal set 220 along the second direction in the flip-chip thin film region B21 is equal to the total width of the first terminal set 220 along the second direction in the first set of embodiments, and is the preset total width. Then, when the first pitch P1 is 14 to 20 micrometers, the following relationship is satisfied between the second pitch P2 and the first pitch P1:

P2+d2＝(L-(d1+P1)*M)/N(I)；

Wherein L is a preset total width of the first terminal set 210 and the second terminal set 220 in the flip-chip thin film region B21 along a second direction, and the second direction is perpendicular to the first direction X;

d1 is the width of the output terminals in the first terminal group;

d2 is the width of the output terminals in the second terminal group;

m is the number of output terminals in the first terminal group 210;

N is the number of output terminals in the second terminal set 220.

Based on the above formula (I), the specific size of the second pitch P2 can be deduced.

In a specific embodiment, when the value of the first pitch P1 ranges from 14 to 20 micrometers, the first threshold is greater than or equal to 50 micrometers, the value of the second pitch P2 ranges from 20 to 14 micrometers, the line width of the second trace portion 520 ranges from 25 to 100 micrometers, and the first pitch is greater than the second pitch.

Taking the first and second embodiments as examples, the sum of the first pitch P10 and the width d1 of the individual output terminals in the first terminal group in the first embodiment is 35 micrometers, and the width of the first terminal group 210 in the second direction is 33600 micrometers; in the second embodiment, the sum of the first pitch P11 and the width d1 of the individual output terminals in the first terminal group is 32 micrometers, the width of the first terminal group 210 along the second direction is widened to 3494 micrometers, and in the second embodiment, the fan-out inflection point C is shifted by about 50 micrometers along the first direction X toward the side close to the display area AA compared to the fan-out inflection point C in the first embodiment, and at this time, the PLG trace 500 includes 10 CLK signal lines in the first embodiment and the second embodiment, and in the second embodiment, compared to the first embodiment, the line width of the second trace portion 520 of the CLK signal line can be widened by 5 micrometers, the sheet resistance is reduced by 0.12 Ω/mm, and the temperature is reduced by 5 ℃.

It should be understood that the foregoing is merely an example, and in practical applications, the specific values of the first pitch, the second pitch, the first threshold value, and the like are not limited thereto.

In other embodiments of the present disclosure, the purpose of releasing more space for the COF corner region may be achieved by reducing the output terminal pitch in the first terminal group 210, i.e., reducing the first pitch P1, without increasing the space occupied by the Chip On Film (COF) unit in the second direction.

In some exemplary embodiments, referring to fig. 6, the fan-out area B22 includes a first sub-wiring area B221 and a second sub-wiring area B222, wherein, along the first direction X, the second sub-wiring area B222 is located between the first sub-wiring area B221 and the display area AA, and the area of the second sub-wiring area B222 increases gradually from the side near the first sub-wiring area B221 to the side near the display area AA, and a fan-out inflection point C is formed at the edge transition of the first sub-wiring area B221 and the second sub-wiring area B222.

By decreasing the first pitch P1 between the output terminals in the first terminal group 210, the area of the first sub-wiring region B221 may be decreased, that is, the width of the first terminal group 210 in the second direction may be decreased, thereby increasing the width of the second terminal group 220 in the second direction, for the purpose of increasing the area of the corner region of the COF.

Fig. 6 (a) is a schematic layout diagram of the second region B2 in the display substrate in the first embodiment, and fig. 6 (B) is a schematic layout diagram of the second region B2 in the display substrate in the third embodiment.

In the first embodiment, the pitch between the output terminals in the second terminal group 220 is P10, the number of the output terminals in the second terminal group 220 is N, the width of the second terminal group 220 along the second direction is L20, the distance between the fan-out inflection point C of the fan-out area B22 and the flip-chip film area B21 in the first direction X is a first threshold H0, and the width of the first sub-wiring area B221 is a second threshold L10.

In the third embodiment, the pitch between the output terminals in the second terminal group 220 is P22, the number of the output terminals in the second terminal group 220 is N, the width of the second terminal group 220 in the second direction is L22, the distance between the fan-out inflection point C of the fan-out region B22 and the flip-chip film region B21 is H0, and the width of the first sub-wiring region B221 is L12.

Since the output terminal pitch of the second terminal group 220 is reduced, and thus P22 is greater than P20, L12 is smaller than L10, and thus the area of the first sub-wiring region B221 in the second group embodiment is necessarily smaller than that of the first sub-wiring region B221 in the first group embodiment, the width of the COF corner region in the second direction is increased, that is, the layout space of the plurality of PLG wirings 500 of the COF corner region in the second direction is increased, so that the line width of the PLG wirings 500 can be widened.

Referring to fig. 7 and 8, in the third embodiment, in the COF corner region, in the case where the number of traces of the PLG trace 500 is the same, since the width of the first wiring region in the second direction is reduced compared with that in the third embodiment, the line width of the second trace portion 520 in the third embodiment may be greater than that of the second trace portion 520 in the third embodiment, so that the trace unit resistance of the COF corner region may be reduced, and the heat generating temperature may be reduced.

It should be noted that, the specific size of the first interval P1 may be reasonably selected according to the size and the product structure of the actual product, and the size of the second threshold may also be calculated according to the actual product layout.

In some embodiments, the line width of the second pitch P2 may range from 14 to 20 microns.

If the third set of embodiments is to be satisfied, the total width of the first terminal set 210 and the second terminal set 220 along the second direction in the flip-chip thin film region B21 is equal to the total width of the first terminal set 220 along the second direction in the first set of embodiments, and is the preset total width. Then, when the second pitch P2 is 28 to 34 micrometers, the following relationship is satisfied between the second pitch P2 and the first pitch P1:

P2+d2＝(L-(d1+P1)*M)/N(I)；

Wherein L is a preset total width of the first terminal set 210 and the second terminal set 220 in the flip-chip thin film region B21 along a second direction, and the second direction is perpendicular to the first direction X;

d1 is the width of the output terminals in the first terminal group;

d2 is the width of the output terminals in the second terminal group;

m is the number of output terminals in the first terminal group 210;

N is the number of output terminals in the second terminal set 220.

Based on the above formula (I), the specific size of the first pitch P1 can be deduced.

In a specific embodiment, the second terminal set 220 includes a first sub-unit and a second sub-unit respectively located at opposite sides of the first terminal set 210 in a second direction, which is perpendicular to the first direction X; wherein the output terminals in the first and second sub-units are symmetrically distributed about a midpoint of the first terminal group 210 in the second direction.

When the value range of the second interval P2 is 14-20 micrometers, the width L2 of one second subunit along the second direction is 3900+/-600 micrometers; the range of the first pitch P1 is 20-14 microns, the range of the line width of the second trace portion 520 is 25-100 microns, the first pitch P1 is smaller than the second pitch P2, and the range of the second threshold value may be (28-37) x 960.

Taking the third set of embodiments and the third set of embodiments described above as an example, the sum of the widths of the first pitch P20 and the individual output terminals in the first terminal set in the third set of embodiments is 35 micrometers, and the width of the second terminal set 220 in the second direction is 3465 micrometers; in the third embodiment, the width of the second pitch P21 and the width of the single output terminal in the first terminal group are 34 micrometers, the width of the second terminal group 220 along the second direction is widened to 3945 micrometers, and in the third embodiment and the third embodiment, taking the PLG trace 500 as an example, the third embodiment has the effect of obviously reducing the temperature by widening the line width of the second trace portion 520 of the CLK signal line by 2.5 micrometers, reducing the sheet resistance by 0.062 Ω/mm, and reducing the temperature by 2.9 ℃.

It should be understood that the foregoing is merely an example, and in practical applications, the specific values of the first pitch, the second threshold, and the like are not limited thereto.

It should be noted that, in the above embodiment, the purpose of reducing the temperature of the PLG trace 500 at the corner region of the COF may be achieved by increasing the second pitch P2 between the output terminals of the second terminal group 220 or reducing the second pitch P2 between the output terminals of the second terminal group 220.

In practical application, different modes can be selected to achieve the purpose of reducing the temperature of the PLG trace 500 under different product application scenarios.

For example, if the requirement on the uniformity of the resistance of the fan-out area B22 is high, a manner of increasing the first pitch P1 between the output terminals of the second terminal set 220 may be selected, but the requirement on the process accuracy such as patterning is high in this manner; if the resistance uniformity of the fan-out area B22 is not high and the process accuracy requirements such as patterning are relatively low, a manner of reducing the first pitch P1 between the output terminals of the second terminal set 220 may be selected.

In other embodiments of the present disclosure, the second pitch P2 between the adjacent output terminals in the second terminal set 220 may be adjusted by changing the arrangement manner of the output terminals in the second terminal set 220, so as to increase the pitch between the adjacent output terminals in the second terminal set 220, so as to facilitate heat dissipation and reduce the temperature.

Specifically, in some embodiments, as shown in fig. 2 and 8, in a second direction perpendicular to the first direction X, the second terminal set 220 is located on one side of the first terminal set 210; the output terminals of the second terminal group 220 include a first end a and a second end b disposed opposite to each other along the first direction X, wherein the first end a is closer to the display area AA than the second end b, and the first end a is offset from the second end b along the second direction, which is perpendicular to the first direction X, toward the first terminal group 210, so that the output terminals of the second terminal group 220 are disposed obliquely to the first direction X; and in the second direction, the second terminal group 220 is directed from a side close to the first terminal group 210 to a side far from the first terminal group 210, and the interval between the output terminals is gradually increased.

With the above-mentioned configuration, in the second direction, the second terminal group 220 is located at one side of the first terminal group 210, and after the PLG trace 500 is led out from the output terminal of the second terminal group 220, the PLG trace 500 is bent, extended and connected to the GOA circuit 300 in a direction away from the first terminal group 210, so, in the second direction, the distance between any one of the PLG traces 500 and the second terminal group 220 is greater, the trace bending portion of the one trace is greater (i.e., the trace bending portion is closer to the COF region), and therefore, when the second end b of the output terminal of the second terminal group 220 is inclined toward the direction close to the first terminal group 210, and the distance between the output terminals is gradually increased from the side close to the first terminal group 210, compared with the configuration in which the output terminals are arranged in parallel in the first direction X, the distance between the PLG traces 500 is increased, so that the PLG trace 500 is advantageous to reduce the heat dissipation temperature of the PLG trace 500.

In some embodiments, the minimum pitch between the output terminals in the second terminal set 220 is 32 microns and the maximum pitch is 47.6 microns. Under this scheme, PLG trace 500 region scope widens, and the line interval increases, is favorable to the heat dissipation, can further reduce the temperature. It is understood that the value of the pitch between the output terminals in the second terminal group 220 is not limited thereto.

Taking the PLG trace 500 as an example, the second terminal group 220 includes n1 CLK signal lines and n2 other signal lines, the CLK output terminal 2211 correspondingly connected to the CLK signal lines and the other signal output terminals 2222 correspondingly connected to the other signal lines, and in the second direction, the CLK output terminal 2211 may be located at an intermediate position of the other signal output terminals 2222.

By adopting the scheme, the interval between the CLK output terminals can be effectively increased so as to be beneficial to heat dissipation of the CLK output terminals, thereby achieving the purpose of reducing the temperature of the PLG wiring 500.

In some exemplary embodiments, as shown in fig. 2 and 8, the second terminal set 220 includes a first sub-unit 220a and a second sub-unit 220b respectively located at opposite sides of the first terminal set 210 in a second direction, which is perpendicular to the first direction X; wherein the output terminals in the first sub-unit 220a and the second sub-unit 220b are symmetrically distributed about a midpoint of the first terminal group 210 in the second direction, so that the output terminals in the first sub-unit 220a and the second sub-unit 220b are symmetrically arranged in a similar "splay" shape; also, the plurality of output terminals in the first terminal group 210 are arranged at intervals in the direction parallel to the first direction X, which is advantageous in reducing the width of the first terminal group 210 in the second direction to release more space for the second terminal group 220.

In addition, the embodiment of the disclosure also provides a display device, which comprises the display substrate provided by the embodiment of the disclosure. Obviously, the display device provided by the embodiment of the present disclosure also has the beneficial effects brought by the display substrate provided by the embodiment of the present disclosure, and will not be described herein again.

The following points need to be described:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) In the drawings for describing embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced for clarity, i.e., the drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The above is merely a specific embodiment of the disclosure, but the protection scope of the disclosure should not be limited thereto, and the protection scope of the disclosure should be subject to the claims.

Claims (11)

1. A display substrate, comprising:

The substrate comprises a display area and a peripheral area, wherein the peripheral area comprises a first area and a second area, the second area comprises a flip-chip film area, a fan-out area and a flip-chip film corner area, the fan-out area is positioned at one side, far away from the display area, of the flip-chip film area along a first direction pointing to the display area from the second area, and the flip-chip film corner area is an area formed by encircling edges of the flip-chip film area and the fan-out area;

the flip chip film unit comprises a first terminal group and a second terminal group which are arranged in the flip chip film region;

The GOA circuit is arranged in the first area;

A fan-out wiring which is arranged in the fan-out area and is connected to the output terminal of the first terminal group;

a plurality of PLG wires, one part of which is distributed in the first area and is electrically connected to the GOA circuit, and the other part of which passes through the corner area of the flip chip film and is electrically connected to the output terminal of the second terminal group; wherein,

A first interval is arranged between two adjacent output terminals in the first terminal group;

a second interval is arranged between two adjacent output terminals in the second terminal group;

the first pitch is not equal to the second pitch and is configured to enable the fan-out region to be formed into a target pattern such that a ratio of an area of the flip chip thin film corner region to the fan-out region is greater than or equal to 1:4.

2. The display substrate of claim 1, wherein a ratio of areas of the flip-chip thin film corner regions to the fan-out regions is 1: 4-1: 2.

3. The display substrate according to claim 1, wherein the portion of the PLG trace disposed in the corner region of the flip chip film includes a first trace portion and a second trace portion, the first trace portion extends along the first direction and is connected to the second terminal group, the second trace portion intersects with the first trace portion and forms a trace bending portion at an intersection, and a ratio of a line width of the second trace portion to a line width of the first trace portion ranges from 1:2 to 1:6.

4. The display substrate of claim 3, wherein the fan-out region comprises a first sub-wiring region and a second sub-wiring region, wherein along the first direction, the second sub-wiring region is located between the first sub-wiring region and the display region, and the second sub-wiring region gradually increases in area from a side near the first sub-wiring region to a side near the display region, and a fan-out inflection point is formed at an edge transition of the first sub-wiring region and the second sub-wiring region; in the first direction, a distance between the fan-out inflection point and the flip chip film region is greater than a first threshold.

5. The display substrate according to claim 4, wherein the first threshold is greater than or equal to 50 micrometers, the first pitch is 14-20 micrometers, the second pitch is 20-14 micrometers, the line width of the second trace portion is 25-100 micrometers, and the first pitch is greater than the second pitch.

6. The display substrate of claim 3, wherein the fan-out region comprises a first sub-wiring region and a second sub-wiring region, wherein along the first direction, the second sub-wiring region is located between the first sub-wiring region and the display region, and the second sub-wiring region gradually increases in area from a side near the first sub-wiring region to a side near the display region, and a fan-out inflection point is formed at an edge transition of the first sub-wiring region and the second sub-wiring region; wherein a width of the first sub-wiring region is smaller than a second threshold in a second direction perpendicular to the first direction.

7. The display substrate according to claim 6, wherein the first pitch is 20 to 14 micrometers, the second pitch is 14 to 20 micrometers, the line width of the second wiring portion is 25 to 100 micrometers, and the first pitch is smaller than the second pitch.

8. The display substrate according to claim 1, wherein the second terminal group is located on one side of the first terminal group in a second direction perpendicular to the first direction; the output terminals of the second terminal group comprise a first end and a second end which are oppositely arranged along the first direction, wherein the first end is closer to the display area relative to the second end, and the first end is offset towards the direction close to the first terminal group along the second direction relative to the second end, so that the output terminals in the second terminal group are obliquely arranged relative to the first direction, and the second direction is perpendicular to the first direction; and in the second direction, the second terminal group is directed from a side close to the first terminal group to a side far from the first terminal group, and the interval between the output terminals is gradually increased.

9. The display substrate according to claim 7, wherein a pitch between the output terminals in the second terminal group is 15 micrometers at a minimum and 30.6 micrometers at a maximum.

10. The display substrate according to claim 1, wherein the second terminal group includes a first sub-unit and a second sub-unit respectively located on opposite sides of the first terminal group in a second direction, the second direction being perpendicular to the first direction; wherein the output terminals in the first and second sub-units are symmetrically distributed about a midpoint of the first terminal group in the second direction.

11. A display device comprising the display substrate according to any one of claims 1 to 10.