CN117956306A

CN117956306A - Image sensor

Info

Publication number: CN117956306A
Application number: CN202211334337.7A
Authority: CN
Inventors: 胡佳; 周文
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-10-28
Filing date: 2022-10-28
Publication date: 2024-04-30

Abstract

The application discloses an image sensor, which comprises a storage capacitor, a floating diffusion capacitor, a switching transistor, a pixel unit and a reading unit, wherein the storage capacitor is connected with the floating diffusion capacitor; the pixel unit is respectively coupled with the power supply end and the floating diffusion node, and the readout unit is respectively coupled with the column bus, the power supply end and the floating diffusion node; the pixel unit is used for converting the optical signal into signal charge, discharging the charge overflowed from the pixel unit in a first preset proportion to a power supply end, and transmitting the charge which is not discharged to the floating diffusion node; the switch transistor is used for switching on or switching off the connection between the floating diffusion capacitor and the storage capacitor; the readout unit is used for reading the voltage of the floating diffusion node and outputting the pixel signal, and the image sensor can be suitable for higher illumination intensity and improves the dynamic range by discharging part of overflowing charges to the power supply end.

Description

Image sensor

Technical Field

The present application relates to the field of image display, and in particular, to an image sensor.

Background

Image sensors are used for recording and saving pictures, and can be classified into charge coupled device (charge coupled device, CCD) image sensors and complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) image sensors. Among them, a complementary metal oxide semiconductor image sensor (complementary metal oxide semiconductor Image Sensor, CIS) is a functional device that converts an optical image on a photosensitive surface into an electrical signal in proportion to the optical image by using a photoelectric conversion function of the device.

The dynamic range (DYNAMIC RANGE, DR) is one of the key performance parameters of CIS. The method is used for indicating the range of the maximum light intensity signal and the minimum light intensity signal which can be detected by the CIS in the same frame of image at the same time, and the higher the dynamic range is, the clearer the contrast details of the image are, and the more the real image information can be restored. To achieve a high dynamic range, it is necessary to achieve high light but not exposure, i.e. to enable the image sensor to absorb more light and store more electrons. And the larger the capacitance, the greater the number of electrons that can be stored and quantified, the more light that can be absorbed. As the current chip design pursues smaller size, it is difficult to achieve larger capacitance value of the capacitor in the small pixel due to the limitation of area, so how to increase the dynamic range of the image sensor is a problem to be solved.

Disclosure of Invention

The application provides an image sensor which is used for solving the problem of how to improve the dynamic range of the image sensor.

In a first aspect, an embodiment of the present application provides an image sensor, including a storage capacitor, a floating diffusion capacitor, a switching transistor, a pixel unit, and a readout unit; the first end of the switch transistor is coupled with the first end of the storage capacitor, the second end of the switch transistor is coupled with the first end of the floating diffusion capacitor, a floating diffusion node is formed at the coupling position of the switch transistor and the floating diffusion capacitor, the pixel unit is respectively coupled with a power supply end and the floating diffusion node, the reading unit is respectively coupled with a column bus, the power supply end and the floating diffusion node, the second end of the storage capacitor is grounded, and the second end of the floating diffusion capacitor is grounded;

The pixel unit is used for generating signal charges according to the received optical signals; discharging the overflowed charges of the first preset proportion to the power supply end, and transmitting the signal charges which are not discharged to the floating diffusion node; wherein the overflowing electric charge is a signal electric charge overflowing the pixel unit;

the switch transistor is used for switching on or switching off the connection between the floating diffusion capacitor and the storage capacitor;

The readout unit is used for reading the voltage of the floating diffusion node and outputting a pixel signal according to the read voltage.

In practical application, the image sensor is limited by the area of the chip, and the dynamic range of the image sensor cannot be further enlarged by enlarging the area of the storage capacitor.

In one possible embodiment, the pixel unit includes a photodiode, a transfer transistor, and a first transistor; the anode of the photodiode is grounded, the cathode of the photodiode is respectively coupled with the first end of the transmission transistor and the first end of the first transistor, the second end of the transmission transistor is coupled with the floating diffusion node, and the second end of the first transistor is coupled with the power supply end;

the photodiode is used for generating signal charges according to the received optical signals;

The first transistor is used for discharging the overflowing electric charge with the first preset proportion to the power supply end;

the transfer transistor is used for conducting connection between the photodiode and the floating diffusion node and transferring signal charges which are not discharged to the floating diffusion node.

Based on the scheme, the overflow charge is discharged to the power supply end according to the first preset proportion by arranging the first transistor, and the charge overflowing to the storage capacitor is not influenced to be quantized.

In a possible embodiment, the pixel cell further comprises a second transistor; wherein a first end of the second transistor is coupled with a cathode of the photodiode, and a second end of the second transistor is coupled with the storage capacitor;

the second transistor is used for discharging overflowing electric charge with a second preset proportion to the storage capacitor.

Based on the scheme, the second transistor is arranged in the pixel unit to drain the overflowing electric charge with the second preset proportion to the storage capacitor, and the selective overflowing with different proportions can be realized by controlling the gate voltages and the width-to-length ratios of the first transistor and the second transistor, so that good linearity can be kept and accurate quantification of read-out signals can be realized.

In one possible implementation, the storage capacitor is a lateral overflow integrated capacitor.

In one possible implementation, the image sensor further includes a reset transistor, a first terminal of the reset transistor being coupled to the floating diffusion node, and a second terminal of the reset transistor being coupled to the power supply terminal;

The reset transistor is used for resetting the pixel unit, the floating diffusion capacitor and the storage capacitor.

In one possible implementation, the readout unit includes a source follower transistor and a select transistor; wherein a first terminal of the source follower transistor is coupled to a second terminal of the select transistor, a second terminal of the source follower transistor is coupled to the power supply terminal, a control terminal of the source follower transistor is coupled to the floating diffusion node, and a first terminal of the select transistor is coupled to a column bus;

The source electrode following transistor is used for following the voltage of the floating diffusion node;

The selection transistor is used for outputting a pixel signal according to the voltage followed by the source electrode following transistor.

In this possible embodiment, the image sensor further comprises a row driver coupled to the control terminal of the switching transistor, the control terminal of the reset transistor, the control terminal of the selection transistor, and the control terminal of the transfer transistor, respectively;

The row driver is configured to:

when the image sensor is applied to the first illumination intensity, controlling the switching transistor to be conducted in an exposure stage EP 1;

an overflow stage OS1 after the exposure stage EP1, controlling the selection transistor to be turned on so as to enable the reading unit to read an overflow signal;

An overflow reset stage OR1 after the overflow stage OS1, controlling the reset transistor to be turned on so as to enable the reading unit to read an overflow reset signal, and controlling the reset transistor to be turned off after the overflow reset signal is read;

in a reset phase HR1 after the overflow reset phase OR1, controlling the switching transistor to be turned off so as to enable the reading unit to read a first reset signal;

In a switching stage HS1 after the reset stage HR1, controlling the transmission transistor to be turned on so as to enable the reading unit to read a first switching signal, and after the first switching signal is read, controlling the transmission transistor to be turned off;

in a switching stage LS1 after the switching stage HS1, controlling the transmission transistor and the switching transistor to be turned on so as to enable the reading unit to read a second switching signal, and after the second switching signal is read, controlling the transmission transistor to be turned off;

And in a reset stage LR1 after the conversion stage LS1, controlling the reset transistor to be turned on so as to enable the reading unit to read out a second reset signal, and after the second reset signal is read out, controlling the reset transistor to be turned off.

Based on the above scheme, when the image sensor is applied to the first illumination intensity, such as high illumination intensity, the switching transistor is turned on in the exposure stage EP1 to communicate with the floating diffusion node and the storage capacitor, signal charges overflow from the photodiode, in the overflow stage OS1, the switching selection transistor is turned on to start reading out signals, charges which are not discharged by the first transistor are transmitted to the floating diffusion node and the storage capacitor, and then the overflow signals are read out, compared with the voltage loss and image noise problems caused by the switching transistor being turned on again in the overflow stage OS1, the switching transistor is turned on in the exposure stage to eliminate voltage disturbance; resetting the floating diffusion node and the storage capacitor in an overflow reset stage OR1, reading out an overflow reset signal, and reading out a first reset signal in a reset stage HR 1; reading out a first switching signal in a switching phase HS 1; reading out a second switching signal in a switching stage LS 1; in the reset stage LR1, the floating diffusion node and the storage capacitor are reset, and the second reset signal is read out.

In this possible embodiment, the row driver is further adapted to:

When the image sensor is applied to the second illumination intensity, in a reset stage HR2 after an exposure stage EP2, the reset transistor and the switch transistor are controlled to be turned on so that the readout unit reads out a third reset signal, and after the third reset signal is read out, the reset transistor and the switch transistor are controlled to be turned off;

In a switching stage HS2 after the reset stage HR2, controlling the pass transistor to be turned on so as to enable the reading unit to read a third switching signal, and after the third switching signal is read, controlling the pass transistor to be turned off;

in a switching stage LS2 after the switching stage HS2, controlling the switching transistor and the transfer transistor to be turned on so that the readout unit reads out a fourth switching signal, and after reading out the fourth switching signal, controlling the transfer transistor to be turned off;

A reset stage LR2 after the switching stage LS2, controlling the reset transistor to be turned on, reading out a fourth reset signal, and controlling the transfer transistor and the reset transistor to be turned off after reading out the fourth reset signal;

Wherein the first illumination intensity is greater than the second illumination intensity.

Based on the above scheme, when the image sensor is applied to the second illumination intensity, such as the middle illumination intensity, there is no or less overflowing electric charge because the illumination intensity is weaker. The image sensor resets the floating diffusion node and the storage capacitor in a reset stage HR2, and reads out a third reset signal; in the conversion stage HS2, the switching transistor is turned on to transfer charges in the photodiode to the floating diffusion node, and a third conversion signal is read out; in the conversion stage LS2, a switching transistor is turned on, namely the floating diffusion node and the storage capacitor are connected and turned on, so that charges in the photodiode are transferred to the floating diffusion node and the storage capacitor, and a fourth conversion signal is read; in the reset stage LR2, the floating diffusion node and the storage capacitor are reset, and a fourth reset signal is read out.

In this possible embodiment, the row driver is further adapted to:

When the image sensor is applied to the third illumination intensity, in a reset stage HR3 after an exposure stage EP3, controlling the reset transistor and the switch transistor to be turned on so as to enable the reading unit to read out a fifth reset signal, and after the fifth reset signal is read out, controlling the reset transistor and the switch transistor to be turned off;

In a switching stage HS3 after the reset stage HR3, controlling the pass transistor to be turned on so as to enable the readout unit to read out a fifth switching signal, and after the fifth switching signal is read out, controlling the pass transistor to be turned off;

wherein the second illumination intensity is greater than the third illumination intensity.

Based on the above-described scheme, when the image sensor is applied to a third illumination intensity, such as a low illumination intensity, since the illumination intensity is weak, signal charges are accumulated in the photodiode, and there is no overflowing charge. The image sensor resets the floating diffusion node in a reset stage HR3, and reads out a fifth reset signal; in the switching stage HS3, the switching transistor is turned on to transfer the charge in the photodiode to the floating diffusion node, and the fifth switching signal is read out.

In this possible embodiment, the image sensor comprises at least one four-pixel structure, each comprising four pixel units.

Based on the scheme, four pixel units can share the same reset transistor, storage capacitor, switch transistor and floating diffusion capacitor, so that the chip area is further saved, and therefore, the storage capacitor with a larger area can be arranged.

Drawings

Fig. 1 is a schematic structural diagram of an image sensor according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another image sensor according to an embodiment of the present application;

FIG. 3a is a schematic diagram of a control timing diagram according to an embodiment of the present application;

FIG. 3b is a schematic diagram of another control timing provided by an embodiment of the present application;

FIG. 3c is a schematic diagram of another control timing provided by an embodiment of the present application;

FIG. 3d is a schematic diagram of another control timing provided by an embodiment of the present application;

Fig. 4 is a schematic diagram of a four-pixel image sensor according to an embodiment of the present application;

FIG. 5a is a schematic diagram of another control timing provided by an embodiment of the present application;

FIG. 5b is a schematic diagram of another control timing provided by an embodiment of the present application;

FIG. 5c is a schematic diagram of another control timing provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of another four-pixel image sensor according to an embodiment of the present application;

FIG. 7a is a schematic diagram of another control timing provided by an embodiment of the present application;

FIG. 7b is a schematic diagram of another control timing provided by an embodiment of the present application;

FIG. 7c is a schematic diagram of another control timing provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of another four-pixel image sensor according to an embodiment of the present application;

FIG. 9a is a schematic diagram of another control timing provided by an embodiment of the present application;

FIG. 9b is a schematic diagram of another control timing provided by an embodiment of the present application;

FIG. 9c is a schematic diagram of another control timing provided by an embodiment of the present application;

FIG. 10a is a schematic diagram of an image sensor according to an embodiment of the present application;

Fig. 10b is a schematic layout diagram of another image sensor according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.

In order to facilitate understanding of the embodiments of the present application, terms related to the embodiments of the present application will be explained.

1. Transverse overflow integrated capacitor (lateral overflow integration capacitor, LOFIC)

The LOFIC technology is an effective method for improving the dynamic range, and by adding a capacitor in a pixel, the overflowed charges of a Photodiode (PD) are effectively collected, so that the total full well capacity is not limited by the full well capacity of the PD any more, and the problems of the full well capacity and conversion gain are effectively solved.

2. Full well capacity

The full well capacity of an image sensor refers to the maximum number of electrons that can be collected and accommodated by a pixel structure. The large full well capacity can effectively improve the dynamic range of the image sensor. For a responsive image sensor, the maximum saturation light intensity that can be detected corresponds to the full well capacity, and the minimum saturation light intensity corresponds to the image noise electron count, so the dynamic range can also be expressed in terms of the ratio of the full well capacity to the background noise electron count.

3. Conversion Gain (CG)

Conversion gain is the rate at which charge accumulated in the floating diffusion node is converted into voltage, i.e., the magnitude of voltage change caused by one electron at the floating diffusion node, and can be expressed by the ratio of the amount of charge to the node capacitance value, and the conversion gain modes can be generally classified into a high conversion gain (high conversion gain, HCG) mode, a low conversion gain (low conversion gain, LCG) mode, and a dual conversion gain (dual conversion gain, DCG) mode for different illumination intensities.

4. Aspect ratio

The length of the grid in the source-drain direction is denoted as the grid length L, the width of the grid in the vertical direction is denoted as the grid width W, and the width-to-length ratio of the grid is denoted as W/L.

5. Floating diffusion node (floating diffusion FD)

The floating diffusion node refers to a node for reading out an electric signal generated by an optical signal irradiated on the pixel structure.

6. Signal linearity

Signal linearity refers to the degree of stability of signal conversion, which is a linear process in an ideal state. However, the conversion process of the signal charge may have a nonlinear state, such as the charge collection efficiency and the conversion of the signal charge into an output voltage may be nonlinear. In an image sensor, nonlinearity of signal conversion may be caused due to floating diffusion capacitance varying with voltage and nonlinearity of an output amplifier.

It should be appreciated that the terms "first," "second," and the like in embodiments of the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. For example, "first voltage difference", "second voltage difference", "third voltage difference", and "fourth voltage difference" are merely exemplary indications of different voltage differences, and do not mean that the four voltage differences are different in importance or priority.

In addition, it should be understood that "at least one" means one or more and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of (a) or the like" refers to any combination of these items, including any combination of single item(s) or plural items(s), e.g., at least one of a, b, or c, may represent: a, b, c, a and b, a and c, b and c, or a and b and c.

Since the dynamic range (DYNAMIC RANGE, DR) is one of the key performance parameters of a complementary metal oxide semiconductor image sensor (complementary metal oxide semiconductor Image Sensor, CIS). The method is used for indicating the range of the maximum light intensity signal and the minimum light intensity signal which can be detected by the CIS in the same frame of image at the same time, the higher the dynamic range is, the clearer the contrast details of the image are, and the more real image information can be restored, so that how to improve the dynamic range of the image sensor is a problem to be solved at present.

At present, the traditional solution is to increase the capacitance value by enlarging the LOFIC capacitance, i.e. enlarging the area of the capacitor plate, and further increase the number of electrons that can be stored and quantized to increase the dynamic range of the image sensor, but the current chip design pursues smaller size, so that the capacitance in a small pixel is difficult to realize a larger capacitance value due to the limitation of the area.

Based on the above-mentioned problems, an embodiment of the present application provides an image sensor for improving the dynamic range of the image sensor.

Fig. 1 is a schematic structural diagram of an image sensor according to an embodiment of the present application. As shown in fig. 1, the image sensor includes a storage capacitor Cs, a floating diffusion capacitor CF, a switching transistor SGB, a pixel unit 101, and a readout unit 102. The first end of the switch transistor SGB is coupled to the first end of the storage capacitor Cs, the second end of the switch transistor SGB is coupled to the first end of the floating diffusion capacitor, the coupling portion of the switch transistor SGB and the floating diffusion capacitor CF forms a floating diffusion node FD, the pixel unit 101 is coupled to the power supply end VDD and the floating diffusion node FD, the readout unit 102 is coupled to the COLUMN bus COLUMN, the power supply end VDD and the floating diffusion node FD, the second end of the storage capacitor Cs is grounded, and the second end of the floating diffusion capacitor CF is grounded.

In one possible embodiment, the storage capacitance Cs may be a LOFIC capacitance. The LOFIC capacitor is used for effectively collecting overflowing charges, so that the total full well capacity is not limited by the full well capacity of the photodiode PD any more, and the problems of the full well capacity and conversion gain can be effectively solved.

It should be understood that the transistors mentioned in the present application may be P-type transistors or N-type transistors, and the current directions of the source and the drain of the transistors are not limited in the present application, and the P-type transistors are used for convenience of description and are not described in detail below.

In conjunction with the image sensor structure of fig. 1, another image sensor structure according to an embodiment of the present application is shown in fig. 2, where the image sensor further includes a reset transistor RST and a row driver 201, the pixel unit 101 includes a photodiode PD, a transfer transistor TG and a first transistor SO, and the readout unit 102 includes a source transistor SF and a selection transistor SEL.

The anode of the photodiode PD is grounded, the cathode of the photodiode PD is coupled with the first end of the transmission transistor TG and the first end of the first transistor SO respectively, the second end of the transmission transistor TG is coupled with the floating diffusion node FD, and the second end of the first transistor SO is coupled with the power supply end VDD; a first terminal of the reset transistor RST is coupled to the floating diffusion node FD, and a second terminal of the reset transistor RST is coupled to the power supply terminal VDD; a first terminal of the source follower transistor SF is coupled to a second terminal of the selection transistor SEL, a second terminal of the source follower transistor SF is coupled to the power supply terminal VDD, a control terminal of the source follower transistor SF is coupled to the floating diffusion node FD, and a first terminal of the selection transistor SEL is coupled to the COLUMN bus COLUMN; the row driver 201 is coupled to the control terminal of the switching transistor SGB, the control terminal of the reset transistor RST, the control terminal of the selection transistor SEL, and the control terminal of the transfer transistor TG, respectively.

The functions of the constituent elements will be described below with reference to the structure of the image sensor of fig. 1 described above:

A photodiode PD for generating signal charges according to the received optical signal;

the first transistor SO is used for discharging overflowing electric charge with a first preset proportion to the power supply end;

A transfer transistor TG for turning on the connection between the photodiode PD and the floating diffusion node FD, transferring the signal charge that is not discharged to the floating diffusion node FD;

A switching transistor SGB for turning on or off the connection between the floating diffusion capacitor CF and the storage capacitor Cs;

a reset transistor RST for resetting the pixel unit 101, the floating diffusion capacitor CF, that is, the floating diffusion node FD, and the storage capacitor Cs;

a source follower transistor SF for following the voltage of the floating diffusion node FD;

a selection transistor SEL for outputting a pixel signal according to a voltage followed by the source follower transistor SF.

The control timing of the row driver 201 is described in detail below in conjunction with the image sensor structure shown in fig. 2:

In one possible embodiment, when the image sensor is applied to a first illumination intensity, such as a high illumination intensity, the row driver 201 controls the coupled transistors by the control timing shown in fig. 3 a:

The row driver 201 controls the reset transistor RST, the switching transistor SGB and the transfer transistor TG to be turned on for global reset, controls the reset transistor RST, the switching transistor SGB and the transfer transistor TG to be turned off after global reset, and enters an exposure stage EP1 to expose the photodiode PD;

In the overflow stage OS1, the selection transistor SEL is controlled to be turned on, the reading process Readout is started, the switching transistor SGB is controlled to be turned on, and charges which are not discharged by the first transistor SO are transferred to the floating diffusion node FD and the storage capacitor Cs, SO that an overflow signal is read;

In the overflow reset stage OR1, a reset transistor RST is controlled to be turned on, the floating diffusion node FD and the storage capacitor Cs are reset, an overflow reset signal is read out, and after the overflow reset signal is read out, the reset transistor RST is controlled to be turned off; in the reset phase HR1, the control switch transistor SGB is turned off, and the first reset signal is read out;

in the switching stage HS1, the transmission transistor TG is controlled to be turned on, the first switching signal is read out, and after the first switching signal is read out, the transmission transistor TG is controlled to be turned off;

In the switching stage LS1, the transmission transistor TG and the switching transistor SGB are controlled to be turned on, the second switching signal is read out, and after the second switching signal is read out, the transmission transistor TG is controlled to be turned off;

in the reset stage LR1, the reset transistor RST is controlled to be turned on, reset the floating diffusion node FD and the storage capacitor Cs, read out the second reset signal, and after the second reset signal is read out, the select transistor SEL and the reset transistor RST are controlled to be turned off, and the read out process Readout is ended.

Further, as shown in the control timing of fig. 3b, the switching transistor SGB may be turned on in the exposure stage EP1, and the floating diffusion node FD and the storage capacitor Cs are connected, and the signal charges overflow from the photodiode PD;

In the overflow stage OS1, overflows to the floating diffusion node FD and the storage capacitor Cs according to a preset proportion through the first transistor SO;

In an overflow reset phase OR1, resetting the floating diffusion node FD and the storage capacitor Cs, and reading out an overflow reset signal;

in the reset phase HR1, the switching transistor SGB is turned off.

Compared to the voltage loss and image noise caused by turning on the switching transistor SGB again in the overflow stage OS1 in fig. 3a, the voltage disturbance can be eliminated by turning on the switching transistor SGB in the exposure stage, and the problem of similar voltage loss in the present application can refer to the control timing shown in fig. 3b, which will not be described in detail.

In one possible embodiment, when the image sensor is applied to a second illumination intensity, such as a medium illumination intensity, since the illumination intensity is weaker, there is no or less overflow charge, the row driver 201 controls the coupled transistors by the control timing shown in fig. 3 c:

the row driver 201 controls the reset transistor RST, the switching transistor SGB, and the transfer transistor TG to be turned on, performs global reset, and controls the reset transistor RST, the switching transistor SGB, and the transfer transistor TG to be turned off after the global reset;

entering an exposure stage EP2, and exposing the photodiode PD;

In the reset stage HR2, the reset transistor RST and the switching transistor SGB are controlled to be turned on, the floating diffusion node FD and the storage capacitor Cs are reset, the selection transistor SEL is controlled to be turned on, the third reset signal is read out, and after the third reset signal is read out, the reset transistor RST and the switching transistor SGB are controlled to be turned off;

in the switching stage HS2, the transfer transistor TG is controlled to be turned on, the charge in the photodiode PD is transferred to the floating diffusion node FD, the third switching signal is read out, and after the third switching signal is read out, the transfer transistor TG is controlled to be turned off;

In a switching stage LS2 after the switching stage HS2, the switching transistor SGB and the transfer transistor TG are controlled to be turned on, that is, the floating diffusion node FD and the storage capacitor Cs are connected and turned on, so that charges in the photodiode PD are transferred to the floating diffusion node FD and the storage capacitor Cs, a fourth switching signal is read out, and after the fourth switching signal is read out, the transfer transistor TG is controlled to be turned off;

In the reset stage LR2, the reset transistor RST is controlled to be turned on, the fourth reset signal is read out, the transfer transistor TG and the reset transistor RST are controlled to be turned off after the fourth reset signal is read out, and the selection transistor SEL is controlled to be turned off after the signal of the pixel unit 101 is read out, and the read-out process Readout is ended.

In one possible embodiment, when the image sensor is applied to a third illumination intensity, such as a low illumination intensity, since the illumination intensity is weak, the signal charges are accumulated in the photodiode PD, and there is no overflowing charge, the row driver 201 controls the coupled transistors through the control timing shown in fig. 3 d:

entering an exposure stage EP3, and exposing each photodiode PD1-4 in sequence;

taking the Readout process Readout of one pixel cell 101 as an example:

In the reset stage HR3, the reset transistor RST and the switching transistor SGB are controlled to be turned on, the floating diffusion node FD is reset, the fifth reset signal is read out, and after the fifth reset signal is read out, the reset transistor RST and the switching transistor SGB are controlled to be turned off;

in the switching stage HS3, the transfer transistor TG is controlled to be turned on to transfer the charge in the photodiode PD to the floating diffusion node FD, read out the fifth switching signal, and after the fifth switching signal is read out, the transfer transistor TG is controlled to be turned off, and after the signal of each pixel unit 101 is read out, the selection transistor SEL is controlled to be turned off, ending the Readout process Readout.

It should be understood that the "sequential" in the present application is only exemplarily described in order of 1 to 2 to 3 to 4, and in practical application, the on and off order of the transistors and the exposure order of the photodiodes are not particularly limited.

Fig. 4 is a schematic diagram of an image sensor with a four-pixel structure according to an embodiment of the present application. The image sensor may include a plurality of four-pixel structures, taking one four-pixel structure in the image sensor as an example, as shown in fig. 4, each pixel unit 101 in the four-pixel structure shares the same reset transistor RST, storage capacitor Cs, switching transistor SGB and floating diffusion capacitor CF, and compared with the pixel unit 101 which is independently used, the chip area is saved, so that the storage capacitor Cs with a larger area can be set, and further, a larger full-well capacity can be realized, thereby expanding the dynamic range of the image sensor.

The control timing of the row driver 201 is described in detail below in conjunction with the image sensor structure shown in fig. 4:

In one possible embodiment, when the image sensor is applied to a first illumination intensity, such as a high illumination intensity, the row driver 201 controls the coupled transistors by the control timing shown in fig. 5 a:

the row driver 201 controls the reset transistor RST, the switching transistor SGB, and the respective transfer transistors TG1 to 4 to be turned on, performs global reset, and controls the reset transistor RST, the switching transistor SGB, and the respective transfer transistors TG1 to 4 to be turned off after the global reset;

Exposing each photodiode PD1-4 by entering an exposure stage EP 1;

In the overflow reset stage OR1, a reset transistor RST is controlled to be turned on, the floating diffusion node FD and the storage capacitor Cs are reset, an overflow reset signal is read out, and after the overflow reset signal is read out, the reset transistor RST is controlled to be turned off;

in the reset phase HR1, the control switch transistor SGB is turned off, and the first reset signal is read out;

In one possible embodiment, when the image sensor is applied to a second illumination intensity, such as a medium illumination intensity, since the illumination intensity is weaker, there is no or less overflow charge, the row driver 201 controls the coupled transistors by the control timing shown in fig. 5 b:

The row driver 201 controls the reset transistor RST to be turned on, sequentially turns on the respective transfer transistors TG1 to 4 to perform global reset, turns off the transfer transistor TG in the reset pixel unit 101 after each pixel unit 101 is reset, controls the switch transistor SGB to be turned on after all the pixel units 101 are reset, and turns off the switch transistor SGB and the reset transistor RST after the storage capacitor Cs and the floating diffusion node FD are reset;

Entering an exposure stage EP2, and exposing each photodiode PD1-4 in sequence;

taking the Readout process Readout of one pixel cell 101 as an example:

In the reset stage PD1-HR2, the reset transistor RST and the switch transistor SGB are controlled to be turned on, the floating diffusion node FD and the storage capacitor Cs are reset, a third reset signal is read out, after the third reset signal is read out, the reset transistor RST and the switch transistor SGB are controlled to be turned off, and the selection transistor SEL is controlled to be turned on;

in the switching stage PD1-HS2, the transfer transistor TG is controlled to be turned on, charges in the photodiode PD are transferred to the floating diffusion node FD, a third switching signal is read out, and after the third switching signal is read out, the transfer transistor TG is controlled to be turned off;

In the conversion stage PD1-LS2, the switching transistor SGB and the transmission transistor TG are controlled to be conducted, namely the floating diffusion node FD and the storage capacitor Cs are connected and conducted, so that charges in the photodiode PD are transferred to the floating diffusion node FD and the storage capacitor Cs, a fourth conversion signal is read out, and after the fourth conversion signal is read out, the transmission transistor TG is controlled to be turned off;

In the reset stage PD1 to LR2, the reset transistor RST is controlled to be turned on, the fourth reset signal is read out, the transfer transistor TG and the reset transistor RST are controlled to be turned off after the fourth reset signal is read out, and the select transistor SEL is controlled to be turned off after the signal of each pixel unit 101 is read out, and the read-out process Readout is ended.

In one possible embodiment, when the image sensor is applied to a third illumination intensity, such as a low illumination intensity, since the illumination intensity is weak, the signal charges are accumulated in the photodiode PD, and there is no overflowing charge, the row driver 201 controls the coupled transistors through the control timing shown in fig. 5 c:

The row driver 201 controls the reset transistor RST to be turned on, and sequentially turns on the respective transfer transistors TG1 to 4 to perform global reset, turns off the transfer transistor TG in the pixel unit 101 that has been reset after each pixel unit 101 is reset, controls the switching transistor SGB to be turned on after all the pixel units 101 are reset, and turns off the switching transistor SGB and the reset transistor RST after global reset;

entering an exposure stage EP3, and exposing each photodiode PD1-4 in sequence;

taking the Readout process Readout of one pixel cell 101 as an example:

In the reset stage PD1-HR3, the reset transistor RST and the switch transistor SGB are controlled to be turned on, the floating diffusion node FD is reset, a fifth reset signal is read out, and after the fifth reset signal is read out, the reset transistor RST and the switch transistor SGB are controlled to be turned off;

In the switching stage PD1 to HS3, the transfer transistor TG is controlled to be turned on to transfer the charge in the photodiode PD to the floating diffusion node FD, read out the fifth switching signal, and after the fifth switching signal is read out, the transfer transistor TG is controlled to be turned off, and after the signal of each pixel unit 101 is read out, the selection transistor SEL is controlled to be turned off, ending the Readout process Readout.

The image sensor structure shown in fig. 4 occupies a small area and is convenient for hardware layout design, but the overflow path of the overflowed charges is that the photodiode PD is transmitted to the floating diffusion node FD and then to the storage capacitor Cs, SO that the first preset proportion of design needs to consider the gate voltages of the first transistor SO, the transmission transistor TG and the switching transistor SGB at the same time, the voltage design is difficult, in order to solve the voltage design problem, a second transistor SGA can be arranged in the pixel unit 101 of the image sensor, and the problem of difficult voltage design is solved by controlling the gate voltages and the width-to-length ratio of the first transistor SO and the second transistor SGA, as shown in fig. 6, the first end of the second transistor SGA is coupled with the cathode of the photodiode PD, and the second end of the second transistor SGA is coupled with the storage capacitor Cs; the second transistor SGA is configured to bleed the overflowing electric charge of the second predetermined proportion to the storage capacitor Cs.

Therefore, under high light intensity, the charge accumulated by the photodiode PD increases, and after reaching the full well capacity of the photodiode PD, an overflow phenomenon occurs, and a part of the overflow charge is discharged to the storage capacitor Cs; the other part is discharged to the power supply terminal. The discharge ratio of the overflowing electric charge can be further controlled by controlling the off-voltage of the two overflow paths and the width-to-length ratio of the gate transistor.

For example, the amount of charges of the overflowing electric charge is 900C, assuming that the first preset ratio is 2/3 and the second preset ratio is 1/3, the signal charges with 600C charges in the overflowing electric charge generated by exposure are discharged to the power supply end through the first transistor SO, and the signal charges with 300C charges are discharged to the storage capacitor Cs through the second transistor SGA.

The control timing of the row driver 201 is described in detail below in conjunction with the image sensor structure shown in fig. 6:

in one possible embodiment, where the image sensor is applied to the first illumination intensity, the row driver 201 controls the coupled transistors by the control timing shown in fig. 7 a:

The row driver 201 controls the reset transistor RST, the switching transistor SGB, the respective transfer transistors TG1 to 4, and the respective second transistors SGA1 to 4 to be turned on for global reset, and after the global reset, the row driver 201 controls the reset transistor RST, the switching transistor SGB, and the respective transfer transistors TG to be turned off; the repetition of the control sequence shown in fig. 5a is not repeated.

In one possible embodiment, where the image sensor is applied to the second illumination intensity, the row driver 201 controls the coupled transistors by the control timing shown in fig. 7 b:

The row driver 201 controls the reset transistor RST, the switching transistor SGB, each transfer transistor TG, and each second transistor SGA to be turned on to perform global reset, and after the global reset, the row driver 201 controls the reset transistor RST, the switching transistor SGB, and each transfer transistor TG to be turned off; the repetition of the control sequence shown in fig. 5b is not repeated.

In one possible embodiment, where the image sensor is applied to the third illumination intensity, the row driver 201 controls the coupled transistors by the control timing shown in fig. 7 c:

The row driver 201 controls the reset transistor RST, the switching transistor SGB, the respective transfer transistors TG1 to 4, and the respective second transistors SGA1 to 4 to be turned on for global reset, and after the global reset, the row driver 201 controls the reset transistor RST, the switching transistor SGB, and the respective transfer transistors TG to be turned off; the repetition of the control sequence shown in fig. 5c is not repeated.

Further, since there are a large number of parasitic capacitances due to the larger number of sources and drains of the transistors coupled to the floating diffusion node FD, fig. 8 provides a schematic diagram of another image sensor, which further includes a first partition transistor SGC and a second partition transistor SGD, in combination with the image sensor shown in fig. 6; a first terminal of the first split transistor SGC is coupled to the control terminal of the source follower transistor SF and the second terminal of the second split transistor SGD, respectively, a second terminal of the first split transistor SGC is coupled to the first terminal of the switching transistor SGB and the first terminal of the storage capacitor Cs, respectively, and a control terminal of the first split transistor SGC is coupled to the row driver 201; a first terminal of the second partition transistor SGD is coupled to the floating diffusion node FD and a first terminal of the reset transistor RST, respectively, a second terminal of the second partition transistor SGD is coupled to a control terminal of the source follower transistor SF, and a control terminal of the second partition transistor SGD is coupled to the row driver 201; the coupling of the first end of the first partition transistor SGC and the second end of the second partition transistor SGD forms a sensing node FC so that the signal is sensed without passing through the floating diffusion node FD, and voltage disturbance caused by the signal sensing is alleviated by changing the timing and reducing parasitic capacitance.

In one possible embodiment, the image sensor is applied to a first illumination intensity, such as a high illumination intensity, and the row driver 201 controls the coupled transistors by the control timing shown in fig. 9 a:

In the overflow stage OS1, the first partition transistor SGC is controlled to be turned on, and a partition overflow signal is read out based on the charge amount stored in the storage capacitor Cs; in an overflow reset phase OR1, a reset transistor RST is controlled to be conducted, a storage capacitor Cs is reset, and a separation overflow reset signal is read; in the reset phase HR1, the first split transistor SGC is controlled to be turned off, and after the first split transistor SGC is turned off, the second split transistor SGD is controlled to be turned on, so that the connection between the floating diffusion node FD and the control terminal of the source follower transistor SF is turned on, and a sixth reset signal is read out; in the switching stage HS1, each transfer transistor TG is controlled to be turned on so that the non-discharged charges in each photodiode PD are transferred to the floating diffusion node FD, the sixth switching signal is read out, and after the sixth switching signal is read out, each transfer transistor TG is controlled to be turned off; in the switching stage LS1, the switching transistor SGB is controlled to be turned on to turn on the connection between the floating diffusion node FD and the storage capacitor Cs, and then the transfer transistors TG are controlled to be turned on to transfer the unreleased charges in the photodiodes PD to the floating diffusion node FD and the storage capacitor Cs, the seventh switching signal is read out, and after the seventh switching signal is read out, the transfer transistors TG are controlled to be turned off; in the reset stage LR1, the first partition transistor SGC and the reset transistor RST are controlled to be turned on to reset the floating diffusion node FD and the storage capacitor Cs, read out the seventh reset signal, and after the seventh reset signal is read out, the second partition transistor SGD and the selection transistor SEL are controlled to be turned off, ending the read out process Readout. The repetition of the control sequence shown in fig. 7a is not repeated.

In a possible embodiment, where the image sensor is applied to the second illumination intensity, the row driver 201 controls the coupled transistors by the control timing shown in fig. 9b, the row driver 201 controls the first partition transistor SGC to remain in an off state for the whole period, the row driver 201 controls the second partition transistor SGD to remain in an off state before exposure, after exposure, the row driver 201 controls the second partition transistor SGD to be turned on, after reading out all signals, controls the second partition transistor SGD to be turned off, and ends the reading out process Readout. The repetition of the control sequence shown in fig. 7b is not repeated.

In a possible embodiment, where the image sensor is applied to the second illumination intensity, the row driver 201 controls the coupled transistors by the control sequence shown in fig. 9c, the row driver 201 controls the second partition transistor SGD to remain in an off state before exposure, after exposure, the row driver 201 controls the second partition transistor SGD to turn on, after reading out all signals, controls the second partition transistor SGD to turn off, ending the reading out process Readout. The repetition of the control sequence shown in fig. 7c is not repeated.

In addition, with reference to the image sensor structure shown in fig. 4, fig. 10a is a schematic layout diagram of an image sensor according to an embodiment of the present application, where a part shown by oblique lines is a connecting piece; with reference to the image sensor structure shown in fig. 6, fig. 10b is a schematic layout diagram of another image sensor according to an embodiment of the present application, where a portion shown by a dot in the figure is a connecting member.

It should be noted that the image sensor provided in the embodiment of the present application may be used in an independent package, and may also be applied to various camera modules, for example, may be applied to camera devices such as a camera, and a security monitor.

It should be noted that the same reference numerals in the drawings of the present application denote the same or similar structures, and thus a repetitive description thereof will be omitted. The words expressing the positions and directions described in the present application are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present application. The drawings of the present application are merely schematic representations of relative positional relationships and are not intended to represent true proportions.

It should be appreciated that the terms "first," "second," and the like in embodiments of the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of (a) or the like" refers to any combination of these items, including any combination of single item(s) or plural items(s), e.g., at least one of a, b, or c, may represent: a, b, c, a and b, a and c, b and c, or a and b and c.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. An image sensor, characterized in that the image sensor comprises a storage capacitor, a floating diffusion capacitor, a switching transistor, a pixel unit and a readout unit; the first end of the switch transistor is coupled with the first end of the storage capacitor, the second end of the switch transistor is coupled with the first end of the floating diffusion capacitor, a floating diffusion node is formed at the coupling position of the switch transistor and the floating diffusion capacitor, the pixel unit is respectively coupled with a power supply end and the floating diffusion node, the reading unit is respectively coupled with a column bus, the power supply end and the floating diffusion node, the second end of the storage capacitor is grounded, and the second end of the floating diffusion capacitor is grounded;

2. The image sensor of claim 1, wherein the pixel cell comprises a photodiode, a transfer transistor, and a first transistor; the anode of the photodiode is grounded, the cathode of the photodiode is respectively coupled with the first end of the transmission transistor and the first end of the first transistor, the second end of the transmission transistor is coupled with the floating diffusion node, and the second end of the first transistor is coupled with the power supply end;

3. The image sensor of claim 2, wherein the pixel cell further comprises a second transistor; wherein a first end of the second transistor is coupled with a cathode of the photodiode, and a second end of the second transistor is coupled with the storage capacitor;

4. The image sensor of any of claims 1-3, wherein the storage capacitance is a lateral overflow integration capacitance.

5. The image sensor of any of claims 1-4, further comprising a reset transistor, a first terminal of the reset transistor coupled to the floating diffusion node, a second terminal of the reset transistor coupled to the power supply terminal;

6. The image sensor of any of claims 1-5, wherein the readout unit comprises a source follower transistor and a select transistor; wherein a first terminal of the source follower transistor is coupled to a second terminal of the select transistor, a second terminal of the source follower transistor is coupled to the power supply terminal, a control terminal of the source follower transistor is coupled to the floating diffusion node, and a first terminal of the select transistor is coupled to a column bus;

7. The image sensor of claim 6, further comprising a row driver coupled to the control terminal of the switching transistor, the control terminal of the reset transistor, the control terminal of the select transistor, and the control terminal of the pass transistor, respectively;

The row driver is configured to:

8. The image sensor of claim 7, wherein the row driver is further to:

9. The image sensor of claim 8, wherein the row driver is further to:

10. The image sensor of any of claims 1-9, wherein the image sensor comprises at least one four-pixel structure, each four-pixel structure comprising four pixel cells.