CN117955498A - Step-by-step Flash ADC (analog to digital converter) with variable reference voltage - Google Patents

Abstract

The invention belongs to the technical field of analog-digital hybrid integrated circuits, and particularly relates to a step-by-step Flash ADC with a variable reference voltage. According to the invention, a group of reference voltages are obtained by using the low-dropout linear voltage stabilizer, so that in the process of each step of quantization of the step-by-step Flash ADC, the residual voltage of the quantized signal generated after the switching of the capacitor array switch is not required to be amplified, the Flash ADC reference voltage can be replaced and then directly subjected to the next quantization operation, the residual amplifying structure is not added, and the reference voltage of the comparator module is regulated down to directly perform the next quantization on the residual; therefore, the structure of the residual amplifier and the residual amplifying process are omitted by adjusting the reference voltage of the comparator circuit, the quantization speed of the circuit is improved, and the circuit design difficulty and the power consumption are reduced. Finally, the invention improves the quantization speed of the circuit and reduces the complexity of circuit design.

Description

Step-by-step Flash ADC (analog to digital converter) with variable reference voltage

Technical Field

The invention belongs to the technical field of analog-digital hybrid integrated circuits, and particularly relates to a step-by-step type FlashADC with a variable reference voltage.

Background

Analog-to-digital converters (ADCs) bridge analog and digital signals, the performance of which plays a decisive role in the overall system. With the continuous development of the times of digital information and the Internet of things, the ADC with high resolution, high conversion rate, low distortion and low power consumption is also being researched more and more. Successive Approximation (SAR) ADCs are widely used in medium-to-high resolution analog-to-digital converter circuits with the advantages of low voltage and low power consumption. However, since the SAR ADC is based on the principle of binary method, comparison and quantization can be performed only bit by bit. When quantization with N-bit quantization accuracy is performed, the SARADC needs N times of quantization to obtain a result, resulting in a bottleneck restriction of the quantization speed.

The Flash ADC can process a plurality of data in parallel and has the advantages of simple structure and high speed. On one hand, however, parameters such as Flash ADC power consumption, circuit area and the like show an exponential relationship with resolution; on the other hand, with the improvement of resolution, the problems of potential nonlinearity, mismatch and the like are also gradually serious. Therefore, the conventional Flash ADC structure is difficult to apply to a medium-high resolution circuit.

In order to exert the speed advantage of the Flash ADC and avoid a series of problems caused by the improvement of resolution, researchers invented a stepwise FlashADC structure. In the traditional step-by-step FlashADC structure, a Flash ADC firstly performs m-bit coarse quantization comparison, and then a digital logic unit controls a sampling hold capacitor array switch to switch, so as to generate a residual signal. The residual signal is subjected to residual amplification through a residual amplifier of2 ^m times, re-quantized through a Flash ADC of m-bit, and the steps are repeated for n times, so that a quantized result of n x m-bit is finally obtained. The method effectively improves the upper limit of the quantization resolution of the Flash ADC, increases the application scene of the Flash ADC, but consumes a certain degree of quantization time due to the fact that the residual amplifier structure is added in the circuit, and the residual amplifier has high requirements on the amplification precision, and increases the circuit design difficulty and potential errors.

Therefore, in order to improve the resolution and the application scene of the Flash ADC and simultaneously keep the advantages of high speed and simple structure of the Flash ADC, the Flash ADC needs to be further optimized in the aspect of architecture. One way is to circumvent the shortcomings of various architectures by combining Flash ADCs with other types of ADCs, creating a new hybrid architecture, retaining the advantages of various architectures, such as the common Flash-SAR type ADC. However, the method of the hybrid architecture needs to consider the problem of matching among various ADC structures, and has higher design difficulty; another approach is to further optimize the structure of the Flash ADC step by step to reduce the speed degradation and structural complexity drawbacks due to the step architecture, which is also a hotspot for high-speed FlashADC research.

Disclosure of Invention

Aiming at the problems or the shortcomings, the invention provides a step-by-step Flash ADC with a variable reference voltage in order to further improve the resolution of the FlashADC and keep the speed advantage of the FlashADC. And between each step of quantization of the Flash ADC, a residual error amplifying structure is not added, and the residual error is directly quantized in the next step by regulating the reference voltage of the comparator module.

The specific technical scheme of the invention is as follows:

A reference voltage variable step-by-step Flash ADC includes a low dropout linear regulator (LDO) module 100, a quantization circuit module 101, and a DAC module 102, as shown in FIG. 3.

The low dropout linear regulator module 100 (as shown in fig. 4) is composed of a resistor string voltage division sampling circuit with total K resistors R ₁、R₂、……、R_K, an error amplifier EA and a power PMOS transistor M1. The purpose of this circuit is to output the reference voltages V _{ref_c} and V _{ref_Q_M} required by the subsequent circuits.

The power supply Vdd is connected to the negative input of the error amplifier EA and to the source of the M1 pipe. The drain end of M1 is connected with one end of a resistor R1 in the resistor string voltage division sampling circuit and the positive input end of an error amplifier EA to form a negative feedback circuit with voltage connected in series. K reference voltages V _ref1、V_ref2、……、V_refK are led out from the resistor string R ₁、R₂、……、R_K and output to a back-end circuit connected with the resistor string. The back-end circuit is affected by temperature, noise, load resistance change and other interference, so that V _ref1、V_ref2、……、V_refK can be subjected to fluctuation change. When the voltage value of the V _ref1、V_ref2、……、V_refK interfered by the back-end circuit is increased/decreased, the output end of the error amplifier EA is increased/decreased due to the increase/decrease of the voltage at the positive end, so that the current of the M1 tube is decreased/increased, and finally, the V _ref1、V_ref2、……、V_refK is decreased/increased again, so that the effect of stabilizing the output voltage V _ref1、V_ref2、……、V_refK is achieved. And due to the function of resistance voltage division, the method can obtain:

A set of stable output voltage values V _ref1、V_ref2、……、V_refK are finally obtained by the low dropout linear regulator module 100. V _ref1 is input to the DAC module 102 as V _{ref_c}, and V _ref2、V_ref3、……、V_refK is output at the quantization circuit module 101 as signal ctrl_v <1: and K is sequentially input to the quantization circuit module 101 as V _{ref_Q_M} under the control of K.

The quantization circuit block 101 (shown in fig. 5) is composed of a resistor string comparator reference voltage generation array, a comparator array, and an encoder. The resistor string comparator reference voltage generating array is composed of M resistors with R ₀ resistance values in series connection, and M-1 wires are led out from the interconnection positions of adjacent resistors of the resistor string and are connected with negative terminals of the M-1 comparators in a one-to-one correspondence mode. The positive ends of the M-1 comparators are connected with externally input voltage V _hold/V_res, the OUTPUT ends are connected with the input end of an encoder (Encoder circuit), and the encoder (Encoder circuit) finally OUTPUTs a K-bit control signal CTRL <1:K > and a (K-1) N-bit OUTPUT signal OUTPUT <1: (K-1) & N >.

The quantization circuit block 101 outputs a K-bit signal ctrl_v < 1: k > to control the reference signal V _{ref_Q_M},V_{ref_Q_M} required by the low dropout linear regulator module 100 to output the quantization circuit module 101 to be one of the K-1 total reference voltages V _ref2、V_ref3、……、V_refK. Reference signalAnd then (M-1) the negative end input voltage V _{ref_Q_1}、V_{ref_Q_2}、……、V_{ref_Q_M-1} of each comparator required by Flash ADC quantification is obtained through a resistor string comparator reference voltage generation array, namely:

…

V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_M-1} is M-1 division values of FlashADC, the sampled and held input voltage V _hold/V_res is input into the positive input end of the comparator array to be compared with the positive input end of the comparator array, and finally the comparator array outputs M-1 digital code words, and binary output results are obtained through encoding in an encoder (Encoder circuit).

The DAC module 102 (shown in FIG. 6) is comprised of a capacitor array, a switch array, and a sample-and-hold switch. The capacitor array consists of N+1 capacitors C ₀、C₁、……、C_N, wherein the upper polar plates of the N capacitors C ₁、C₂、……、C_N are in one-to-one correspondence with N bit control signals CTRL <1 through N switches S ₁、S₂、……、S_N respectively: n >, V _{ref_C} and Gnd are connected, and the upper polar plate of the C ₀ capacitor is always connected with V _{ref_C}; the lower polar plates of the N+1 capacitors C ₀、C₁、……、C_N are connected with V _hold/V_res and are connected with Vin through a sample-and-hold switch S _S/H.

In the sampling stage, the lower electrode plates of the capacitors are connected with a signal V _{ref_c} generated by the low dropout linear voltage regulator module 100, a switch S _S/H is closed, and the voltages V _hold＝V_in of the upper electrode plates of the capacitors are used for completing the sampling and the holding of input signals. After the signal V _hold is input into the quantization circuit module 101, the switch array is switched according to the control signal CTRL < 1:N > generated by the quantization circuit module 101. For the s < th signal CTRL < s >, CTRL < s > =1, then the C _s bottom plate switch switches to Gnd, and if CTRL < s > =0, then the C _s bottom plate switch remains V _{ref_c}. After the switch is completed and the capacitor array voltage is established, a residual signal V _res is generated and input to the quantization circuit module 101 again.

The working sequence of the step-by-step FlashADC with the variable reference voltage comprises the following steps:

Step 1: in the sampling stage of the 1 st step quantization, V _ref1 is input to the DAC module 102 as a reference voltage V _{ref_C} required by the DAC module 102 under the control of ctrl_v1 > output from the quantization circuit module 101; the low dropout linear regulator module 100 inputs the V _ref2 signal as the reference voltage V _{ref_Q_M} required by the quantization circuit module 101 to the quantization circuit module 101 under the control of ctrl_v2 > output by the quantization circuit module 101. At this time, the lower polar plates of the capacitor are connected with V _{ref_C}, the switch S _S/H is closed, and the voltage V _hold＝V_in of the upper polar plates of the capacitor is used for completing the sampling and the holding of the input signals.

Step 2: in the quantization stage of the 1 st step quantization, the switch S _S/H is turned off, the DAC module 102 inputs V _hold to the quantization circuit module 101, and V _hold is compared with a total of M-1 reference voltages V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_M-1} obtained by dividing V _{ref_Q_M} by the resistor string.

When V _hold is larger than the reference voltage V _{ref_Q_k} and smaller than the reference voltage V _{ref_Q_k+1} (1 is not smaller than k is not smaller than M-1), the first k comparators from low to high are output as 1, and the remaining M-k-1 comparators are output as zero. M-1 comparators OUTPUT M-1 thermometer code OUTPUT code words, and then N-bit OUTPUT code words are obtained by a decoder circuit, wherein the OUTPUT is smaller than 1: n > and CTRL < 1: n >.

Step 3: the quantization circuit module 101 sets the N-bit digital word CTRL < 1: the N > output to DAC module 102 controls the switching of the switch array. When the i-th bit (i is more than or equal to 1 and less than or equal to N) controls the digital code word CTRL < i > =1, the switch S _i controlled by the signal is connected with Gnd; when the i-th bit control signal digital codeword CTRL < i > =0, the switch S _i controlled by the signal is still connected to V _{ref_c}. According to the principle of conservation of charge:

The voltage of the upper polar plate of the capacitor array is obtained through the switching of the switch array:

the voltage is the residual voltage obtained by the first FlashADC quantization.

Step 4: in the quantization stage of the 2 nd step quantization, the DAC module 102 inputs the quantized residual voltage V _res _{Conveying device} to the quantization circuit module 101, and the low dropout linear regulator module 100 inputs the generated reference voltage signal V _ref3 to the V _{ref_Q} input port of the quantization circuit module 101 under the control of the signal ctrl_v <3 > of the quantization circuit module 101. Namely at this time:

V_{ref_Q}＝V_ref3

In the quantization circuit block 101, a new set of reference voltages V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_M-1} are obtained by resistor string voltage division. At this time, the quantized residual voltage V _res and the reference voltage V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_M-1} are compared with each other by (M-1) reference voltages. When V _res is greater than the kth reference voltage V _{ref_Q_k} and less than the (k+1) th reference voltage V _{ref_Q_k+1}, the first k comparators from low to high output 1 and the remaining (M-k-1) comparators output zero. The (M-1) comparators OUTPUT (M-1) thermometer code OUTPUT code words, and the OUTPUT code words of N bits are updated by a decoder circuit to obtain OUTPUT < N+1:2N > and CTRL <1:N >.

Step 5: the quantization circuit module 101 outputs the N-bit digital word CTRL <1:n > obtained by the quantization in the step 2 to the DAC module 102 to control the switching of the switch array. When the i-th bit control signal digital code word CTRL < i > =1, the switch S _i controlled by the signal is connected with Gnd; when the i-th bit control signal digital codeword CTRL < i > =0, switch S _i controlled by the signal is still connected to V _{ref_C}. According to the principle of conservation of charge:

The voltage of the upper polar plate of the capacitor array is obtained through the switching of the switch array:

the voltage is the residual voltage obtained by the second step of Flash ADC quantization.

Step 6: and (4) repeating the step (4-5), finally finishing the quantization of the Flash ADC in the step (K-1), and finally outputting the digital code word OUTPUT <1 (K-1) & N > of the input signal obtained by quantization.

In summary, the invention obtains a group of reference voltages by using the low dropout linear voltage regulator, so that in each step of quantization process of the step-by-step Flash ADC, the residual voltage of the quantized signal generated after the switch of the capacitor array is not required to be amplified, and the Flash ADC reference voltage can be directly quantized in a next step after being replaced. By adjusting the reference voltage of the comparator circuit, the structure of the residual amplifier and the residual amplifying process can be omitted, the quantization speed of the circuit can be improved, and the circuit design difficulty and the power consumption can be reduced.

Drawings

FIG. 1 illustrates a conventional step Flash ADC operation;

FIG. 2 shows the operation of the step Flash ADC of the present invention;

FIG. 3 is a block diagram of the overall structure of the present invention;

FIG. 4 is a circuit diagram of a low dropout linear regulator (LDO) of the present invention;

FIG. 5 is a circuit diagram of a quantization circuit module of the present invention;

Fig. 6 is a circuit diagram of a DAC module of the invention.

Detailed Description

The technical scheme of the invention is further described in detail below with reference to the accompanying drawings and examples.

This example illustrates 8-bit 3-step FlashADC with one-bit redundancy.

In the low dropout linear regulator (LDO) module 100, K is 4, and if the unit resistance is R ₀, R ₁＝4R₀、R₂＝24R₀、R₃＝7R₀、R₄＝R₀ is set. Thus (2)

M in the quantization circuit block 101 takes 8 to complete the comparison of 3 bits at a time. The decoder thus selects an 8-3 decoder to effect conversion from an 8-bit thermometer code to a 3-bit binary code.

In the DAC module 102, in order to realize 8-bit FlashADC quantization with one-bit redundancy, N is taken as 9. Let C0 be the unit capacitance, then for the lower six bits of capacitance C _i＝2^i-1·C₀. To achieve one-bit redundancy, C ₇＝C₆＝32·C₀、C₈＝64·C₀、C₉＝128·C₀.

Step 1: in the sampling stage of the 1 st step quantization, under the control of ctrl_v1 > output by the quantization circuit module 101, the low dropout linear regulator module 100 inputs the V _ref2 signal as the reference voltage V _{ref_Q_8} required by the quantization circuit module 101 to the quantization circuit module 101; v _ref1 is input to the DAC module 102 as a reference voltage V _{ref_C} required for the DAC module 102. At this time, the lower polar plates of the capacitor are connected with V _{ref_C}, the switch S _S/_H is closed, and the voltage V _hold＝V_in of the upper polar plates of the capacitor is used for completing the sampling and the holding of the input signals.

Step 2: in the quantization stage of the 1 st step quantization, the switch S _S/H is turned off, V _hold is input to the quantization circuit module 101 by the DAC module 102, and V _hold is compared with a total of 7 reference voltages, such as V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_7} obtained by dividing V _{ref_Q_8} by a resistor string. Let 1.ltoreq.k.ltoreq.M-1, when V _hold is larger than the kth reference voltage V _{ref_Q_k} and smaller than the (k+1) th reference voltage V _{ref_Q_k+1}, the output of the k comparators from the low position to the high position is 1, and the output of the remaining (7-k) comparators is zero. 7 comparators OUTPUT 7 thermometer code OUTPUT code words, and then the OUTPUT code words OUTPUT of 3 bits are smaller than 1 through an 8-3 decoder circuit: 3 > and CTRI < 1:3 >.

Step 3: the quantization circuit module 101 sets the 3-bit digital word CTRL < 1: the 3 > output to DAC module 102 controls the switching of the switch array. Let 1.ltoreq.i.ltoreq.N, when the i-th bit control signal digital codeword CTRL < i > = 1, the switch S _i controlled by the signal connects Gnd; when the i-th bit control signal digital codeword CTRL < i > =0, the switch S _i controlled by the signal is still connected to V _{ref_C}. According to the principle of conservation of charge:

The voltage of the upper polar plate of the capacitor array is obtained through the switching of the switch array:

the voltage is the residual voltage obtained by the first FlashADC quantization.

Step 4: in the quantization stage of the 2 nd step quantization, the DAC module 102 inputs the quantized residual voltage V _res to the quantization circuit module 101, and simultaneously, under the control of the signal ctrl_v <3 > of the quantization circuit module 101, the low dropout linear regulator module 100 inputs the reference voltage signal V _ref3 generated by the quantization circuit module 101 to the V _{ref_Q_8} input port of the quantization circuit module 101. Namely at this time:

In the quantization circuit block 101, a new set of reference voltages V _{ref_Q1}、V_{ref_Q2}、…、V_{ref_Q_7} are obtained by resistor string voltage division. At this time, the quantized residual voltage V _res and the reference voltage V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_7} are compared with each other for 7 reference voltages. When V _res is greater than the kth reference voltage V _{ref_Q_k} and less than the (k+1) th reference voltage V _{ref_Q_k+1}, the first k comparators from low to high output 1 and the remaining (7-k) comparators output zero. 7 comparators OUTPUT 7 thermometer code OUTPUT code words, and then the decoder circuit updates the OUTPUT code words to obtain 3-bit OUTPUT code words which are smaller than 4:6 > and CTRL < 1:3 >.

Step 5: the quantization circuit module 101 sets the 3-bit digital word CTRL < 1: the 3 > output to DAC module 102 controls the switching of the switch array. When the i-th bit control signal digital code word CTRL < i > =1, the switch S _i controlled by the signal is connected with Gnd; when the i-th bit control signal digital codeword CTRL < i > =0, the switch S _i controlled by the signal is still connected to V _{ref_C}. According to the principle of conservation of charge:

The voltage of the upper polar plate of the capacitor array is obtained through the switching of the switch array:

The voltage V _res1 is the residual voltage obtained by the second step Flash ADC quantization.

Step 6: in the quantization stage of the 3 rd step quantization, the DAC module 102 inputs the quantized residual voltage V _res1 to the quantization circuit module 101, and simultaneously, under the control of the signal ctrl_v <4 > of the quantization circuit module 101, the low dropout linear regulator module 100 inputs the reference voltage signal V _ref4 generated by the same to the V _{ref_Q_8} input port of the quantization circuit module 101. Namely at this time:

in the quantization circuit block 101, a new set of reference voltages V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_7} are obtained by resistor string voltage division. At this time, the quantized residual voltage V _res and the reference voltage V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_7} are compared with each other for 7 reference voltages. When V _res is greater than the kth reference voltage V _{ref_Q_k} and less than the (k+1) th reference voltage V _{ref_Q_k+1}, the first k comparators from low to high output 1 and the remaining (7-k) comparators output zero. 7 comparators OUTPUT 7 thermometer code OUTPUT code words, and then the decoder circuit updates the OUTPUT code words to 3 bits, wherein the OUTPUT is less than 7:9 > and CTRL <1:3 >.

And finally obtaining nine-bit OUTPUT code words OUTPUT <1:9> through three steps of Flash ADC quantization, wherein 1-bit redundancy information exists, and then obtaining 8-bit digital code words.

A schematic diagram of the circuit optimizing the Flash ADC quantization process is shown in FIG. 2, and FIG. 1 is a quantization process of a traditional step-by-step Flash ADC. In the figure, T _quantify is the time required for quantification of each step of comparator, T _RG is the time required for generation of each step of residual error, T _RA is the time required for amplification of each step of residual error, and the situations of m-th comparison and m+1-th comparison of the conventional step Flash ADC and the Flash ADC with the variable reference voltage according to the invention are respectively listed in fig. 1 and 2. Compared with the traditional distributed Flash ADC structure, the method omits the residual amplification process, thereby greatly improving the quantization speed of the ADC circuit and reducing the power consumption and the complexity of the circuit structure of the ADC circuit.

In summary, the invention obtains a group of reference voltages by using the low dropout linear voltage regulator, so that in each step of quantization process of the step-by-step Flash ADC, the residual voltage of the quantized signal generated after the switch of the capacitor array is not required to be amplified, the Flash ADC reference voltage can be directly subjected to next quantization operation after being replaced, the residual amplifying structure is not added, and the residual is directly subjected to next quantization by regulating the reference voltage of the comparator module; therefore, the structure of the residual amplifier and the residual amplifying process are omitted by adjusting the reference voltage of the comparator circuit, the quantization speed of the circuit is improved, and the circuit design difficulty and the power consumption are reduced.

Claims (2)

1. A step Flash ADC with a variable reference voltage is characterized in that: the low dropout linear regulator comprises a low dropout linear regulator module 100, a quantization circuit module 101 and a DAC module 102;

The low dropout linear regulator module 100 is composed of a resistor string voltage division sampling circuit with total K R ₁、R₂、……、R_K, an error amplifier EA and a power PMOS tube M1; outputting reference voltages V _{ref_C} and C _{ref_Q_M} required by subsequent circuits;

the power supply Vdd is connected with the negative input end of the error amplifier EA and the source end of the M1 tube, and the drain end of the M1 tube is connected with one end of the resistor R1 in the resistor string voltage division sampling circuit and the positive input end of the error amplifier EA to form a voltage series negative feedback circuit; k reference voltages V _ref1、V_ref2、……、V_refK are led out from the resistor string R ₁、R₂、……、R_K and output to a back-end circuit connected with the resistor string R _ref1、V_ref2、……、V_refK; when the voltage value of the V _ref1、V_ref2、……、V_refK interfered by the back-end circuit is increased/decreased, the output end of the error amplifier EA is increased/decreased due to the increase/decrease of the voltage at the positive end, so that the current of the M1 tube is decreased/increased, and finally, the V _ref1、V_ref2、……、V_refK is decreased/increased again, so that the effect of stabilizing the output voltage V _ref1、V_ref2、……、V_refK is achieved; and due to the function of resistance voltage division, the method can obtain:

…

A set of stable output voltage values V _ref1、V_ref2、……、V_refK is finally obtained by the low dropout linear regulator module 100; v _ref1 is input to the DAC module 102 as V _{ref_C}, and V _ref2、V_ref3、……、V_refK is output at the quantization circuit module 101 as signal ctrl_v <1: under the control of K > the signals are sequentially input into the quantization circuit module 101 as V _{ref_Q_M};

The quantization circuit module 101 is composed of a resistor string comparator reference voltage generation array, a comparator array and an encoder; the resistor string comparator reference voltage generating array consists of M resistors with the resistance value of R ₀ connected in series, M-1 wires are led out from the interconnection positions of adjacent resistors of the resistor string and are respectively connected with the negative ends of M-1 comparators in a one-to-one correspondence manner, the positive ends of the M-1 comparators are all connected with externally input voltage V _hold/V_res, the OUTPUT ends of the M-1 comparators are all connected with the input end of an encoder, and the encoder finally OUTPUTs a K-bit control signal CTRL <1:K > and a (K-1) N-bit OUTPUT signal OUTPUT <1: (K-1) N >;

The quantization circuit module 101 controls the low dropout linear regulator module 100 to output a reference signal V _{ref_Q_M},V_{ref_Q_M} required by the quantization circuit module 101 as one of a total of K-1 reference voltages V _ref2、V_ref3、……、V_refK by outputting a K-bit signal ctrl_v <1:K >; the reference signal V _{ref_Q_M} is then passed through a resistor string comparator reference voltage generating array to obtain the negative terminal input voltage V _{ref_Q_1}、V_{ref_Q_2}、……、V_{ref_Q_M-1} of each comparator required by the quantization of M-1 Flash ADC, namely:

…

V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_M-1} is M-1 graduation values of the Flash ADC, the sampled and held input voltage V _hold/V_res is input into the positive input end of the comparator array to be compared with the positive input end of the comparator array, and finally the comparator array outputs M-1 digital code words, and a binary output result is obtained through encoding in an encoder;

The DAC module 102 is composed of a capacitor array, a switch array and a sample hold switch; the capacitor array is composed of n+1 capacitors C ₀、C₁、……、C_N, wherein N capacitors C ₁、C₂、……、C_N are respectively corresponding to N bit control signals CTRL <1 through N switches S ₁、S₂、……、S_N: n >, V _{ref_C} and Gnd are connected, and the upper polar plate of the capacitor C ₀ is always connected with V _{ref_C}; the lower polar plates of the N+1 capacitors C ₀、C₁、……、C_N are connected with V _hold/V_res and are connected with Vin through a sample-hold switch S _S/H;

In the sampling stage, the lower polar plates of the capacitors are connected with a signal V _{ref_c} generated by the low-dropout linear voltage regulator module 100, a switch S _S/H is closed, and the voltages V _hold＝Vi_in of the upper polar plates of the capacitors finish the sampling and the holding of input signals; after the signal V _hold is input into the quantization circuit module 101, the switch array is switched according to the control signal CTRL <1:N > generated by the quantization circuit module 101; for the s-th CTRL signal CTRL < s >, CTRL < s > = 1 then the C _s bottom plate switch switches to Gnd, and if CTRL < s > = 0 then the C _s bottom plate switch remains at V _{ref_c}; after the switch is completed and the capacitor array voltage is established, a residual signal V _res is generated and input to the quantization circuit module 101 again.

2. The step Flash ADC of claim 1, wherein the specific operation sequence comprises the steps of:

Step 1: in the sampling stage of the 1 st quantization, V _ref1 is input to the DAC module 102 as a reference voltage V _{ref_C} required by the DAC module 102 under the control of ctrl_v1 > output from the quantization circuit module 101; under the control of CTRL_V2 > output by the quantization circuit module 101, the low dropout linear regulator module 100 inputs a V _ref2 signal as a reference voltage V _{ref_Q_M} required by the quantization circuit module 101 to the quantization circuit module 101, at this time, the lower electrode plates of the capacitor are connected with V _{ref_C}, the switch S _S/H is closed, and the upper electrode plate voltage V _hold＝V_in of the capacitor is used for completing the sampling and holding of the input signal;

Step 2: in the quantization stage of the 1 st step, the switch S _S/H is turned off, the DAC module 102 inputs V _hold to the quantization circuit module 101, and V _hold is compared with a total of M-1 reference voltages V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_M-1} obtained by dividing V _{ref_Q_M} by a resistor string;

When V _hold is larger than the reference voltage V _{ref_Q_k} and smaller than the reference voltage V _{ref_Q_k+1}, k is larger than or equal to 1 and smaller than or equal to M-1, the first k comparators from low to high are output as 1, and the remaining M-k-1 comparators are output as zero; m-1 comparators OUTPUT M-1 thermometer code OUTPUT code words, and then N-bit OUTPUT code words (1:N) and CTRL (1:N) are obtained through a decoder circuit;

Step 3: the quantization circuit module 101 outputs the N-bit digital words CTRL <1:n > to the DAC module 102 to control the switching of the switch array; when the digital code word CTRL < i > =1 of the ith control signal, i is not less than 1 and not more than N, and a switch S _i controlled by the signal is connected with Gnd; when the i-th bit control signal digital codeword CTRL < i > =0, the switch S _i controlled by the signal is still connected with V _{ref_c}; according to the principle of conservation of charge:

The voltage of the upper polar plate of the capacitor array is obtained through the switching of the switch array:

the voltage is the residual voltage obtained by the first Flash ADC quantization;

step 4: in the quantization stage of the 2 nd step quantization, the DAC module 102 inputs the quantized residual voltage V _res to the quantization circuit module 101, and simultaneously, under the control of the signal ctrl_v <3> of the quantization circuit module 101, the low dropout linear regulator module 100 inputs the generated reference voltage signal V _ref3 to the V _{ref_Q} input port of the quantization circuit module 101, that is, at this time:

V_{ref_Q}＝V_ref3

In the quantization circuit module 101, a new set of reference voltages V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_M-1} is obtained by voltage division through the resistor string, and at this time, the quantized residual voltage V _res and the reference voltage V _{ref_Q_1}、V_{ref_Q_2}、…、V_{ref_Q_M-1} are compared with M-1 reference voltages in total; when V _res is larger than the kth reference voltage V _{ref_Q_k} and smaller than the k+1th reference voltage V _{ref_Q_k+1}, the k comparators from the low level to the high level output 1, and the remaining M-k-1 comparators output zero; m-1 comparators OUTPUT M-1 thermometer code OUTPUT code words, and then the OUTPUT code words of N bits are updated by a decoder circuit to obtain OUTPUT < N+1:2N > and CTRL <1:N >;

Step 5: the quantization circuit module 101 outputs the N-bit digital word CTRL <1:n > obtained by the quantization in the step 2 to the DAC module 102 to control the switching of the switch array, and when the i-th bit control signal digital word CTRL < i > =1, the switch S _i controlled by the signal is connected to Gnd; when the i-th bit control signal digital codeword CTRL < i > =0, the switch S _i controlled by the signal is still connected with V _{ref_C}; according to the principle of conservation of charge:

The voltage of the upper polar plate of the capacitor array is obtained through the switching of the switch array:

The voltage is the residual voltage obtained by the second step of Flash ADC quantization;

Step 6: and (4) repeating the step (4-5), finally quantizing the Flash ADC in the step (K-1), and finally outputting the quantized digital code word OUTPUT <1 (K-1) & N > of the input signal.