CN117955046B - Method for inhibiting tripping of leakage current protector - Google Patents
Method for inhibiting tripping of leakage current protector Download PDFInfo
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Abstract
The application discloses a method for inhibiting tripping of a leakage current protector, which is applied to an inverter system, wherein the output positive end of a rear-stage DC/AC unit of the inverter system is connected with a power grid live wire through at least two first relays connected in series, and the output negative end of the inverter system is connected with a power grid zero line through at least two second relays connected in series; in the action stage of the first relay and the second relay, the leakage current is reduced by increasing the bus voltage; or by reducing the duration of simultaneous conduction of all the first relays. The application has the beneficial effects that: the application suppresses leakage current by controlling the bus voltage or controlling the closing duration of the relay with waveform distortion, so that the peak value of the leakage current is reduced, and the tripping of the leakage current protector under the condition of non-leakage current fault can be avoided.
Description
Technical Field
The application relates to the technical field of new energy power generation, in particular to a method for inhibiting tripping of a leakage current protector.
Background
As shown in fig. 1, a typical topology structure of a photovoltaic system is shown, wherein the front stage is a DC/DC unit adopting a Boost topology, and the rear stage is a DC/AC unit adopting a Heric topology. The output of the DC/AC unit is provided with a redundant relay T 1~T4.
When the photovoltaic system performs grid-connected power generation, four stages as shown in fig. 2 are required. The first stage: the bus voltage V dc is established, the DC/DC unit is started at this stage, and the switching tube S B performs PWM. And a second stage: in the self-checking stage of the relay T 1~T4, four actions are required to implement all self-checking of the four relays. First, relay T 2、T4、T1 is high, relay T 3 is low, self-test relay T 3 monitors whether port voltage v IO is the grid voltage. The second time, relay T 2、T4、T3 high level, relay T 1 low level, self-test relay T 1, monitor if port voltage v IO is the grid voltage. Third, relay T 1、T3、T4 is high, relay T 2 is low, self-checking relay T 2 monitors whether port voltage v IO is the grid voltage. Fourth time, relay T 1、T3、T2 high level, relay T 4 low level, self-checking relay T 4, monitor if port voltage v IO is the grid voltage. And a third stage: the relays are all closed, i.e. relay T 1~T4 is high. Fourth stage: and grid-connected power generation is performed, and the DC/AC unit enters PWM modulation.
In actual use, it was found that during the second stage relay self-test and the third stage relay full-closure, the leakage current i go was distorted as shown in fig. 3 before the relays T 1 and T 3 were closed, but the DC/AC unit did not wave. The leakage current protector is sensitive to leakage current of non-50 Hz, when distortion in the output ground current i g0 is too large, the non-50 Hz component is increased, and tripping of the leakage current protector is easy to cause, so that the DC/AC unit is off-line.
Disclosure of Invention
It is an object of the present application to provide a method for suppressing tripping of a leakage current protector that addresses at least one of the above-mentioned drawbacks of the prior art.
In order to achieve at least one of the above objects, the present application adopts the following technical scheme: the method is applied to an inverter system, wherein an output positive end of the inverter system is connected with a power grid live wire through at least two first relays connected in series, and an output negative end of the inverter system is connected with a power grid zero line through at least two second relays connected in series; in the action stage of the first relay and the second relay, the leakage current is reduced by increasing the bus voltage; or by reducing the duration of simultaneous conduction of all the first relays.
Preferably, the number of the first relays is two, namely, the relays T 1 and T 3; the number of the second relays is two, namely, the relays T 2 and T 4.
Preferably, in the self-checking phase and the full-closing phase of the relay T 1~T4, the leakage current is reduced by increasing the bus voltage.
Preferably, in the self-checking stage of the relay T 1~T4, when the relays T 1 and T 3 are turned on simultaneously, the bus voltage is raised to V max, and the bus voltage maintains the normal voltage V normal during the rest of the process.
Preferably, during the process in which relays T 1 and T 3 remain on, the bus voltage gradually rises from the voltage V normal corresponding to the beginning of the process to the voltage V max corresponding to the end of the process through a slope k.
Preferably, the closing of relay T 4 is detected during the full closing phase of relay T 1~T4, and upon detecting that relay T 4 is closed, the system immediately enters the grid-tie generation phase to shorten the duration of the full closing phase of relay T 1~T4.
Preferably, the duration of a single self-checking action of the relay T 1~T4 is set to be T; by adjusting the self-checking sequence of the relay T 1~T4, the two self-checking actions including the simultaneous conduction of the relays T 1 and T 3 are staggered, so that the single continuous time of the simultaneous conduction of the relays T 1 and T 3 is shortened from 2T to T.
Preferably, the two self-checking actions including the simultaneous conduction of the relays T 1 and T 3 are the first self-checking action and the third self-checking action of the self-checking phase, respectively.
Preferably, the self-checking form of the relay T 1~T4 is adjusted so as to avoid the simultaneous conduction of the relays T 1 and T 3 in the self-checking stage of the relay T 1~T4, and further shorten the simultaneous conduction time of the relays T 1 and T 3 to 0 in the self-checking stage.
Preferably, in the self-checking stage of the relay T 1~T4, the corresponding relay of the opposite bus of the target relay to be self-checked is closed, and the other relays are opened; the self-checking judgment of the relay is carried out by detecting whether the bus voltage between the relays is the target voltage; and the self-checking stage is completed after the four relays are respectively subjected to self-checking judgment.
Compared with the prior art, the application has the beneficial effects that:
the application suppresses leakage current by controlling the bus voltage or controlling the closing duration of the relay with waveform distortion, so that the peak value of the leakage current is reduced, and the tripping of the leakage current protector under the condition of non-leakage current fault can be avoided.
Drawings
Fig. 1 is a schematic diagram of a topology circuit structure of a photovoltaic system in the prior art.
Fig. 2 is a schematic timing logic diagram of the photovoltaic system shown in fig. 1.
Fig. 3 is a schematic diagram of waveform simulation of the photovoltaic system shown in fig. 1 when performing relay self-test and relay closing.
Fig. 4 is a schematic diagram of a system waveform structure when the photovoltaic system relays T 1 and T 3 shown in fig. 1 are closed.
Fig. 5 is a schematic diagram of an equivalent circuit structure of stage one based on the schematic diagram of the waveform structure shown in fig. 4.
Fig. 6 is a schematic diagram of an equivalent circuit of stage two and stage four divided based on the schematic diagram of the waveform structure shown in fig. 4.
Fig. 7 is a schematic diagram of an equivalent circuit structure of stage three based on the schematic diagram of the waveform structure shown in fig. 4.
FIG. 8 is a schematic diagram of the timing logic of the photovoltaic system based on bus voltage boosting of the present invention.
FIG. 9 is a schematic diagram of timing logic of a photovoltaic system based on shortening the bus voltage rise time according to the present invention.
Fig. 10 is a schematic diagram of sequential logic of the photovoltaic system based on gradual rise of bus voltage according to the present invention.
Fig. 11 is a schematic circuit diagram of a photovoltaic system based on voltage acquisition between relays according to the present invention.
Fig. 12 is a schematic diagram of the timing logic of the photovoltaic system of the present invention based on relay self-test form adjustment.
Fig. 13 is a schematic diagram of sequential logic of a photovoltaic system based on relay self-test sequence adjustment according to the present invention.
Detailed Description
The present application will be further described with reference to the following specific embodiments, and it should be noted that, on the premise of no conflict, new embodiments may be formed by any combination of the embodiments or technical features described below.
In the description of the present application, it should be noted that, for the azimuth words such as terms "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., the azimuth and positional relationships are based on the azimuth or positional relationships shown in the drawings, it is merely for convenience of describing the present application and simplifying the description, and it is not to be construed as limiting the specific scope of protection of the present application that the device or element referred to must have a specific azimuth configuration and operation.
It should be noted that the terms "first," "second," and the like in the description and in the claims are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The terms "comprises" and "comprising," along with any variations thereof, in the description and claims, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical scheme of the application is not limited to a photovoltaic system, but can be a wind power generation system, a hydroelectric generation system and the like, and can be used as long as the technical scheme of the application comprises an inverter system. In order to facilitate clear and detailed understanding of the technical scheme of the present application, the technical scheme of the present application may be described in detail below through a photovoltaic system.
As shown in fig. 1, the photovoltaic system includes a DC/DC unit of a front stage and a DC/AC unit of a rear stage, the DC/DC unit including a switching tube S B connected to positive and negative buses; the DC/AC unit comprises switching tubes S a1、Sb1、Sa2 and S b2, switching tubes S a1 and S b1 are connected in parallel with a positive bus, switching tubes S b2 and S a2 are connected in parallel with a negative bus, switching tubes S a1 and S a2 are connected in series, and switching tubes S b1 and S b2 are connected in series. And switching tubes S 2 and S 3 with opposite directions are also connected in series between the positive and negative output terminals of the DC/AC unit and the power grid. Relay T 1~T4 is provided between switching tubes S 2 and S 3 to the grid.
The process of distortion of leakage current when the relays T 1 and T 3 between the output positive terminal of the post-stage DC/AC unit connected to the photovoltaic system and the live line of the power grid are simultaneously closed, which is shown in fig. 1 and 2, can be first analyzed in detail.
As shown in fig. 4, one period of the grid voltage after the relays T 1 and T 3 are simultaneously closed may be selected for analysis, and the one period of the grid voltage is divided into four phases; i.e., the areas corresponding to ①、②、③ and ④ in fig. 4.
Stage one: that is, as shown in region ① of FIG. 4, the corresponding waveform period segment is [ t 0, pi/2ω ]; fig. 5 shows an equivalent circuit structure. In this phase, after the positive zero crossing of the grid, it is assumed that, starting from time t 0, the grid voltage V g starts to be greater than the capacitance voltage V dc+ of the bus capacitance of the corresponding positive bus. Then, the diode of the switching tube S a1 is turned on, and charges the capacitor to the ground on the dc side through the diode, and the charging is stopped at the positive peak of the power grid. Finally, the upper edge of the capacitor voltage V dc+ is V gm, where V gm is the grid voltage peak. Similarly, the upper edge of the capacitance voltage V dc– of the bus capacitor corresponding to the negative bus is V gm–Vdc,Vdc, which is the bus voltage.
Assuming that the system damping is large, the peak I g0M of the leakage current is negative and approximated as shown in equation one below:
。
Wherein C PV+ represents the positive end-to-ground capacitance of the photovoltaic module PV, and C PV- represents the negative end-to-ground capacitance of the photovoltaic module PV; c dc+ represents positive bus-to-ground capacitance, C dc- represents negative bus-to-ground capacitance; ω represents the angular frequency of the grid voltage.
It should be noted that at time t 0, the threshold of the grid voltage is equal to the capacitor voltage V dc+, and is also equal to the capacitor voltage V dc– plus the bus voltage V dc; the time t 0 can be calculated by the following two:
。
Stage two: that is, as shown in region ② of FIG. 4, the corresponding waveform period segment is [ pi/2ω, pi/ω+t 0 ]; fig. 6 is a schematic diagram of an equivalent circuit structure. At this stage, the grid starts to drop from the forward peak, the diode turns off, and the dc side capacitor voltage remains unchanged because there is no discharge loop. Finally, the negative ground voltage of the photovoltaic module PV, i.e. the capacitance voltage V dc–, stabilizes at the upper edge V gm-Vdc.
Stage three: that is, as shown in region ③ of FIG. 4, the corresponding waveform period segment is [ pi/omega+t 0, 3pi/2omega ]; fig. 7 shows an equivalent circuit structure. At this stage, after the negative grid zero crossing, the capacitor voltage V dc– is assumed to be greater than the grid voltage starting from the time pi/ω+t 0. Then, the diode of the switching tube S a2 is turned on, and the capacitor on the dc side is discharged through the diode and stops at the negative peak of the power grid. Finally, the negative ground voltage of the photovoltaic module PV, i.e. the lower edge of the capacitor voltage V dc–, is-V gm.
Similarly, assuming that the system damping is large, the peak I g0M of the leakage current is forward and approximated as shown in equation three below:
。
It should be noted that at time pi/ω+t 0, the threshold of the grid voltage is equal to the capacitor voltage V dc–, as shown in the following formula four:
。
By observing the second and fourth equations, it can be calculated that the time t 0 corresponding to the first and third phases is identical. Similarly, by observing the first and third formulas, the peak value I g0M of the leakage current is also identical.
Stage four: that is, as shown in region ④ of FIG. 4, the corresponding waveform period segment is [ 3pi/2ω, 2pi/ω+t 0 ]; fig. 6 is a schematic diagram of an equivalent circuit structure. At this stage, the grid starts to rise from the negative peak, the diode turns off, and the dc side capacitor voltage remains unchanged because there is no discharge loop. Finally, the negative voltage to ground (i.e., the capacitive voltage) V dc– of the photovoltaic module PV stabilizes at the lower edge-V gm.
The parameters affecting the leakage current I g0 can be analyzed below, and as can be seen from equation one, the peak value I g0M of the leakage current is inversely proportional to the time t 0 under the condition that the grid voltage is unchanged and the loop impedance is unchanged. In addition, as can be seen from equation two, time t 0 is proportional to bus voltage V dc.
Based on the analysis result, in one preferred embodiment of the present application, a method for suppressing tripping of a leakage current protector may suppress the leakage current by increasing the bus voltage V dc or shortening the rising duration of the leakage current, so as to reduce the peak value of the leakage current, thereby avoiding the occurrence of false tripping operation of the leakage current protector.
Specifically, the method for inhibiting tripping of the leakage current protector is applied to an inverter system, wherein the output positive end of the inverter system is connected with a power grid live wire through at least two first relays connected in series, and the output negative end of the inverter system is connected with a power grid zero line through at least two second relays connected in series. In the action stage of the first relay and the second relay, the leakage current is reduced by increasing the bus voltage; or by reducing the duration of simultaneous conduction of all the first relays.
It should be noted that, in the grid-connection process of the power systems such as photovoltaic power generation, wind power generation and hydroelectric power generation, the inverter system needs to be connected with the power grid in a relay redundancy manner. Therefore, the method for inhibiting the tripping of the leakage current protector is applied to the inverter system to adapt to different power grid-connected scenes.
Meanwhile, as shown by the analysis of the distortion process of the leakage current, the distortion process of the leakage current mainly occurs in a relay connected in series on a bus between an output positive end of a DC/AC unit of an inverter system and a live wire of a power grid, namely, the first relay is closed and conducted at the same time. Therefore, the peak lifting time of the leakage current can be shortened by shortening the duration of closing and conducting the first relay at the same time, and further the suppression of the leakage current is realized. Of course, the action phases of the first relay and the second relay comprise a self-checking phase and a full-closing phase of the relay, and the situation that the first relay is fully closed and conducted exists in the traditional relay self-checking phase; of course, in the all-closed phase of the relay, there must be a case where all the first relay is closed and turned on. Therefore, in the operation stage of the first relay and the second relay, the leakage current can be reduced by increasing the bus voltage.
It should be noted that for redundancy of relays, at least two relays in series are provided on a single bus to achieve redundancy. Of course, too many relays connected in series on a single bus also affects the response speed and impedance of the system. Therefore, the present embodiment may preferably have two numbers of the first relay and the second relay; the two first relays may be labeled as relays T 1 and T 3, respectively, and the two second relays may be labeled as relays T 2 and T 4, respectively; the following description will also take relay T 1~T4 as an example.
In this example, there are three specific embodiments for increasing the bus voltage in the operation stage of the relay T 1~T4.
First kind: the process of increasing the bus voltage is only in the self-checking stage of the relay T 1~T4.
Second kind: the process of increasing the bus voltage is only in the fully closed phase of relay T 1~T4.
Third kind: as shown in fig. 8, the process of increasing the bus voltage is in the self-check phase and the full-close phase of the relay T 1~T4.
It should be noted that the duration of the full closing phase of the relay T 1~T4 is relatively short, so that the second mode has limited effect of suppressing the leakage current and cannot achieve good suppression effect. Therefore, the first and third embodiments described above are preferably employed in this example.
The following may be described in detail by the third embodiment described above for convenience of understanding. As shown in fig. 8, in the phase of establishing the bus voltage and the phase of grid-connected power generation, the bus voltage is controlled in the same manner as the conventional method, and the voltage value is V normal. And in the self-checking stage and the full-closing stage of the relay, the bus voltage is increased, and the controlled voltage value is V max. As can be seen from the waveform distortion analysis process of the leakage current, if the bus voltage is increased before the relays T 1 and T 3 are closed but the DC/AC unit does not emit waves, the peak value of the leakage current i g0 can be reduced, so that the distorted waveform can be effectively inhibited from easily causing tripping of the leakage protection.
In this embodiment, as shown in fig. 9, in the self-checking stage of the relay T 1~T4, when the relays T 1 and T 3 are turned on simultaneously, the bus voltage is raised to V max, and the bus voltage maintains the normal voltage V normal in the rest of the process.
It should be noted that the losses of the system will increase during the self-test phase and the full-close phase of the relay due to the pulling up of the bus voltage; in order to further reduce the system losses, the duration of the bus voltage pull-up can be shortened as much as possible. In the self-checking stage of the relay, there is a process that the relays T 1 and T 3 are not closed simultaneously, so that the bus voltage corresponding to the process that the relays T 1 and T 3 are not closed simultaneously can be maintained at the normal voltage V normal, and the bus voltage is increased to V max only when the relays T 1 and T 3 are closed simultaneously, so that the pull-up time of the bus voltage can be effectively shortened to reduce the system loss.
Specifically, in four actions of the relay self-test: for the first time, relay T 2、T4、T1 is high level, relay T 3 is low level, self-test relay T 3; the bus voltage at this time was V normal. The second time, relay T 2、T4、T3 high level, relay T 1 low level, self-checking relay T 1; the bus voltage at this time was V normal. Third time, relay T 1、T3、T4 is high level, relay T 2 is low level, self-checking relay T 2; the bus voltage at this time is raised to V max. Fourth time, relay T 1、T3、T2 high level, relay T 4 low level; the bus voltage at this time maintains V max. Compared with the mode of improving the bus voltage in the full self-checking stage, the method can shorten the pull-up time of the bus voltage in the relay self-checking stage by half.
In this embodiment, as shown in fig. 10, during the process in which the relays T 1 and T 3 remain on, the bus voltage gradually rises from the voltage V normal corresponding to the start of the process to the voltage V max corresponding to the end of the process through the slope k.
It will be appreciated that tripping of the leakage protector is an accumulated action, which does not take place until a certain time. Therefore, at the very beginning of the closing conduction of relays T 1 and T 3, the leakage current can be a little larger, and the rise of the bus voltage is not large. As the duration of closed conduction of relays T 1 and T 3 increases, the leakage current needs to be smaller, which is a larger increase in bus voltage. In popular terms, the boost to the bus voltage does not immediately boost to the maximum voltage V max, but rather increases slowly over time, as relays T 1 and T 3 are closed on. The gradual rise of the bus voltage can be linear or nonlinear; in this embodiment, a linear lifting mode is preferably adopted. That is, by setting a slope k of the bus voltage rise, the bus voltage is gradually raised to V max according to the slope k. According to the embodiment, the accumulated efficiency of the leakage current protector is utilized, so that the influence of busbar voltage promotion on a system can be minimized, leakage current is effectively restrained, and tripping of the leakage current protector is prevented.
In this embodiment, there are mainly three embodiments for suppressing leakage current by shortening the continuous time for which the relays T 1 and T 3 are closed and turned on.
First kind: the closing on duration of relays T 1 and T 3 in the full closing phase is shortened.
Second kind: the duration of closed conduction of relays T 1 and T 3 in the self-test phase is shortened.
Third kind: the duration of closed conduction of the relays T 1 and T 3 in the self-check phase and the full-close phase is shortened.
It should be noted that the essence of the third embodiment is the combination of the first embodiment and the second embodiment, so that the third embodiment can be obtained by implementing the first embodiment and the second embodiment simultaneously. For simplicity of explanation, only the specific processes of the first embodiment and the second embodiment will be described below.
Specifically, for the first embodiment described above, the closing of relay T 4 is detected during the full closing phase of relay T 1~T4, and after detecting that relay T 4 is closed, the system immediately enters the grid-connected power generation phase to shorten the duration of the full closing phase of relay T 1~T4; the bus voltage is now regulated by V max back to V normal.
It should be noted that in the full-closing phase of the relay T 1~T4, as known from the self-checking phase of the relay T 1~T4, only the relay T 4 is not closed in the final process of the self-checking phase, so that the system vertical horse can be controlled to enter the grid-connected wave-generating mode only after the relay T 4 is detected to be closed; the duration of the full closing phase of the relay can now be greatly shortened.
It will be appreciated that the action of the relays T 1 and T 3 simultaneously closing and conducting is located in the third and fourth actions in succession of the self-test phase, as known from the conventional self-test phase of the relay T 1~T4 described in the background. Namely, when the relay T 1~T4 adopts the traditional self-checking mode to perform self-checking, the duration of closing and conducting the relay T 1 and the relay T 3 simultaneously is the time of two actions. Therefore, for the second embodiment described above, the present application can be realized by the following two methods.
The method comprises the following steps: relays T 1 and T 3 are still able to conduct closed simultaneously, but for a reduced duration.
The second method is as follows: the relays T 1 and T 3 cannot achieve simultaneous closed conduction.
For the first method, in the present embodiment, as shown in fig. 13, let the duration of a single self-checking action of the relay T 1~T4 be T; by adjusting the self-checking sequence of the relay T 1~T4, the two self-checking actions including the simultaneous conduction of the relays T 1 and T 3 are staggered, so that the single continuous time of the simultaneous conduction of the relays T 1 and T 3 is shortened from 2T to T. The method can also be used simultaneously with the method of increasing the bus voltage when the relays T 1 and T 3 are simultaneously turned on.
Specifically, eight self-checking sequence adjustment modes for staggering two self-checking actions including simultaneous conduction of the relays T 1 and T 3 are implemented, and the self-checking sequence adjustment modes are respectively as follows:
(1) The relay T 2 is self-checked, at this time, the relays T 1、T3 and T 4 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. And then the self-checking relay T 1 is closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time at the moment when the relays T 2、T3 and T 4 are closed and conducted. And then the self-checking relay T 4, at the moment, the relays T 1、T2 and T 3 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. Finally, the self-checking relay T 3 is closed and conducted by the relays T 1、T2 and T 4, and the action relays T 1 and T 3 are not conducted at the same time.
(2) The relay T 2 is self-checked, at this time, the relays T 1、T3 and T 4 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. And then the self-checking relay T 3 is closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time at the moment when the relays T 1、T2 and T 4 are closed and conducted. And then the self-checking relay T 4, at the moment, the relays T 1、T2 and T 3 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. Finally, the self-checking relay T 1 is closed and conducted by the relays T 2、T3 and T 4, and the action relays T 1 and T 3 are not conducted at the same time.
(3) The relay T 4 is self-checked, at this time, the relays T 1、T2 and T 3 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. And then the self-checking relay T 1 is closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time at the moment when the relays T 2、T3 and T 4 are closed and conducted. And then the self-checking relay T 2, at the moment, the relays T 1、T3 and T 4 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. Finally, the self-checking relay T 3 is closed and conducted by the relays T 1、T2 and T 4, and the action relays T 1 and T 3 are not conducted at the same time.
(4) The relay T 4 is self-checked, at this time, the relays T 1、T2 and T 3 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. And then the self-checking relay T 3 is closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time at the moment when the relays T 1、T2 and T 4 are closed and conducted. And then the self-checking relay T 2, at the moment, the relays T 1、T3 and T 4 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. Finally, the self-checking relay T 1 is closed and conducted by the relays T 2、T3 and T 4, and the action relays T 1 and T 3 are not conducted at the same time.
(5) The relay T 3 is self-checked, at this time, the relays T 1、T2 and T 4 are closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time. And then the self-checking relay T 2, at the moment, the relays T 1、T3 and T 4 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. And then the self-checking relay T 1 is closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time at the moment when the relays T 2、T3 and T 4 are closed and conducted. Finally, the self-checking relay T 4 is closed and conducted by the relays T 1、T2 and T 3, and the action relays T 1 and T 3 are conducted simultaneously.
(6) The relay T 3 is self-checked, at this time, the relays T 1、T2 and T 4 are closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time. And then the self-checking relay T 4, at the moment, the relays T 1、T2 and T 3 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. And then the self-checking relay T 1 is closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time at the moment when the relays T 2、T3 and T 4 are closed and conducted. Finally, the self-checking relay T 2 is closed and conducted by the relays T 1、T3 and T 4, and the action relays T 1 and T 3 are conducted simultaneously.
(7) The relay T 1 is self-checked, at this time, the relays T 2、T3 and T 4 are closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time. And then the self-checking relay T 2, at the moment, the relays T 1、T3 and T 4 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. And then the self-checking relay T 3 is closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time at the moment when the relays T 1、T2 and T 4 are closed and conducted. Finally, the self-checking relay T 4 is closed and conducted by the relays T 1、T2 and T 3, and the action relays T 1 and T 3 are conducted simultaneously.
(8) The relay T 1 is self-checked, at this time, the relays T 2、T3 and T 4 are closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time. And then the self-checking relay T 4, at the moment, the relays T 1、T2 and T 3 are closed and conducted, and the action relays T 1 and T 3 are conducted simultaneously. And then the self-checking relay T 3 is closed and conducted, and the action relays T 1 and T 3 are not conducted at the same time at the moment when the relays T 1、T2 and T 4 are closed and conducted. Finally, the self-checking relay T 2 is closed and conducted by the relays T 1、T3 and T 4, and the action relays T 1 and T 3 are conducted simultaneously.
It should be noted that for the above eight self-test sequence adjustment methods, a single continuous time for simultaneously turning on the relays T 1 and T 3 in the relay self-test stage can be reduced from 2T to T. For the full closing phase after the self-checking phase of the relay is completed, the manner of shortening the full closing phase can be adopted, so that the duration of the full closing phase of the relay is about several milliseconds, and the leakage current caused in the duration is insufficient to cause tripping of the leakage current protector.
Of course, it is contemplated that there may be situations where relays T 1 and T 3 are simultaneously conducting during the full closing phase of relay T 1~T4. In the self-checking sequence adjustment process of the relay T 1~T4, it is preferable that the two self-checking actions including the simultaneous conduction of the relays T 1 and T 3 are the first self-checking action and the third self-checking action of the self-checking stage, respectively. The self-checking sequence adjusting modes of the relay T 1~T4 preferably adopt the adjusting modes (1) - (4), so that the time increase of the simultaneous conduction of the relays T 1 and T 3 caused by the continuity of the last self-checking stage and the full closing stage of the relay can be avoided.
For the second method, in the embodiment, as shown in fig. 11 and 12, the self-checking form of the relay T 1~T4 is adjusted so as to avoid the simultaneous conduction of the relays T 1 and T 3 in the self-checking stage of the relay T 1~T4, and further shorten the simultaneous conduction time of the relays T 1 and T 3 to 0 in the self-checking stage.
Specifically, there are various adjustment modes for the self-checking mode of the relay, one of which is shown in fig. 11 and 12, in the self-checking stage of the relay T 1~T4, the corresponding relay of the opposite bus of the target relay to be self-checked is closed, and the other relays are opened; the self-checking judgment of the relay is carried out by detecting whether the bus voltage between the relays is the target voltage; and the self-checking stage is completed after the four relays are respectively subjected to self-checking judgment.
For ease of understanding, a detailed description of specific implementations will follow. When the self-checking relay T 4 is needed, the corresponding relay on the reverse bus of the relay T 4 is T 3, the relay T 3 is closed and conducted, and meanwhile, the relays T 1、T2 and T 4 are disconnected; and then detecting whether the bus voltage between the relays is the power grid voltage to finish the self-checking of the relay T 4. Meanwhile, when the self-checking relay T 3 is needed, the relay T 4 is closed and conducted, and meanwhile, the relays T 1、T2 and T 3 are disconnected; and then detecting whether the bus voltage between the relays is the power grid voltage to finish the self-checking of the relay T 3. When the self-checking relay T 2 is needed, the relay T 1 is closed and conducted, and meanwhile, the relays T 2、T3 and T 4 are disconnected; and then detecting whether the bus voltage between the relays is the output voltage of the DC/AC unit to complete the self-checking of the relay T 2. When the self-checking relay T 1 is needed, the relay T 2 is closed and conducted, and meanwhile, the relays T 1、T3 and T 4 are disconnected; and then detecting whether the bus voltage between the relays is the output voltage of the DC/AC unit to complete the self-checking of the relay T 1.
It should be noted that, after the self-checking form is adopted, the self-checking sequence of the relays T 1~T4 can be arbitrarily adjusted, so long as the self-checking of each relay can be completed.
Meanwhile, as shown in fig. 11, the bus voltage between the relays is the voltage v tset of the bus between the relays T 1 and T 3 and the bus between the relays T 2 and T 4. Taking a target relay as a relay T 4 as an example, the relay T 3 is closed and conducted, the relays T 1、T2 and T 4 are opened, the output end of the DC/AC unit is in an off state theoretically, a bus between the relays T 1 and T 3 is connected with a power grid through the relay T 3, if the relay T 4 is adhered at the moment, the value of the bus voltage v tset is theoretically equal to the power grid voltage, if the relay T 4 is not adhered at the moment, the value of the bus voltage v tset is theoretically equal to 0. Taking a target relay as a relay T 2 as an example, the relay T 1 is closed and conducted, the relays T 2、T3 and T 4 are opened, the system is in an off state with the power grid theoretically, a bus between the relays T 1 and T 3 is connected with the output end of the DC/AC unit through the relay T 1, if the relay T 2 is adhered at the moment, the value of the bus voltage v tset is equal to the output voltage of the DC/AC unit theoretically, if the relay T 2 is not stuck at this time, the value of the bus voltage v tset is theoretically equal to 0. The purpose of the self-test phase of the relay is to detect if uncontrolled adhesion of the relay occurs.
The foregoing has outlined the basic principles, features, and advantages of the present application. It will be understood by those skilled in the art that the present application is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present application, and various changes and modifications may be made therein without departing from the spirit and scope of the application, which is defined by the appended claims. The scope of the application is defined by the appended claims and equivalents thereof.
Claims (9)
1. The method is applied to an inverter system, wherein an output positive end of the inverter system is connected with a power grid live wire through at least two first relays connected in series, and an output negative end of the inverter system is connected with a power grid zero line through at least two second relays connected in series; the method is characterized in that in the action stage of the first relay and the second relay, the leakage current is reduced by increasing the bus voltage;
Or, reducing leakage current by shortening the duration of time that all of the first relays are simultaneously turned on;
the action phases of the first relay and the second relay comprise a self-checking phase and a full-closing phase of the relay.
2. The method of suppressing tripping of a leakage current protector of claim 1, wherein the number of first relays is two, relays T 1 and T 3, respectively; the number of the second relays is two, namely, the relays T 2 and T 4.
3. The method of suppressing tripping of a leakage current protector according to claim 2, characterized in that, in the self-checking phase of the relay T 1~T4, when the relays T 1 and T 3 are simultaneously turned on, the bus voltage is raised to V max, and the bus voltage is maintained at the normal voltage V normal during the rest of the process.
4. A method of suppressing tripping of a leakage current protector as defined in claim 3, characterized in that during the process in which the relays T 1 and T 3 remain on, the bus voltage is gradually raised from the voltage V normal corresponding to the beginning of the process to the voltage V max corresponding to the end of the process by the slope k.
5. A method of suppressing tripping of a leakage current protector as defined in any one of claims 2-4, characterized in that the closing of relay T 4 is detected during the fully closed phase of relay T 1~T4; upon detecting that relay T 4 is closed, the system immediately enters a grid-tie power generation phase to shorten the duration of the fully closed phase of relay T 1~T4.
6. The method of suppressing tripping of a leakage current protector of claim 5, wherein the duration of a single self-test action of relay T 1~T4 is set to be T; by adjusting the self-checking sequence of the relay T 1~T4, the two self-checking actions including the simultaneous conduction of the relays T 1 and T 3 are staggered, so that the single continuous time of the simultaneous conduction of the relays T 1 and T 3 is shortened from 2T to T.
7. The method of suppressing a leakage current protector trip of claim 6, wherein the two self-test actions including the simultaneous conduction of relays T 1 and T 3 are the first self-test action and the third self-test action of the self-test phase, respectively.
8. The method of suppressing a leakage current protector trip according to claim 5, wherein the self-test form of the relay T 1~T4 is adjusted so that the simultaneous conduction of the relays T 1 and T 3 is avoided in the self-test stage of the relay T 1~T4, thereby shortening the simultaneous conduction time of the relays T 1 and T 3 to 0 in the self-test stage.
9. The method of suppressing tripping of a leakage current protector of claim 8, wherein in a self-checking phase of the relay T 1~T4, the corresponding relay of the opposite bus of the target relay to be self-checked is closed, and the remaining relays are opened; the self-checking judgment of the relay is carried out by detecting whether the bus voltage between the relays is the target voltage; and the self-checking stage is completed after the four relays are respectively subjected to self-checking judgment.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105337519A (en) * | 2015-11-18 | 2016-02-17 | 阳光电源股份有限公司 | Self-checking system and self-checking method for cascaded multilevel converter |
| CN110703085A (en) * | 2019-11-11 | 2020-01-17 | 爱士惟新能源技术(扬中)有限公司 | Relay fault detection method for grid-connected inverter |
| CN112924855A (en) * | 2019-12-06 | 2021-06-08 | 苏州阿特斯阳光电力科技有限公司 | Grid-connected relay circuit |
| GB2603854A (en) * | 2021-01-12 | 2022-08-17 | Schneider Electric Ind Sas | Residual current device and self-testing method for the same |
| CN117277242A (en) * | 2023-11-21 | 2023-12-22 | 锦浪科技股份有限公司 | Leakage current suppression method for photovoltaic system |
| CN117318454A (en) * | 2023-11-28 | 2023-12-29 | 锦浪科技股份有限公司 | Low-frequency common-mode leakage current suppression method |
-
2024
- 2024-03-26 CN CN202410348106.4A patent/CN117955046B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105337519A (en) * | 2015-11-18 | 2016-02-17 | 阳光电源股份有限公司 | Self-checking system and self-checking method for cascaded multilevel converter |
| CN110703085A (en) * | 2019-11-11 | 2020-01-17 | 爱士惟新能源技术(扬中)有限公司 | Relay fault detection method for grid-connected inverter |
| CN112924855A (en) * | 2019-12-06 | 2021-06-08 | 苏州阿特斯阳光电力科技有限公司 | Grid-connected relay circuit |
| GB2603854A (en) * | 2021-01-12 | 2022-08-17 | Schneider Electric Ind Sas | Residual current device and self-testing method for the same |
| CN117277242A (en) * | 2023-11-21 | 2023-12-22 | 锦浪科技股份有限公司 | Leakage current suppression method for photovoltaic system |
| CN117318454A (en) * | 2023-11-28 | 2023-12-29 | 锦浪科技股份有限公司 | Low-frequency common-mode leakage current suppression method |
Non-Patent Citations (1)
| Title |
|---|
| 固体继电器在火工品点火电路的应用;赵笃良;郭建章;刘理想;韦跃武;;火工品;20191015(第05期);第16-20页 * |
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