CN117954471A - Epitaxial structure of semiconductor device, preparation method of epitaxial structure and semiconductor device - Google Patents

Abstract

The embodiment of the invention provides an epitaxial structure of a semiconductor device, a preparation method thereof and the semiconductor device, wherein the epitaxial structure comprises a substrate; a buffer layer located on one side of the substrate, the buffer layer including iron atoms; a barrier structure located on a side of the buffer layer away from the substrate, the barrier structure comprising at least one silicon nitride barrier layer; a channel structure comprising at least one channel layer, wherein at least one channel layer is positioned on one side of the barrier structure away from the substrate; wherein the channel structure is in contact with both the blocking structure and the buffer layer. By adopting the technical scheme, the tailing effect of iron atoms on the channel structure can be reduced and the crystal quality of the channel layer can be improved by arranging the silicon nitride barrier layer, so that the quality of the epitaxial structure and the quality of the semiconductor device can be improved.

Description

Epitaxial structure of semiconductor device, preparation method of epitaxial structure and semiconductor device

Technical Field

The embodiment of the invention relates to the technical field of semiconductors, in particular to an epitaxial structure of a semiconductor device, a preparation method of the epitaxial structure and the semiconductor device.

Background

The semiconductor material gallium nitride (GaN) has the characteristics of large forbidden bandwidth, high electron mobility, high breakdown field intensity, good heat conduction performance and the like, has very strong spontaneous and piezoelectric polarization effects, is more suitable for manufacturing high-frequency, high-voltage and high-temperature-resistant high-power electronic devices compared with the first-generation semiconductor material and the second-generation semiconductor material, and has obvious advantages especially in the fields of radio frequency and power supply.

The existing GaN-based high electron mobility transistor (High Electron Mobility Transistor, HEMT for short) can realize a high-resistance buffer layer by doping Fe, so that vertical electric leakage can be prevented, and pinch-off performance can be improved.

However, fe has a strong driving force when a Fe-doped GaN high-resistance buffer layer is grown, so that Ga can be replaced to be enriched on the surface. After the Fe source is closed, part of Fe enriched on the surface is incorporated into the crystal lattice when the undoped GaN channel layer is grown, and part of Fe is continuously segregated on the surface, and the doping concentration of Fe gradually decreases along with the increase of the thickness, namely, the tailing effect exists in the GaN channel. The formation of deep level trap trapping electrons as Fe enters the channel layer reduces the Two-dimensional electron gas (Two-Dimensional Electron Gas, 2 DEG) concentration and forms impurity scattering that reduces mobility. That is, the buffer layer doped with Fe may be originally aimed at improving characteristics of the semiconductor device contrary to expected results, thereby degrading the characteristics of the semiconductor device.

Disclosure of Invention

In view of the above, embodiments of the present invention provide an epitaxial structure of a semiconductor device, a method for manufacturing the same, and a semiconductor device, so as to solve the problem of iron atom tailing effect in the prior art and improve the quality of the epitaxial structure and the quality of the semiconductor device.

In a first aspect, an embodiment of the present invention provides an epitaxial structure of a semiconductor device, including:

A substrate;

a buffer layer located on one side of the substrate, the buffer layer including iron atoms;

a barrier structure located on a side of the buffer layer away from the substrate, the barrier structure comprising at least one silicon nitride barrier layer;

a channel structure comprising at least one channel layer, wherein at least one channel layer is positioned on one side of the barrier structure away from the substrate;

the barrier layer is positioned on one side of the channel structure far away from the substrate, and the channel layer and the barrier layer on one side close to the barrier layer form a heterojunction structure;

wherein the channel structure is in contact with both the blocking structure and the buffer layer.

Optionally, the silicon nitride barrier layer includes a plurality of independently disposed island structures.

Optionally, the barrier structure comprises a plurality of layers of the silicon nitride barrier layer, and the channel structure comprises a plurality of layers of the channel layer;

and the silicon nitride barrier layers and the channel layers are sequentially and alternately arranged along the thickness direction of the epitaxial structure.

Optionally, the silicon nitride barrier layer includes a plurality of independently disposed island structures;

the plurality of silicon nitride barrier layers comprise a first silicon nitride barrier layer and a second silicon nitride barrier layer; the first silicon nitride barrier layer comprises a plurality of independently arranged first island structures, and the second silicon nitride barrier layer comprises a plurality of independently arranged second island structures;

Along the thickness direction of the epitaxial structure, at least one first island structure overlaps with the gap between two adjacent second island structures.

Optionally, along the thickness direction of the epitaxial structure, the first island structure and the second island structure are staggered.

Optionally, the epitaxial structure further includes:

a nucleation layer between the substrate and the buffer layer;

And the cap layer is positioned on one side of the barrier layer away from the substrate.

Optionally, the thickness d1 of the silicon nitride barrier layer is 0.1nm or less and d1 or less and 50nm or less along the thickness direction of the epitaxial structure.

Optionally, along the thickness direction of the epitaxial structure, the thickness d2 of the channel structure satisfies d2 less than or equal to 500nm.

In a second aspect, an embodiment of the present invention further provides a method for preparing an epitaxial structure of a semiconductor device, including:

providing a substrate;

preparing a buffer layer, wherein the buffer layer is positioned on one side of the substrate and comprises iron atoms;

Preparing a blocking structure and a channel structure, wherein the blocking structure is positioned on one side of the buffer layer away from the substrate, and the blocking structure comprises at least one silicon nitride blocking layer; the channel structure comprises at least one channel layer, and at least one channel layer is positioned on one side of the blocking structure away from the substrate;

And preparing a barrier layer, wherein the barrier layer is positioned on one side of the channel structure far away from the substrate, and the channel layer and the barrier layer which are close to one side of the barrier layer form a heterojunction structure.

Optionally, preparing the barrier structure includes:

Preparing a buffer layer in a metal organic compound chemical vapor deposition reaction chamber;

and introducing monosilane gas and ammonia gas into the metal organic compound chemical vapor deposition reaction chamber to prepare a blocking structure.

Optionally, preparing the barrier structure includes:

Preparing a buffer layer in a metal organic compound chemical vapor deposition reaction chamber;

preparing a mask structure on the surface of one side of the buffer layer away from the substrate;

and introducing dichlorosilane gas and ammonia gas into the plasma enhanced chemical vapor deposition reaction chamber, and preparing a blocking structure in the exposed area of the mask structure.

Optionally, the barrier structure comprises a plurality of layers of the silicon nitride barrier layer, and the channel structure comprises a plurality of layers of the channel layer;

preparing a barrier structure and a channel structure, comprising:

and sequentially and alternately preparing the silicon nitride barrier layer and the channel layer.

Optionally, before preparing the buffer layer, the method further includes:

preparing a nucleation layer between the substrate and the buffer layer;

After preparing the barrier layer, further comprising:

A cap layer is prepared, the cap layer being located on a side of the barrier layer remote from the substrate.

In a third aspect, an embodiment of the present invention further provides a semiconductor device, including an epitaxial structure of the semiconductor device according to any one of the embodiments of the first aspect;

the semiconductor device further includes:

A source, a gate and a drain on a side of the barrier layer remote from the substrate, the gate being located between the source and the drain.

The epitaxial structure of the semiconductor device, the preparation method of the epitaxial structure and the semiconductor device provided by the embodiment of the invention comprise a substrate, a buffer layer, a blocking structure, a channel structure and a barrier layer. The blocking structure is provided with at least one silicon nitride blocking layer, so that the tailing effect of iron atoms on the channel structure can be reduced, in addition, the silicon nitride blocking layer can promote the growth of a selected area of the gallium nitride epitaxial structure, the dislocation density is reduced, the crystal quality of the channel layer is improved, and the quality of the epitaxial structure and the quality of a semiconductor device are further improved.

Drawings

Fig. 1 is a schematic structural diagram of an epitaxial structure of a semiconductor device according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an epitaxial structure of another semiconductor device according to an embodiment of the present invention;

fig. 3 is a schematic structural view of an epitaxial structure of another semiconductor device according to an embodiment of the present invention;

fig. 4 is a schematic flow chart of a method for preparing an epitaxial structure of a semiconductor device according to an embodiment of the present invention;

Fig. 5 is a schematic flow chart of a method for preparing an epitaxial structure of another semiconductor device according to an embodiment of the present invention;

fig. 6 is a schematic flow chart of a method for preparing an epitaxial structure of another semiconductor device according to an embodiment of the present invention;

Fig. 7 is a schematic flow chart of a method for preparing an epitaxial structure of a semiconductor device according to another embodiment of the present invention;

fig. 8 is a flow chart of a method for preparing an epitaxial structure of a semiconductor device according to another embodiment of the present invention;

Fig. 9 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

Fig. 1 is a schematic structural diagram of an epitaxial structure of a semiconductor device according to an embodiment of the present invention, where, as shown in fig. 1, the epitaxial structure of the semiconductor device according to the embodiment of the present invention includes: a substrate 110; a buffer layer 120 located at one side of the substrate 110, the buffer layer 120 including iron atoms; a barrier structure 130 located on a side of the buffer layer 120 away from the substrate 110, and the barrier structure 130 includes at least one silicon nitride barrier layer 131; a channel structure 140 including at least one channel layer 141, and the at least one channel layer 141 is located at a side of the barrier structure 130 away from the substrate 110; the barrier layer 150 is located on one side of the channel structure 140 away from the substrate 110, and the channel layer on one side close to the barrier layer 150 and the barrier layer 150 form a heterojunction structure; wherein the channel structure 140 is in contact with both the barrier structure 130 and the buffer layer 120.

By way of example, substrate 110 may be one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material capable of growing group III nitrides, and embodiments of the present invention are not limited to a particular type of substrate 110. Further, the substrate 110 may be a material with better heat conduction property, such as silicon carbide.

Illustratively, referring to fig. 1, the buffer layer 120 is located on one side of the substrate 110, the material of the buffer layer 120 may be gallium nitride, and iron atoms may be included in the buffer layer 120, which is beneficial to realizing high resistance of the buffer layer 120, ensuring that vertical leakage can be blocked, and improving pinch-off performance of the semiconductor device. Specifically, the doping concentration of the iron atoms in the buffer layer 120 may be between 1×10 ¹⁷-1*10²¹, so that on one hand, the high resistance performance of the buffer layer 120 is ensured, and on the other hand, the existing doping process is ensured to meet the above doping concentration requirement, and the doping process of the iron atoms is ensured to be simple. Further, the thickness of the buffer layer 120 may be between 100nm and 2000nm, for example, the thickness of the buffer layer 120 is 250nm.

Illustratively, the barrier structure 130 includes at least one silicon nitride barrier layer 131; the channel structure 140 includes at least one channel layer 141, and the material of the channel layer 141 may be gallium nitride; the barrier layer 150 may be an AlGaN barrier layer, and the channel layer 141 near the barrier layer 150 and the barrier layer 150 form a heterojunction structure to form a two-dimensional electron gas arrangement region.

Specifically, the silicon nitride barrier layer 131 may be prepared by using silane gas and ammonia gas, and in addition to depositing the silicon nitride barrier layer 131 on the surface of the buffer layer 120 during the growth of the silicon nitride barrier layer 131, the silane gas has a strong etching effect on the gallium nitride buffer layer 120, and the higher the temperature is, the faster the etching rate of the silane gas is, because the generated stable compound silicon nitride causes the gallium nitride decomposition reaction to proceed in the forward direction. The silicon nitride barrier layer 131 deposited on the surface of the buffer layer simultaneously after the gallium nitride buffer layer is etched by the silane gas can effectively block a part of iron atoms from segregating to the surface of the silicon nitride barrier layer 131. And the bond energy of the Si-N bond is 439KJ/mol, and the bond energy of the Ga-N bond is 103KJ/mol, so that the silicon nitride has strong masking capability on impurity ions, and can effectively block part of iron atoms from segregating to the surface of the silicon nitride barrier layer 131. Therefore, the silicon nitride barrier layer 131 in the barrier structure 130 can reduce the tailing effect of the iron atoms in the channel layer 141, and thus can reduce the thickness of the channel layer 141. Since the channel layer 141 and the barrier layer 150 can form two-dimensional electron gas, the distance of the two-dimensional electron gas from the buffer layer 120 can be reduced by reducing the thickness of the channel layer 141, and thus the concentration of the two-dimensional electron gas in the channel can be increased and the conductive channel can be expanded. A sufficiently thick channel layer 141 is required in the conventional structure to reduce the influence of iron atoms on the two-dimensional electron gas. The addition of the silicon nitride barrier layer 131 achieves the above effects compared to the conventional HEMT epitaxial structure, thereby reducing the thickness of the entire epitaxial structure, further making it easier for the silicon carbide in the substrate 110 to dissipate heat, and reducing thermal resistance.

Further, during the epitaxial growth of the semiconductor material, a large number of surface traps, i.e., dislocations, are generated on the surface of the semiconductor layer due to lattice mismatch, and the silicon nitride barrier layer 131 is more likely to grow at the surface dislocations of the buffer layer 120, thereby preventing the dislocations from further extending toward the surface of the epitaxial structure. Meanwhile, the silicon nitride barrier layer 131 has good insulativity and stability, no matter the silicon atoms or the nitrogen atoms in the silicon nitride barrier layer 131 are, gallium nitride is not easy to nucleate, the channel layer 141 is preferentially grown on the surface of the exposed gallium nitride buffer layer, and the silicon nitride barrier layer 131 plays a role in promoting the selective growth of the gallium nitride epitaxial structure. Lateral growth of the channel layer 141 over the silicon nitride barrier layer 131 causes dislocations in the epitaxial structure to buckle and disappear and not extend upward to the surface of the epitaxial structure.

Furthermore, the silicon nitride material is insulating, and Si atoms can diffuse into the GaN buffer layer and the GaN channel layer in consideration of high temperature in the epitaxial growth process, but the acceptor concentration formed by doping Fe into the buffer layer is far greater than the donor concentration formed by diffusion of Si, so that the high resistance characteristic of the buffer layer is not affected; si diffuses into the GaN channel layer, so that the two-dimensional electron gas concentration in the channel can be increased, and the device performance can be improved.

In summary, in the epitaxial structure of the semiconductor device provided by the embodiment of the invention, at least one silicon nitride barrier layer is arranged on the barrier structure, so that the tailing effect of iron atoms in the channel layer can be reduced; in addition, the silicon nitride barrier layer can promote the selective growth of the gallium nitride epitaxial structure, reduce dislocation density, improve the crystal quality of the channel layer, and further improve the quality of the epitaxial structure and the quality of the semiconductor device.

Optionally, referring to fig. 1, the silicon nitride barrier layer 131 includes a plurality of independently disposed island structures 200.

For example, since the gallium nitride material is not easy to grow on the surface of the silicon nitride, the silicon nitride barrier layer 131 may include a plurality of independently arranged island structures 200, and the buffer layer 120 is exposed in the silicon nitride barrier layers 131 of two adjacent island structures 200, so that it is ensured that the channel structure 140 is easier to grow on the side of the silicon nitride barrier layer 131 away from the substrate 110, and the channel structure 140 is ensured to be simultaneously contacted with the barrier structure 130 and the buffer layer 120, and the epitaxial structure of the semiconductor device is ensured to be normally grown and prepared.

Optionally, fig. 2 is a schematic structural diagram of an epitaxial structure of another semiconductor device according to an embodiment of the present invention, where, as shown in fig. 2, the barrier structure 130 includes a multilayer silicon nitride barrier layer 131, and the channel structure 140 includes a multilayer channel layer 141; the silicon nitride barrier layers 131 and the channel layers 141 are alternately arranged in order in the thickness direction of the epitaxial structure (X direction as shown in the drawing).

Specifically, referring to fig. 2, the silicon nitride barrier layers 131 and the channel layers 141 are alternately arranged in sequence, and the structure of the multi-layer silicon nitride barrier layer 131 can further block the segregation of iron atoms to the surface and filter dislocation, so that the crystal quality of the channel layer 141 is improved, and further the quality of the epitaxial structure and the quality of the semiconductor device are improved.

Optionally, referring to fig. 2, the silicon nitride barrier layer 131 includes a plurality of independently disposed island structures 200; the multilayer silicon nitride barrier layer 131 includes a first silicon nitride barrier layer 1311 and a second silicon nitride barrier layer 1312; the first silicon nitride barrier layer 1311 includes a plurality of independently disposed first island structures 201, and the second silicon nitride barrier layer 1312 includes a plurality of independently disposed second island structures 202; along the thickness direction of the epitaxial structure (X direction as shown in the figure), there is at least one first island structure 201 overlapping with the gap of two adjacent second island structures 202.

Specifically, the existence of the overlapping of the gaps between at least one first island structure 201 and two adjacent second island structures 202 may be understood that the arrangement of the plurality of first island structures 201 in the first silicon nitride barrier layer 1311 and the plurality of second island structures 202 in the second silicon nitride barrier layer 1312 is not exactly the same, that is, not all of the second island structures 202 are disposed directly above the first island structures 201. Further, since the silicon nitride barrier layer 131 is more likely to grow at the dislocation of the gallium nitride surface, the embodiment of the present invention may set at least one first island 201 overlapping with the gaps between two adjacent second islands 202, and may prevent the dislocation from further extending to the surface of the epitaxial structure, that is, may filter the dislocation, and improve the quality of the epitaxial structure and the quality of the semiconductor device.

Optionally, fig. 3 is a schematic structural diagram of an epitaxial structure of another semiconductor device according to an embodiment of the present invention, as shown in fig. 3, in a thickness direction (an X direction as shown in the drawing) of the epitaxial structure, the first island structures 201 and the second island structures 202 are staggered.

Specifically, referring to fig. 3, in the embodiment of the present invention, the first island structure 201 and the second island structure 202 may be staggered, that is, the second island structure 202 overlaps with the gaps between two adjacent first island structures 201, and the first island structure 201 overlaps with the gaps between two adjacent second island structures 202, so that on one hand, the normal growth of the channel layer 141 is ensured, and on the other hand, the overall coverage area of the island structure 200 is ensured to be larger, and the shielding and filtering effects on the position formed in the gallium nitride are good, so that dislocation is prevented from further extending to the surface of the epitaxial structure, that is, dislocation can be filtered, and the quality of the epitaxial structure and the quality of the semiconductor device are improved.

Optionally, referring to fig. 1 to 3, the epitaxial structure further includes: a nucleation layer 160 located between the substrate 110 and the buffer layer 120. A cap layer 170 is located on a side of the barrier layer 150 remote from the substrate 110.

Illustratively, the material of nucleation layer 160 may be aluminum nitride, which is positioned between substrate 110 and buffer layer 120, and serves to adhere the semiconductor material layers that are subsequently grown. Alternatively, the thickness of nucleation layer 160 may be 20nm.

The cap layer 170 has the main functions of reducing the surface state, reducing the surface leakage of the subsequent semiconductor device, and inhibiting the current collapse, thereby improving the performance and reliability of the epitaxial structure and the semiconductor device. Optionally, the material of the cap layer 170 is a group III nitride, such as P-doped gallium nitride (P-GaN), and the P-GaN structure can effectively reduce the barrier height of the barrier layer. Alternatively, the cap layer 170 may have a thickness between 1nm and 10 nm.

Alternatively, referring to FIG. 1, the thickness d1 of the silicon nitride barrier layer 131 satisfies 0.1 nm.ltoreq.d1.ltoreq.50 nm in the thickness direction of the epitaxial structure (X direction as shown in the drawing).

Specifically, since the gallium nitride material is not easy to grow on the surface of the silicon nitride, the thickness d1 of the silicon nitride barrier layer 131 can be accurately controlled between 0.1nm and 50nm, the silicon nitride barrier layer 131 is ensured to comprise a plurality of independently arranged island structures, the phenomenon that the growth of gallium nitride in the channel layer 141 is influenced due to continuous film formation of silicon nitride on the silicon nitride barrier layer 131 can be avoided, and thus the channel structure 140 can be more easily grown on one side of the silicon nitride barrier layer 131 away from the substrate 110, and the normal growth preparation of the epitaxial structure of the semiconductor device is ensured. By way of example, the thickness d1 of the silicon nitride barrier layer 131 may be 30nm.

Alternatively, referring to FIG. 1, the thickness d2 of the channel structure 140 satisfies d2.ltoreq.500 nm in the thickness direction of the epitaxial structure.

Illustratively, with continued reference to fig. 1, the thickness of the channel layer 141 in the channel structure 140 may be between 10nm-500 nm. Alternatively, the thickness of the channel layer 141 may be 100nm,200nm,300nm. The tailing effect of iron atoms in the channel structure is reduced by adding the silicon nitride barrier layer, so that the thickness of the traditional channel layer can be greatly reduced, and the two-dimensional electron gas concentration in the channel can be increased. Therefore, the thickness d2 of the channel structure 140 composed of at least one channel layer 141 is set to satisfy d2.ltoreq.500 nm in the present invention. According to the invention, the silicon nitride barrier layer 131 and the thinned channel layer 141 are added, so that the distance between the two-dimensional electron gas and the buffer layer 120 is smaller than or equal to 600nm and is far smaller than the distance of the conventional structure, the two-dimensional electron gas is closer to the bottom liner 110, the heat dissipation performance is better, in addition, the dislocation density can be reduced when the thickness d2 of the channel structure 140 is smaller, the crystal quality of the channel layer 141 is improved, the quality of an epitaxial structure, the stability and the reliability of a semiconductor device are further improved, and the service life of the semiconductor device is prolonged.

It should be understood that from the perspective of the design of the epitaxial structure of the semiconductor device, the embodiment of the invention reduces the tailing effect of iron atoms in the channel structure and promotes the selective growth of the gallium nitride epitaxial structure by adding the silicon nitride barrier layer, reduces the dislocation density and improves the crystal quality of the channel layer. The semiconductor device includes, but is not limited to: high-power HEMTs operating in high-voltage and high-current environments, silicon-On-Insulator (SOI) structured transistors, gallium arsenide (GaAs) based transistors, and Metal Oxide semiconductor Field effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), metal-Insulator semiconductor Field effect transistors (Metal-Semiconductor Field-Effect Transistor, MISFET), double heterojunction Field effect transistors (Double Heterojunction Field-Effect Transistor, DHFET), junction Field effect transistors (Junction Field-Effect Transistor, MESFET), metal-semiconductor heterojunction Field effect transistors (Metal-Semiconductor Field-Effect Transistor, MESFET), metal-Insulator semiconductor heterojunction Field effect transistors (Metal-Semiconductor Heterojunction Field-Effect Transistor, MISFET), or other Field effect transistors. The semiconductor epitaxial structure and the manufacturing method thereof provided by the invention can be widely applied to the field of manufacturing semiconductor devices such as radio frequency microwaves, power electronics and the like. The gallium nitride electronic device has more obvious advantages on the gallium nitride electronic device with large forbidden bandwidth, high electron mobility, high breakdown field intensity and good heat conduction performance, and can better meet the high-performance requirements of the fields of fast development of electronic communication and the like.

Based on the same inventive concept, the embodiment of the invention also provides a method for preparing an epitaxial structure of a semiconductor device, and fig. 4 is a schematic flow chart of the method for preparing the epitaxial structure of the semiconductor device. As shown in fig. 4, the method for preparing an epitaxial structure of a semiconductor device according to an embodiment of the present invention may include:

S101, providing a substrate.

By way of example, the substrate may be a material with good thermal conductivity, such as silicon carbide. The substrate may be prepared by atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal organic chemical vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical vapor deposition, rapid thermal chemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.

S102, preparing a buffer layer, wherein the buffer layer is positioned on one side of the substrate and comprises iron atoms.

Illustratively, the inclusion of iron atoms in the buffer layer may provide a high resistance buffer layer that may provide for blocking vertical leakage and improving pinch-off performance of the semiconductor device.

By way of example, the buffer layer may be prepared in a metal organic chemical vapor deposition reaction chamber, and by growing the buffer layer by introducing a Ga source and an Fe source, the buffer layer may achieve high resistance by doping iron atoms.

S103, preparing a blocking structure and a channel structure, wherein the blocking structure is positioned on one side of the buffer layer away from the substrate and comprises at least one silicon nitride blocking layer; the channel structure comprises at least one channel layer, and the at least one channel layer is positioned on one side of the barrier structure away from the substrate.

For example, the silicon nitride barrier layer may be prepared by introducing silane gas and ammonia gas, and referring to fig. 1, since the gallium nitride material is not easy to grow on the surface of silicon nitride, the silicon nitride barrier layer 131 may be provided to include a plurality of independently arranged island structures 200, and the silicon nitride on the silicon nitride barrier layer 131 may be prevented from continuously forming a film to affect the growth of gallium nitride in the channel layer 141, so that the channel structure 140 may be more easily grown on the side of the silicon nitride barrier layer 131 away from the substrate 110, and the epitaxial structure of the semiconductor device may be ensured to be normally grown. Further, after the preparation of the barrier structure 130 is completed, the silane gas channel may be closed, the Ga source channel may be opened, and the preparation of the gallium nitride channel structure may be continued.

S104, preparing a barrier layer, wherein the barrier layer is positioned on one side of the channel structure far away from the substrate, and the channel layer and the barrier layer on one side close to the barrier layer form a heterojunction structure.

And forming a heterojunction structure through the channel layer and the barrier layer to form a motion channel of the two-dimensional electron gas.

According to the preparation method of the epitaxial structure, provided by the embodiment of the invention, at least one silicon nitride barrier layer is arranged on the barrier structure, so that the tailing effect of iron atoms in a channel layer can be reduced; in addition, the silicon nitride barrier layer can promote the selective growth of the gallium nitride epitaxial structure, reduce dislocation density, improve the crystal quality of the channel layer, and further improve the quality of the epitaxial structure and the quality of the semiconductor device.

On the basis of the above embodiment, the embodiment of the present invention further provides a method for preparing an epitaxial structure of another semiconductor device, and fig. 5 is a schematic flow chart of a method for preparing an epitaxial structure of another semiconductor device according to the embodiment of the present invention. As shown in fig. 5, the method for preparing an epitaxial structure of a semiconductor device according to an embodiment of the present invention may include:

s201, providing a substrate.

S202, preparing a buffer layer in a metal organic compound chemical vapor deposition reaction chamber.

By way of example, high resistance can be achieved by doping iron atoms when preparing the buffer layer in a metal organic chemical vapor deposition reaction chamber.

S203, introducing monosilane gas and ammonia gas into the metal organic compound chemical vapor deposition reaction chamber to prepare a blocking structure.

Illustratively, after the buffer layer is prepared, the iron source and the gallium source are closed, monosilane gas and ammonia gas are introduced into the metal organic compound chemical vapor deposition reaction chamber, and a silicon nitride barrier layer of 0.1nm-50nm can be grown on the buffer layer. The reaction chamber temperature can be controlled between 800 ℃ and 1100 ℃. Alternatively, the reaction chamber temperature is controlled at 900 ℃. The growth rate of silicon nitride can be controlled by temperature, monosilane gas concentration, ammonia partial pressure, hydrogen partial pressure, or the like.

S204, preparing a channel structure in the metal organic compound chemical vapor deposition reaction chamber.

After the preparation of the blocking structure is completed, monosilane gas is closed, the temperature is raised to 1100 ℃, and a gallium arsenide source is opened, so that a gallium nitride channel layer can be grown on the silicon nitride blocking layer, and the thickness of the gallium nitride channel layer can be 10nm-500nm.

S205, preparing a barrier layer in the metal organic compound chemical vapor deposition reaction chamber, wherein the barrier layer is positioned on one side of the channel structure far away from the substrate, and the channel layer and the barrier layer on one side close to the barrier layer form a heterojunction structure.

According to the preparation method of the epitaxial structure, provided by the embodiment of the invention, the buffer layer and the blocking structure are prepared in the metal organic compound chemical vapor deposition reaction chamber, so that the pollution problem caused by transfer in the preparation process of the epitaxial structure can be avoided, and the quality and the performance of the whole epitaxial structure are ensured.

Fig. 6 is a schematic flow chart of a method for preparing an epitaxial structure of a semiconductor device according to another embodiment of the present invention. As shown in fig. 6, a method for preparing an epitaxial structure of a semiconductor device according to an embodiment of the present invention may include:

S301, providing a substrate.

S302, preparing a buffer layer in a metal organic compound chemical vapor deposition reaction chamber.

S303, preparing a mask structure on the surface of one side of the buffer layer away from the substrate.

Illustratively, the material of the mask structure may be photoresist.

S304, introducing dichlorosilane gas and ammonia gas into the plasma enhanced chemical vapor deposition reaction chamber, and preparing a blocking structure in the exposed area of the mask structure.

The epitaxial structure with the high-resistance buffer layer grown is cooled, placed in an ion-enhanced chemical vapor deposition reaction chamber, and ammonia gas and dichlorosilane gas are introduced, so that a silicon nitride barrier layer with the thickness of 0.1-50 nm can be grown in the exposed area of the mask structure, and the growth position of the silicon nitride barrier layer with the island-shaped structure can be selected according to requirements.

S305, preparing a channel structure in a metal organic compound chemical vapor deposition reaction chamber.

And (3) putting the epitaxial structure containing the silicon nitride barrier layer into the metal organic compound chemical vapor deposition reaction chamber again, heating to 1100 ℃, and opening a gallium arsenide source to grow a gallium nitride channel layer on the silicon nitride barrier layer, wherein the thickness of the gallium nitride channel layer is 100-500 nm.

S306, preparing a barrier layer in the metal organic compound chemical vapor deposition reaction chamber, wherein the barrier layer is positioned on one side of the channel structure far away from the substrate, and the channel layer on one side close to the barrier layer and the barrier layer form a heterojunction structure.

According to the preparation method of the epitaxial structure, provided by the embodiment of the invention, the buffer layer is prepared in the metal organic compound chemical vapor deposition reaction chamber, dichlorosilane gas and ammonia gas are introduced into the plasma enhanced chemical vapor deposition reaction chamber, and the barrier structure is prepared in the exposed area of the mask structure, so that the island structure can be selectively grown, the barrier structure can be selectively prepared according to the requirements, and the epitaxial structure of the semiconductor device and the semiconductor device can meet the use requirements.

Fig. 7 is a schematic flow chart of a method for preparing an epitaxial structure of a semiconductor device according to an embodiment of the present invention. As shown in fig. 7, the method for preparing an epitaxial structure of a semiconductor device according to an embodiment of the present invention may include:

S401, providing a substrate.

S402, preparing a buffer layer, wherein the buffer layer is positioned on one side of the substrate and comprises iron atoms.

S403, alternately preparing a silicon nitride barrier layer and a channel layer in sequence.

Specifically, the silicon nitride barrier layer and the channel layer are alternately arranged in sequence, namely, a plurality of periods of silicon nitride barrier layer and channel layer are formed on the buffer layer, and the silicon nitride barrier layer and the channel layer are alternately arranged in sequence. The number of cycles may be, for example, 1-50. Preferably, in the multicycle alternating structure, the thickness of the single-layer silicon nitride barrier layer is less than or equal to 9nm, for example, the thickness of the single-layer silicon nitride barrier layer is 3nm.

Specifically, the silicon nitride barrier layer and the channel layer can both be prepared in a metal organic chemical vapor deposition reaction chamber; alternatively, the silicon nitride barrier layer may be prepared in a plasma enhanced chemical vapor deposition reaction chamber, and the channel layer may be prepared in a metal organic chemical vapor deposition reaction chamber, and the various preparation processes have been described in the above embodiments, and are not repeated here.

When both the silicon nitride barrier layer and the channel layer are prepared in the metal organic chemical vapor deposition reaction chamber, the positions of the silicon nitride barrier layers of the island structures are randomly distributed, as shown in fig. 2, that is, there is a gap overlapping between at least one first island structure and two adjacent second island structures, so that the dislocation can be prevented from further extending to the surface of the epitaxial structure, that is, the dislocation can be filtered, and the quality of the epitaxial structure and the quality of the semiconductor device are improved.

When the silicon nitride barrier layer is prepared in the plasma enhanced chemical vapor deposition reaction chamber, and the channel layer is prepared in the metal organic compound chemical vapor deposition reaction chamber, the silicon nitride barrier layer with the island structure can be prepared at a specific position according to requirements, for example, the silicon nitride barrier layer with the island structure is prepared at a region with larger dislocation density, as shown in fig. 3, the first island structure and the second island structure are staggered, the second island structure overlaps with a gap between two adjacent first island structures, and the first island structure overlaps with a gap between two adjacent second island structures, so that the normal growth of the channel layer is ensured, the whole coverage area of the island structure is ensured to be larger, and the shielding and filtering effects on the position formed in gallium nitride are good, thereby preventing dislocation from extending further to the surface of the epitaxial structure, namely, dislocation can be filtered, and the quality of the epitaxial structure and the quality of a semiconductor device are improved.

It should be noted that, in order to avoid the contamination of the epitaxial structure during the mutual transfer between the metal organic chemical vapor deposition reaction chamber and the plasma enhanced chemical vapor deposition reaction chamber, there may be two layers of the silicon nitride barrier layer and the channel layer in general.

S404, preparing a barrier layer, wherein the barrier layer is positioned on one side of the channel structure far away from the substrate, and the channel layer and the barrier layer on one side close to the barrier layer form a heterojunction structure.

According to the preparation method of the epitaxial structure, the silicon nitride barrier layers and the channel layers are sequentially and alternately arranged, so that segregation of iron atoms to the surface and dislocation filtration can be further prevented, the crystal quality of the channel layers is improved, and further the quality of the epitaxial structure and the quality of a semiconductor device are improved.

Fig. 8 is a flow chart of a method for preparing an epitaxial structure of a semiconductor device according to another embodiment of the present invention. As shown in fig. 8, a method for preparing an epitaxial structure of a semiconductor device according to an embodiment of the present invention may include:

s501, providing a substrate.

S502, preparing a nucleation layer, wherein the nucleation layer is positioned between the substrate and the buffer layer.

By way of example, the substrate is subjected to a high temperature treatment in a hydrogen atmosphere at a temperature of 1050-1200 c for 10-20 min, whereby an aluminum nitride nucleation layer having a thickness of 5-200 nm may be grown on the substrate, which may serve to adhere the next semiconductor material layer to be grown. Alternatively, the thickness of nucleation layer 160 may be 20nm.

S503, preparing a buffer layer, wherein the buffer layer is positioned on one side of the substrate and comprises iron atoms.

S504, preparing a blocking structure and a channel structure, wherein the blocking structure is positioned on one side of the buffer layer away from the substrate, and comprises at least one silicon nitride blocking layer; the channel structure comprises at least one channel layer, and the at least one channel layer is positioned on one side of the barrier structure away from the substrate.

S505, preparing a barrier layer, wherein the barrier layer is positioned on one side of the channel structure far away from the substrate, and the channel layer and the barrier layer on one side close to the barrier layer form a heterojunction structure.

S506, preparing a cap layer, wherein the cap layer is positioned on one side of the barrier layer away from the substrate.

Illustratively, a gallium nitride cap layer is grown on the barrier layer to a thickness of 1nm to 10 nm. The cap layer has the main functions of reducing the surface state, reducing the surface leakage of the subsequent semiconductor device and inhibiting the current collapse, thereby improving the performance and the reliability of the epitaxial structure and the semiconductor device.

According to the preparation method of the epitaxial structure, provided by the embodiment of the invention, the nucleation layer is prepared to be capable of adhering the effect of the semiconductor material layer to be grown next and reducing the surface state, and the cap layer is prepared to be capable of reducing the surface leakage of the subsequent semiconductor device and inhibiting the current collapse, so that the performance and the reliability of the epitaxial structure and the semiconductor device are improved.

Based on the same inventive concept, the embodiment of the present invention further provides a semiconductor device, including the epitaxial structure of the semiconductor device according to the embodiment of the present invention, and fig. 9 is a schematic structural diagram of the semiconductor device according to the embodiment of the present invention, where, as shown in fig. 9, the semiconductor device further includes:

a source 210, a gate 220, and a drain 230 on a side of the barrier layer 150 remote from the substrate 110, the gate 220 being located between the source 210 and the drain 230.

Illustratively, the source 210 and drain 230 form ohmic contacts with the barrier layer 150, respectively; the gate 220 is located between the source 210 and the drain 230 while the cap layer 170 is located on a side away from the substrate 110, the gate 220 forming a schottky contact with the cap layer 170.

The semiconductor device provided in the embodiment of the present invention includes the epitaxial structure in the above embodiment, so the semiconductor device provided in the embodiment of the present invention also has the beneficial effects described in the above embodiment, and is not described herein again.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (14)

1. An epitaxial structure of a semiconductor device, comprising:

A substrate;

a buffer layer located on one side of the substrate, the buffer layer including iron atoms;

a barrier structure located on a side of the buffer layer away from the substrate, the barrier structure comprising at least one silicon nitride barrier layer;

a channel structure comprising at least one channel layer, wherein at least one channel layer is positioned on one side of the barrier structure away from the substrate;

the barrier layer is positioned on one side of the channel structure far away from the substrate, and the channel layer and the barrier layer on one side close to the barrier layer form a heterojunction structure;

Wherein the channel structure is in contact with both the blocking structure and the buffer layer.

2. The epitaxial structure of claim 1, wherein the silicon nitride barrier layer comprises a plurality of independently disposed island structures.

3. The epitaxial structure of claim 1 wherein the barrier structure comprises a plurality of layers of the silicon nitride barrier layer and the channel structure comprises a plurality of layers of the channel layer;

and the silicon nitride barrier layers and the channel layers are sequentially and alternately arranged along the thickness direction of the epitaxial structure.

4. The epitaxial structure of claim 3 wherein the silicon nitride barrier layer comprises a plurality of independently disposed island structures;

the plurality of silicon nitride barrier layers comprise a first silicon nitride barrier layer and a second silicon nitride barrier layer; the first silicon nitride barrier layer comprises a plurality of independently arranged first island structures, and the second silicon nitride barrier layer comprises a plurality of independently arranged second island structures;

Along the thickness direction of the epitaxial structure, at least one first island structure overlaps with the gap between two adjacent second island structures.

5. The epitaxial structure of claim 4, wherein the first island-like structures are offset from the second island-like structures along a thickness direction of the epitaxial structure.

6. The epitaxial structure of claim 1, wherein the epitaxial structure further comprises:

a nucleation layer between the substrate and the buffer layer;

And the cap layer is positioned on one side of the barrier layer away from the substrate.

7. The epitaxial structure of claim 1, wherein a thickness d1 of the silicon nitride barrier layer satisfies 0.1nm +.d1 +.50nm along a thickness direction of the epitaxial structure.

8. The epitaxial structure of claim 1, wherein a thickness d2 of the channel structure in a thickness direction of the epitaxial structure satisfies d2.ltoreq.500 nm.

9. A method for fabricating an epitaxial structure of a semiconductor device, comprising:

providing a substrate;

preparing a buffer layer, wherein the buffer layer is positioned on one side of the substrate and comprises iron atoms;

Preparing a blocking structure and a channel structure, wherein the blocking structure is positioned on one side of the buffer layer away from the substrate, and the blocking structure comprises at least one silicon nitride blocking layer; the channel structure comprises at least one channel layer, and at least one channel layer is positioned on one side of the blocking structure away from the substrate;

And preparing a barrier layer, wherein the barrier layer is positioned on one side of the channel structure far away from the substrate, and the channel layer and the barrier layer which are close to one side of the barrier layer form a heterojunction structure.

10. The method of manufacturing according to claim 9, wherein manufacturing the barrier structure comprises:

Preparing a buffer layer in a metal organic compound chemical vapor deposition reaction chamber;

and introducing monosilane gas and ammonia gas into the metal organic compound chemical vapor deposition reaction chamber to prepare a blocking structure.

11. The method of manufacturing according to claim 9, wherein manufacturing the barrier structure comprises:

Preparing a buffer layer in a metal organic compound chemical vapor deposition reaction chamber;

preparing a mask structure on the surface of one side of the buffer layer away from the substrate;

and introducing dichlorosilane gas and ammonia gas into the plasma enhanced chemical vapor deposition reaction chamber, and preparing a blocking structure in the exposed area of the mask structure.

12. The method of manufacturing of claim 9, wherein the barrier structure comprises a plurality of layers of the silicon nitride barrier layer and the channel structure comprises a plurality of layers of the channel layer;

preparing a barrier structure and a channel structure, comprising:

and sequentially and alternately preparing the silicon nitride barrier layer and the channel layer.

13. The method of manufacturing according to claim 9, further comprising, before the step of manufacturing the buffer layer:

preparing a nucleation layer between the substrate and the buffer layer;

After preparing the barrier layer, further comprising:

A cap layer is prepared, the cap layer being located on a side of the barrier layer remote from the substrate.

14. A semiconductor device comprising the epitaxial structure of any one of claims 1-8;

the semiconductor device further includes:

A source, a gate and a drain on a side of the barrier layer remote from the substrate, the gate being located between the source and the drain.