CN117954441A - Electrostatic discharge protection device - Google Patents
Electrostatic discharge protection device Download PDFInfo
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- CN117954441A CN117954441A CN202211348176.7A CN202211348176A CN117954441A CN 117954441 A CN117954441 A CN 117954441A CN 202211348176 A CN202211348176 A CN 202211348176A CN 117954441 A CN117954441 A CN 117954441A
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- 230000003071 parasitic effect Effects 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 238000002955 isolation Methods 0.000 claims description 14
- 238000007599 discharging Methods 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 abstract 3
- 230000005611 electricity Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 3
- 238000010531 catalytic reduction reaction Methods 0.000 description 2
- 230000001808 coupling effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- 238000006722 reduction reaction Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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Abstract
The invention provides an electrostatic discharge protection device. The electrostatic discharge protection device comprises a substrate and a grid structure positioned on the substrate, wherein a first well region and a second well region which are connected are formed in the substrate, the first well region is provided with a first conduction type, the second well region is provided with a second conduction type, the grid structure spans from the upper part of a part of the substrate of the first well region to the upper part of a part of the substrate of the second well region, a first doping region and a second doping region which are positioned on one side of the grid structure are formed on the top of the substrate of the first well region, the first doping region is provided with the first conduction type, the second doping region is provided with the second conduction type, a third doping region and a fourth doping region which are positioned on the other side of the grid structure are formed on the top of the substrate of the second well region, and the third doping region is provided with the first conduction type. Therefore, the first parasitic triode and the second parasitic triode for discharging static electricity can be formed in the static discharge protection device, and the static discharge capacity of the circuit is improved.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and in particular, to an electrostatic discharge protection device.
Background
The electrostatic discharge (Electro-STATIC DISCHARGE, ESD) phenomenon refers to a charge transfer phenomenon that occurs when objects having different electric potentials come close to or come into contact with each other. With the continuous reduction of the size of semiconductor manufacturing processes and the continuous expansion of the scale of integrated circuits, chips are increasingly subject to electrostatic damage during production, transportation and use. Therefore, research into electrostatic discharge protection is of great importance.
Currently, some high voltage applications have higher voltages, and there is a higher demand for electrostatic discharge protection of Integrated Circuits (ICs). However, the conventional electrostatic discharge protection structure has insufficient electrostatic discharge capability.
Disclosure of Invention
The invention aims to provide an electrostatic discharge protection device which can improve the electrostatic discharge capacity of a circuit and meet the electrostatic discharge protection requirement of a high-voltage device.
In order to achieve the above object, the present invention provides an electrostatic discharge protection device including a substrate and a gate structure on the substrate; a first well region and a second well region which are connected are formed in the substrate, wherein the first well region has a first conductivity type, and the second well region has a second conductivity type opposite to the first conductivity type; the gate structure spans from above a portion of the base of the first well region to above a portion of the base of the second well region; a first doped region and a second doped region are formed at the top of the substrate of the first well region, the first doped region and the second doped region are positioned at one side of the gate structure, the first doped region has a first conductivity type, and the second doped region has a second conductivity type; a third doped region and a fourth doped region are formed at the top of the substrate of the second well region, the third doped region and the fourth doped region are positioned at the other side of the gate structure, the third doped region has a first conductivity type, and the fourth doped region has a second conductivity type; the first doped region and the second doped region are electrically connected to a first potential terminal, and the gate structure and the third doped region are electrically connected to a second potential terminal.
Optionally, the first well region, the second well region and the third doped region form a first parasitic triode; the second doped region, the first well region and the second well region form a second parasitic triode; the first parasitic transistor and the second parasitic transistor share the first well region and the second well region and are commonly used for electrostatic discharge.
Optionally, the first well region, the second well region and the third doped region are respectively used as a collector, a base and an emitter of the first parasitic triode; the second well region, the first well region and the second doped region are respectively used as a collector, a base and an emitter of the second parasitic triode.
Optionally, the first doped region and the second doped region are arranged along a width direction of the conductive channel under the gate structure.
Optionally, the second doped region is formed at two ends of the first doped region.
Optionally, the third doped region is located between the gate structure and the fourth doped region, and the third doped region and the fourth doped region are elongated along a width direction of the conductive trench under the gate structure.
Optionally, an isolation structure is formed on the top of the substrate between the gate structure and the first doped region, the top of the substrate between the gate structure and the second doped region, and the top of the substrate between the first doped region and the second doped region; and/or an isolation structure is formed on the top of the substrate between the third doped region and the fourth doped region.
Optionally, the first sidewall of the gate structure is in contact with the isolation structure, and the second sidewall of the gate structure is in contact with the third doped region.
Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.
Optionally, the first potential end is an anode end, and the second potential end is a cathode end.
The invention provides an electrostatic discharge protection device which comprises a substrate and a grid structure positioned on the substrate, wherein a first well region and a second well region which are connected are formed in the substrate, the first well region has a first conduction type, and the second well region has a second conduction type opposite to the first conduction type; the gate structure spans from above a portion of the base of the first well region to above a portion of the base of the second well region; a first doped region and a second doped region are formed at the top of the substrate of the first well region, the first doped region and the second doped region are positioned at one side of the gate structure, the first doped region has a first conductivity type, and the second doped region has a second conductivity type; and a third doped region and a fourth doped region are formed at the top of the substrate of the second well region, the third doped region and the fourth doped region are positioned at the other side of the gate structure, the third doped region has a first conductivity type, and the fourth doped region has a second conductivity type. Therefore, the first parasitic triode can be formed by the first well region, the second well region and the third doped region, the second parasitic triode can be formed by the second doped region, the first well region and the second well region, the first parasitic triode and the second parasitic triode share the first well region and the second well region to be connected with each other, the first parasitic triode can trigger the second parasitic triode to be conducted, and then an SCR (selective catalytic reduction) passage with higher electrostatic discharge capacity is formed, the electrostatic discharge capacity of a circuit is improved, and the electrostatic discharge protection requirement of a high-voltage device is met.
Drawings
Fig. 1 is a top view of an LDMOS for ESD protection.
Fig. 2 is a cross-sectional view of the LDMOS shown in fig. 1 and a schematic diagram of an equivalent triode circuit inside the LDMOS.
Fig. 3 is a current-voltage plot of an LDMOS for ESD protection.
Fig. 4 is a top view of an esd protection device according to an embodiment of the invention.
Fig. 5 is a cross-sectional view of the esd protection device shown in fig. 4 along the BB line and a schematic diagram of an equivalent triode circuit therein.
Fig. 6 is a cross-sectional view of the esd protection device shown in fig. 4 along line CC and a schematic diagram of an equivalent triode circuit therein.
Fig. 7 is a current-voltage diagram of an esd protection device according to an embodiment of the invention.
Reference numerals illustrate:
(FIGS. 1-2) 101-N-well; 102-P well; 103-gate; 104-a first n+ region;
(fig. 4-6) 200-substrate; 201-a first well region; 202-a second well region; 203-a first doped region; 204-a second doped region; 205-a third doped region; 206-a fourth doped region; 207-isolation structures; 300-gate structure.
Detailed Description
In integrated circuits, ESD protection structures are typically used between an Anode (Anode) and a Cathode (Cathode), and are typically of the same type as the circuit to be protected, e.g., high voltage LDMOS circuits are used to protect LDMOS circuits in high voltage applications.
Fig. 1 is a top view of an LDMOS for ESD protection. Fig. 2 is a cross-sectional view of the LDMOS shown in fig. 1 and a schematic diagram of an equivalent triode circuit inside the LDMOS. Fig. 2 is a cross-sectional view taken along line AA in fig. 1, and the LDMOS shown in fig. 1 and 2 is of N-type.
Referring to fig. 1 and 2, a parasitic NPN transistor T1 is formed between an N-well 101 (N-well), a P-well 102 (P-well), and a first n+ region 104 of the LDMOS, wherein the N-well 101 is a collector of T1, the P-well 102 is a base of T1, and the first n+ region 104 is an emitter of T1. When a positive ESD pulse is applied to the anode, the reverse PN junction of the N-well 101 and the P-well 102 forms a leakage current, and the ESD pulse can also cause the voltage of the gate 103 to rise instantaneously through the coupling effect of the parasitic capacitance, so that an inversion layer is formed on the surface layer of the substrate under the gate 103. Therefore, as the anode terminal voltage increases, the leakage current also becomes larger.
Fig. 3 is a current-voltage plot of an LDMOS for ESD protection. Referring to fig. 1 to 3, when the leakage current is large to a certain value, the base-emitter of the parasitic NPN transistor T1 is forward biased, the parasitic NPN transistor T1 is turned on to form a current from the anode to the cathode, corresponding to the trigger point (Vt 1, it 1) of fig. 3, so as to bleed the ESD current and protect the protected circuit. After the trigger of the parasitic NPN tube T1, the LDMOS can generate a quick hysteresis phenomenon (snapback), after the voltage returns to the holding voltage Vh, the LDMOS continues to discharge along with the further rising of the ESD pulse, and the voltage at two ends rises along with the further rising, so that the LDMOS burns out after reaching the breakdown voltage Vt 2.
In addition, LDMOS is used for ESD protection, and a parallel multi-finger structure is generally adopted, which can increase the total device width. However, since the high voltage characteristic of the high voltage LDMOS determines that the trigger voltage Vt1 of the parasitic NPN transistor T1 is higher, the transistor of the parallel multi-finger structure near the middle part is usually turned on more easily, and the hysteresis phenomenon will occur immediately once some of the interdigital transistors are turned on, the voltage of the LDMOS decreases rapidly until reaching the breakdown voltage Vt2, and other interdigital transistors that have not been turned on are difficult to turn on, so that the electrostatic discharge capability of the LDMOS for ESD protection is poor, and the ESD protection requirement of the high voltage device cannot be met.
In order to improve the electrostatic discharge capability of a circuit and meet the ESD protection requirement of a high-voltage device, the invention provides an electrostatic discharge protection device. The electrostatic discharge protection device includes a substrate and a gate structure on the substrate. A first well region and a second well region which are connected are formed in the substrate, wherein the first well region has a first conductivity type, and the second well region has a second conductivity type opposite to the first conductivity type; the gate structure spans from above a portion of the base of the first well region to above a portion of the base of the second well region. A first doped region and a second doped region are formed at the top of the substrate of the first well region, the first doped region and the second doped region are positioned at one side of the gate structure, the first doped region has a first conductivity type, and the second doped region has a second conductivity type; and a third doped region and a fourth doped region are formed at the top of the substrate of the second well region, the third doped region and the fourth doped region are positioned at the other side of the gate structure, the third doped region has a first conductivity type, and the fourth doped region has a second conductivity type. The first doped region and the second doped region are electrically connected to a first potential terminal, and the gate structure and the third doped region are electrically connected to a second potential terminal.
In the electrostatic discharge protection device, the first well region, the second well region and the third doped region can form a first parasitic triode, the second doped region, the first well region and the second well region can form a second parasitic triode, the first parasitic triode and the second parasitic triode share the first well region and the second well region so as to be connected with each other, the first parasitic triode can trigger the second parasitic triode to be conducted, and then an SCR (Silicon Controlled Rectifier, chinese is called silicon controllable) passage with stronger electrostatic discharge capacity is formed, the electrostatic discharge capacity of a circuit is improved, and the electrostatic discharge protection requirement of a high-voltage device is met.
The electrostatic discharge protection device according to the present invention is described in further detail below with reference to the accompanying drawings and specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 4 is a top view of an esd protection device according to an embodiment of the invention. Fig. 5 is a cross-sectional view of the esd protection device shown in fig. 4 along the BB line and a schematic diagram of an equivalent triode circuit therein. Fig. 6 is a cross-sectional view of the esd protection device shown in fig. 4 along line CC and a schematic diagram of an equivalent triode circuit therein.
As shown in fig. 4 to 6, the electrostatic discharge protection device includes a substrate 200 and a gate structure 300 on the substrate 200.
The substrate 200 has a first well region 201 and a second well region 202 formed therein, which are connected, for example, in the horizontal direction of fig. 5 and 6, the boundary of the first well region 201 is connected to the boundary of the second well region 202, the first well region 201 has a first conductivity type, and the second well region 202 has a second conductivity type opposite to the first conductivity type.
The substrate 200 may be a silicon substrate, but is not limited thereto. The substrate 200 may also be a germanium substrate, a silicon on insulator (Silicon On Insulator, SOI), a germanium on insulator (Germanium On Insulator, GOI), etc., and certain doping particles may be implanted into the substrate 200 to change electrical parameters according to design requirements.
The gate structure 300 spans from above a portion of the substrate of the first well region 201 to above a portion of the substrate of the second well region 202, i.e., the gate structure 300 is located at the junction of the first well region 201 and the second well region 202, and the gate structure 300 covers a portion of the substrate of the first well region 201 and a portion of the substrate of the second well region 202. The gate structure 300 may include a gate oxide layer (not shown) over the substrate 200 and a gate electrode (not shown) on the gate oxide layer. The material of the gate oxide layer may include silicon oxide, and the gate electrode may be a polysilicon gate electrode, but is not limited thereto.
As shown in fig. 4 to 6, a first doped region 203 and a second doped region 204 are formed on top of the substrate of the first well region 201, the first doped region 203 and the second doped region 204 are located at one side of the gate structure 300, the first doped region 203 has a first conductivity type, and the second doped region 204 has a second conductivity type; a third doped region 205 and a fourth doped region 206 are formed on top of the substrate of the second well region 202, the third doped region 205 and the fourth doped region 206 are located on the other side of the gate structure 300, the third doped region 205 has the first conductivity type, and the fourth doped region 206 has the second conductivity type. The first doped region 203 and the second doped region 204 are electrically connected to a first potential terminal, and the gate structure 300 and the third doped region 205 are electrically connected to a second potential terminal.
In this embodiment, the first conductivity type may be N-type, and the second conductivity type may be P-type, but is not limited thereto.
As an example, the first well region 201 is an N-well (N-well), the second well region 202 is a P-well (P-well), the first doped region 203 and the third implanted region 205 are n+ implanted regions, and the second implanted region 204 and the fourth implanted region 206 are p+ implanted regions. The first well region 201, the second well region 202, the first doped region 203, the second doped region 204, the third doped region 204, and the fourth doped region 205 may all be formed by implanting dopant species in the substrate 200.
The first potential terminal may be an Anode terminal (Anode) and the second potential terminal may be a Cathode terminal (Cathode), but is not limited thereto.
As shown in fig. 5, the first well region 201, the second well region 202 and the third doped region 205 form a first parasitic transistor T1, and the first well region 201, the second well region 202 and the third doped region 205 serve as a collector, a base and an emitter of the first parasitic transistor T1, respectively. In one embodiment of the present invention, the first parasitic transistor T1 is an NPN transistor.
As shown in fig. 6, the second doped region 204, the first well region 201 and the second well region 202 form a second parasitic transistor T2, and the second well region 202, the first well region 201 and the second doped region 204 serve as a collector, a base and an emitter of the second parasitic transistor T2, respectively. In one embodiment of the present invention, the second parasitic transistor T2 is a PNP transistor.
As shown in fig. 4 to 6, the first parasitic transistor T1 and the second parasitic transistor T2 share the first well region 201 and the second well region 202, that is, the collector of the first parasitic transistor T1 and the base of the second parasitic transistor T2 share, the base of the first parasitic transistor T1 and the collector of the second parasitic transistor T2 share, which is represented in the circuit diagram by the connection of the collector of the first parasitic transistor T1 and the base of the second parasitic transistor T2, and the base of the first parasitic transistor T1 and the collector of the second parasitic transistor T2. The first parasitic transistor T1 and the second parasitic transistor T2 are commonly used for electrostatic discharge.
Fig. 7 is a current-voltage diagram of an esd protection device according to an embodiment of the invention. Referring to fig. 4 to 7, when an Anode terminal (Anode) has a positive ESD pulse, the reverse PN junction of the first well region 201 and the second well region 202 forms a leakage current, and the ESD pulse can also cause the voltage of the gate structure 300 to be instantaneously raised by the coupling effect of the parasitic capacitance, thereby forming an inversion layer on the surface layer of the substrate under the gate structure 300. Therefore, as the anode terminal voltage increases, the leakage current also becomes larger. When the leakage current is large to a certain value, the base-emitter electrode of the first parasitic triode T1 is forward biased, the first parasitic triode T1 is conducted to form a current from the anode to the cathode, and the current corresponds to the trigger point (Vt 1, it 1) of FIG. 7, so that the ESD current is discharged, and the protected circuit is protected.
After the first parasitic transistor T1 is triggered, a quick hysteresis phenomenon occurs in the esd protection device, and the voltage returns to the holding voltage Vh. With further rising of the ESD pulse, the first parasitic transistor T1 continues to discharge, the collector current of the first parasitic transistor T1 is fed back to the base of the second parasitic transistor T2, so that the base-emitter of the second parasitic transistor T2 is forward biased, and thus the second parasitic transistor T2 is turned on, corresponding to the second trigger point (Vt 1 ', it1 ') of fig. 7, at this time, the SCR path of PNPN is formed, and a secondary hysteresis phenomenon occurs, and the voltage of the ESD protection structure returns to the holding voltage Vh '. Then, as the ESD pulse increases, most of the ESD current rapidly bleeds out through the SCR path until the second breakdown point (Vt 2, it 2) is reached.
It should be noted that, the ESD protection structure of the present invention is a secondary triggering device, and a second parasitic transistor T2 connected to the first parasitic transistor T1 is embedded on the basis of a conventional LDMOS device for ESD to form an SCR path in the ESD protection structure. When the ESD pulse is increased, the first parasitic triode T1 is triggered to discharge part of ESD current, and the electrostatic discharge protection device is subjected to a first hysteresis phenomenon; when the ESD pulse is further increased, the second parasitic triode T2 is triggered to be conducted to form an SCR (selective catalytic reduction) path, and a second hysteresis phenomenon occurs, and when the ESD pulse is further increased, the ESD current is discharged in an auxiliary mode through the SCR path until a secondary breakdown point of the electrostatic discharge protection device is reached.
Because the ESD protection capability of the unit area of the SCR structure formed by connecting the first parasitic triode T1 and the second parasitic triode T2 is far higher than that of the LDMOS, the ESD protection device is embedded into the second parasitic triode on the basis of the traditional LDMOS device for ESD, and the capability of discharging ESD current of the ESD protection device can be greatly increased.
As shown in fig. 4, the gate structure 300 may be elongated along the X direction, and the width direction of the conductive channel under the gate structure 300 may be the X direction, and the first doped region 203 and the second doped region 204 may be arranged along the width direction of the conductive channel under the gate structure 300. In the Y direction, the widths of the first doped region 203 and the second doped region 204 may be the same, and the ends of the first doped region 203 and the second doped region 204 are aligned, which helps to reduce the size of the esd protection device, but is not limited thereto.
In this embodiment, as shown in fig. 4, the second doped regions 204 may be formed at two ends of the first doped region 203 in the X direction, which is beneficial to improving the discharge uniformity of the esd protection device, but is not limited thereto. In other embodiments, the second doped region 204 may be provided at only one end of the first doped region 203 in the X direction.
As shown in fig. 4 and 5, in the Y direction, the third doped region 205 may be located between the gate structure 300 and the fourth doped region 206, and the third doped region 205 and the fourth doped region 206 may be elongated in a width direction of a conductive channel under the gate structure 300.
As shown in fig. 4 to 6, an isolation structure 207 is formed on the top of the substrate between the gate structure 300 and the first doped region 203, on the top of the substrate between the gate structure 300 and the second doped region 204, and on the top of the substrate between the first doped region 203 and the second doped region 204. An isolation structure 207 may also be formed on top of the substrate between the third doped region 205 and the fourth doped region 206. The isolation structure 207 may be a Field Oxide (FOX) or a Shallow Trench Isolation (STI) using a LOCOS (local oxidation of silicon) process.
A first sidewall of the gate structure 300 is in contact with the isolation structure 207, and a second sidewall of the gate structure 300 is in contact with the third doped region 205, the first sidewall and the second sidewall being located opposite. As illustrated in fig. 4, 5 and 6, the first sidewall of the gate structure 300 is a left sidewall, the second sidewall is a right sidewall, the first sidewall contacts the isolation structure 207 between the gate structure 300 and the first doped region 203 and contacts the isolation structure 207 between the gate structure 300 and the second doped region 204, and the second sidewall contacts the third doped region 205.
The electrostatic discharge protection device of the present embodiment includes a substrate 200 and a gate structure 300 on the substrate 200; a first well region 201 and a second well region 202 are formed in the substrate 200, the first well region 201 having a first conductivity type, and the second well region 202 having a second conductivity type opposite to the first conductivity type; the gate structure 300 spans from above a portion of the base of the first well region 201 to above a portion of the base of the second well region 202; a first doped region 203 and a second doped region 204 are formed on the top of the substrate of the first well region 201, the first doped region 203 and the second doped region 204 are located at one side of the gate structure 300, the first doped region 203 has a first conductivity type, and the second doped region 204 has a second conductivity type; a third doped region 205 and a fourth doped region 206 are formed on top of the substrate of the second well region 202, the third doped region 205 and the fourth doped region 206 are located on the other side of the gate structure 300, the third doped region 205 has the first conductivity type, and the fourth doped region 206 has the second conductivity type. In this way, the first well region 201, the second well region 202 and the third doped region 205 can form a first parasitic triode T1, the second doped region 204, the first well region 201 and the second well region 202 can form a second parasitic triode T2, the first parasitic triode T1 and the second parasitic triode T2 share the first well region 201 and the second well region 202 so as to be connected with each other, the first parasitic triode T1 can trigger the second parasitic triode T2 to be conducted, and further an SCR channel with stronger electrostatic discharge capability is formed, which is favorable for improving the electrostatic discharge capability of the circuit, and meets the electrostatic discharge protection requirement of the high-voltage device.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.
Claims (10)
1. An electrostatic discharge protection device, comprising a substrate and a gate structure on the substrate;
A first well region and a second well region which are connected are formed in the substrate, wherein the first well region has a first conductivity type, and the second well region has a second conductivity type opposite to the first conductivity type; the gate structure spans from above a portion of the base of the first well region to above a portion of the base of the second well region;
A first doped region and a second doped region are formed at the top of the substrate of the first well region, the first doped region and the second doped region are positioned at one side of the gate structure, the first doped region has a first conductivity type, and the second doped region has a second conductivity type; a third doped region and a fourth doped region are formed at the top of the substrate of the second well region, the third doped region and the fourth doped region are positioned at the other side of the gate structure, the third doped region has a first conductivity type, and the fourth doped region has a second conductivity type;
The first doped region and the second doped region are electrically connected to a first potential terminal, and the gate structure and the third doped region are electrically connected to a second potential terminal.
2. The esd protection device of claim 1 wherein the first well region, the second well region, and the third doped region comprise a first parasitic transistor; the second doped region, the first well region and the second well region form a second parasitic triode; the first parasitic transistor and the second parasitic transistor share the first well region and the second well region and are commonly used for electrostatic discharge.
3. The esd protection device of claim 2 wherein the first well region, the second well region, and the third doped region function as a collector, a base, and an emitter, respectively, of the first parasitic transistor; the second well region, the first well region and the second doped region are respectively used as a collector, a base and an emitter of the second parasitic triode.
4. The esd protection device of claim 1, wherein the first doped region and the second doped region are arranged along a width of a conductive channel under the gate structure.
5. The esd protection device of claim 4 wherein the second doped region is formed at both ends of the first doped region.
6. The esd protection device of claim 1, wherein the third doped region is located between the gate structure and the fourth doped region, the third doped region and the fourth doped region being elongated along a width of the conductive trench under the gate structure.
7. The esd protection device of claim 1, wherein an isolation structure is formed on top of the substrate between the gate structure and the first doped region, on top of the substrate between the gate structure and the second doped region, and on top of the substrate between the first doped region and the second doped region; and/or an isolation structure is formed on the top of the substrate between the third doped region and the fourth doped region.
8. The esd protection device of claim 1, wherein a first sidewall of the gate structure is in contact with an isolation structure and a second sidewall of the gate structure is in contact with the third doped region.
9. The esd protection device of any one of claims 1 to 8, wherein the first conductivity type is N-type and the second conductivity type is P-type.
10. The esd protection device of any one of claims 1 to 8 wherein the first potential terminal is an anode terminal and the second potential terminal is a cathode terminal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211348176.7A CN117954441A (en) | 2022-10-31 | 2022-10-31 | Electrostatic discharge protection device |
| PCT/CN2023/125966 WO2024093701A1 (en) | 2022-10-31 | 2023-10-23 | Electrostatic discharge protection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211348176.7A CN117954441A (en) | 2022-10-31 | 2022-10-31 | Electrostatic discharge protection device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117954441A true CN117954441A (en) | 2024-04-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211348176.7A Pending CN117954441A (en) | 2022-10-31 | 2022-10-31 | Electrostatic discharge protection device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN117954441A (en) |
| WO (1) | WO2024093701A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832233B (en) * | 2012-08-30 | 2015-05-20 | 北京大学 | SCR (silicon controlled rectifier) type LDMOS ESD (lateral double diffusion metal-oxide-semiconductor device electrostatic discharge) device |
| CN205319155U (en) * | 2015-12-08 | 2016-06-15 | 无锡中感微电子股份有限公司 | Static protective circuit and integrative circuit |
| CN207938608U (en) * | 2018-03-21 | 2018-10-02 | 湖南静芯微电子技术有限公司 | A kind of small island thyristor electrostatic protection device of grid insertion |
| CN108538830A (en) * | 2018-03-30 | 2018-09-14 | 电子科技大学 | High pressure ESD protection device |
-
2022
- 2022-10-31 CN CN202211348176.7A patent/CN117954441A/en active Pending
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2023
- 2023-10-23 WO PCT/CN2023/125966 patent/WO2024093701A1/en unknown
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| Publication number | Publication date |
|---|---|
| WO2024093701A1 (en) | 2024-05-10 |
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