CN117950836A - RISC-V architecture-based interrupt control system and method - Google Patents

Abstract

The invention provides an interrupt control system and method based on a RISC-V architecture, belonging to the technical field of RISC architecture chip design. The value taking module is an instruction pointer register and generates a PC register value serving as an instruction memory address signal; the decoding module interprets the read-write instruction sent by the instruction delay register, generates whether to read and write the register signal, reads and writes the general register according to the signal, and sends the read general register data and the write register signal to the execution delay register; the interrupt management module receives the interrupt request signal, arbitrates the interrupt request and generates an interrupt signal; the execution module receives and executes the instruction of the execution delay register and the interrupt signal of the interrupt management module. The invention generates the final interrupt signal through the interrupt management module arbitrating the synchronous or asynchronous interrupt, the interrupt management module is reliable in design, the code quantity is less, the transplantation is convenient, and the interrupt management requirement can be met.

Description

RISC-V architecture-based interrupt control system and method

Technical Field

The invention relates to an interrupt control system and method based on a RISC-V architecture, belonging to the technical field of RISC architecture chip design.

Background

Interrupts are an important element in chip design, and common interrupt control and arbitration modules are included in processor core designs. Interrupts and exceptions are not themselves an instruction, but are a very important ring in the processor instruction set architecture. The interrupt mechanism, i.e. the processor core is suddenly interrupted by another request during the sequential execution of the program instruction stream to suspend the execution of the current program, and instead, to process another thing, to wait for it to process another thing, and then to revert back to the point of the previous program interrupt to continue executing the previous program instruction stream. The exception that a processor encounters is called a exception. Exceptions are most distinguished from interrupts in that interrupts are often an external cause, and exceptions are caused by events within the processor or in the execution of the program, such as hardware faults themselves, program faults, or execution of special system service instructions, and are simply an internal cause.

Currently, most existing interrupt design modules are complex, and the interrupt design modules are generally part of the processor core, without convenient and reliable interrupt modules

Disclosure of Invention

The invention aims to provide an interrupt control system and method based on RISC-V architecture, which are reliable in design, small in code quantity and convenient to transplant.

The invention aims to achieve the aim, and the aim is achieved by the following technical scheme:

Comprising the following steps: the system comprises a value taking module, a decoding module, an interrupt management module, an execution module, an instruction delay register, an execution delay register, a control module, a RISC-V bus, a general register, an interrupt register and a DIV module;

The output of the control module is connected to the inputs of the value taking module, the instruction delay register and the execution delay register; the output of the value taking module is connected to the input of the RISC-V bus and the input of the instruction delay register; the output of the instruction delay register is connected to the input of the decoding module; the RISC-V bus output is connected to the input of the instruction delay register and is in bidirectional connection with the execution module; the decoding module is connected with the general register in a bidirectional way, and the output of the decoding module is connected with the execution delay register and the interrupt management module; the output of the execution delay register is connected to the execution module; the interrupt management module is in bidirectional connection with the interrupt register and the execution module; the interrupt register is connected with the execution module in a bidirectional way; the output of the execution module is connected to the control module and the general register and is in bidirectional connection with the DIV.

Preferably, the value module is an instruction pointer register, and generates a PC register value as an address signal of the instruction memory;

The decoding module interprets the read-write instruction sent by the instruction delay register, generates whether to read and write register signals, reads and writes the general register according to the signals, and sends the read general register data and the write register signals to the execution delay register;

the interrupt management module receives the interrupt request signal and arbitrates the interrupt request to generate an interrupt signal;

the execution module receives and executes the instruction of the execution delay register and the interrupt signal of the interrupt management module.

Preferably, the value taking module receives a reset signal, instructs the original value of the pointer register, judges whether the jump flag is valid, if so, sets the value of the pointer register to the value of the address to be jumped, and if not, adds 4.

Preferably, the interrupt source signal output by the RISC-V bus is divided into synchronous interrupt and asynchronous interrupt, the synchronous interrupt is an interrupt generated by ECALL instruction and EBREAK instruction of the RISC-V bus, and the asynchronous interrupt is an interrupt generated by an external interrupt source connected with the RISC-V bus.

Preferably, the interface of the external interrupt source of the RISC-V bus connection includes Flash, ROM, USI, PWM and GPIO.

Preferably, the executing module receives the memory access instruction, performs memory reading operation by adopting an asynchronous reading mode, sends a register writing data signal to the REHS module, sends a memory writing data signal to the AHB bus, and distributes the accessed module by the bus.

Preferably, the interrupt management module includes: an IDLE state machine, a MEPC state machine, MSTATUS state machine, MCAUSE state machine, and MSTATUS _ MRET state machine; the IDLE state machine is IDLE, the MEPC state machine is the state of the machine exception PC, the MSTATUS state machine is global interrupt and other state information, the MCAUSE state machine is the type of record current exception generation, and the MSTATUS _ MRET state machine is interrupt return state.

An interrupt control method based on RISC-V architecture, comprising:

The interrupt management module receives instruction content inst_i output by the decoding module, and judges whether synchronous interrupt or asynchronous interrupt is carried out according to the value of inst_i;

the execution module assigns the feedback jump address to the inst_addr, and after the synchronous interrupt or asynchronous interrupt processing is completed, the state machine enters the MEPC state machine;

Setting the value of a MEPC register as a current instruction address when the MEPC state machine is executed, and storing the PC value of an instruction before entering an exception by a MEPC register as a return address of the exception; the CSR_REG module completes the read-write operation of a CSR register;

the MEPC state machine writes the MEPC register of the CSR, jumps to the MSTATUS state machine, writes the matatus register, closes the global interrupt, and jumps to the MCAUSE state machine from the MSTATUS state machine;

The MCAUSE state machine records the type value of synchronous interrupt or asynchronous interrupt and writes the type value into a mcause register;

Assigning the machine mode exception entry base address register mtvec to an interrupt entry address of an execution module, and executing corresponding interrupt processing by the execution module;

After the interrupt processing is completed, the value of the return address mepc register serving as an exception is assigned to an interrupt entry address in the execution module, and the execution module continues to execute the operation interrupted by the interrupt.

The invention has the advantages that: the invention generates the final interrupt signal through the interrupt management module arbitrating the synchronous or asynchronous interrupt, the interrupt management module is reliable in design, the code quantity is less, the transplantation is convenient, and the interrupt management requirement can be met.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention.

FIG. 1 is a schematic diagram of the overall architecture of an interrupt module of the RISC-V architecture of the present invention.

FIG. 2 is a block diagram of a core interrupt management module according to the present invention.

In the figure: pc_reg: instruction pointer register, IF_ID: instruction delay register, ID: decoding module, ID_EX, execution delay register, EX: execution module, DIV: division module, CLINT: interrupt management module, CSR_REG: interrupt register, REGS: general purpose registers.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Example 1

As shown in fig. 1, an interrupt control system based on RISC-V architecture, comprising: the system comprises a value taking module, a decoding module, an interrupt management module, an execution module, an instruction delay register, an execution delay register, a control module, a RISC-V bus, a general register, an interrupt register and a DIV module.

The output of the control module is connected to the inputs of the value taking module, the instruction delay register and the execution delay register. The output of the value taking module is connected to the RISC-V bus input and the instruction delay register input. The instruction delay register output is connected to the decode module input. The RISC-V bus output is connected to the instruction delay register input and is connected in both directions with the execution module. The decoding module is connected with the general register in a bidirectional way, and the output of the decoding module is connected with the execution delay register and the interrupt management module. The execution delay register output is connected to an execution module. The interrupt management module is connected with the interrupt register and the execution module in a bidirectional way. The interrupt register is connected with the execution module in a bidirectional way. The output of the execution module is connected to the control module and the general register and is in bidirectional connection with the DIV.

In this embodiment, the value module is an instruction pointer register, and generates a PC register value as an address signal of the instruction memory.

The decoding module interprets the read-write instruction sent by the instruction delay register, generates whether to read and write register signals, reads and writes the general register according to the signals, and sends the read general register data and the write register signals to the execution delay register.

The interrupt management module receives the interrupt request signal and arbitrates the interrupt request to generate an interrupt signal.

The execution module receives and executes the instruction of the execution delay register and the interrupt signal of the interrupt management module.

In this embodiment, the value taking module receives the reset signal, the original value of the instruction pointer register, determines whether the jump flag is valid, if so, sets the value of the instruction pointer register to the value of the address to be jumped, and if not, adds 4 to the value of the instruction pointer register, each instruction is 32 bits.

In this embodiment, the interrupt source signals output by the RISC-V bus are divided into synchronous interrupts and asynchronous interrupts, where the synchronous interrupts are interrupts generated by ECALL instructions and EBREAK instructions of the RISC-V bus, and the asynchronous interrupts are interrupts generated by an external interrupt source connected to the RISC-V bus.

In this embodiment, the interface of the external interrupt source of the RISC-V bus connection includes Flash, ROM, USI, PWM and GPIO.

In this embodiment, the executing module receives the memory access instruction, performs the memory reading operation in an asynchronous reading mode, sends a register write data signal to the REHS module, sends a memory write data signal to the AHB bus, and distributes the accessed module by the bus.

In this embodiment, the interrupt management module includes: IDLE state machine, MEPC state machine, MSTATUS state machine, MCAUSE state machine, and MSTATUS _ MRET state machine. The IDLE state machine is IDLE, the MEPC state machine is the state of the machine exception PC, the MSTATUS state machine is global interrupt and other state information, the MCAUSE state machine is the type of record current exception generation, and the MSTATUS _ MRET state machine is interrupt return state.

For the interrupt management module, the interrupt management can adopt the following method: when an interrupt signal is detected, the whole pipeline is paused, a jump address is set as an interrupt entry address, then necessary CSR registers (mstatus, mepc, mcause and the like) are read and written, the pipeline pause is canceled after the CSR registers are read and written, and a processor can start to fetch a finger from the interrupt entry address and enter an interrupt service routine.

In addition, it should be noted that, the DIV module in fig. 1 is a division module, and is implemented by adopting a trial-and-quotient method, so that at least 32 clocks are required to complete a division operation.

Example 2

As shown in fig. 2, a RISC-V architecture-based interrupt control method includes:

The interrupt management module receives the instruction content inst_i output by the decoding module, and judges whether synchronous interrupt or asynchronous interrupt is carried out according to the value of inst_i.

The execution module assigns the feedback jump address to the inst_addr, and after the synchronous interrupt or the asynchronous interrupt is processed, the state machine enters the MEPC state machine.

When the MEPC state machine is used, the value of the MEPC register is set as the current instruction address, and the MEPC register stores the PC value of the instruction before entering the exception as the return address of the exception. The CSR_REG module completes the read-write operation of the CSR register.

The MEPC state machine writes the MEPC registers of the CSR, jumps to the MSTATUS state machine, writes the matatus registers, closes the global interrupt, and the MSTATUS state machine jumps to the MCAUSE state machine.

The MCAUSE state machine records the type value of the synchronous interrupt or the asynchronous interrupt and writes the type value into a mcause register.

The machine mode exception entry base address register mtvec is assigned to the interrupt entry address of the execution module, which executes the corresponding interrupt processing.

After the interrupt processing is completed, the value of the return address mepc register serving as an exception is assigned to an interrupt entry address in the execution module, and the execution module continues to execute the operation interrupted by the interrupt.

The disclosed embodiments also provide an interrupt control apparatus based on RISC-V architecture, including a processor (processor) and a memory (memory). Optionally, the apparatus may further comprise a communication interface (Communication Interface) and a bus. The processor, the communication interface and the memory can complete communication with each other through the bus. The communication interface may be used for information transfer. The processor may invoke logic instructions in memory to perform the RISC-V architecture based interrupt control method of the above embodiments.

Further, the logic instructions in the memory described above may be implemented in the form of software functional units and stored in a computer-readable storage medium when sold or used as a stand-alone product.

The memory is used as a computer readable storage medium for storing a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor executes the functional application and the data processing by running the program instructions/modules stored in the memory, i.e. implements the RISC-V architecture based interrupt control method in the above embodiments.

The memory may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function. The storage data area may store data created according to the use of the terminal device, etc. Further, the memory may include a high-speed random access memory, and may also include a nonvolatile memory.

Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. An interrupt control system based on RISC-V architecture, comprising: the system comprises a value taking module, a decoding module, an interrupt management module, an execution module, an instruction delay register, an execution delay register, a control module, a RISC-V bus, a general register, an interrupt register and a DIV module;

The output of the control module is connected to the inputs of the value taking module, the instruction delay register and the execution delay register; the output of the value taking module is connected to the input of the RISC-V bus and the input of the instruction delay register; the output of the instruction delay register is connected to the input of the decoding module; the RISC-V bus output is connected to the input of the instruction delay register and is in bidirectional connection with the execution module; the decoding module is connected with the general register in a bidirectional way, and the output of the decoding module is connected with the execution delay register and the interrupt management module; the output of the execution delay register is connected to the execution module; the interrupt management module is in bidirectional connection with the interrupt register and the execution module; the interrupt register is connected with the execution module in a bidirectional way; the output of the execution module is connected to the control module and the general register and is in bidirectional connection with the DIV.

2. The RISC-V architecture based interrupt control system of claim 1, wherein the value module is an instruction pointer register that generates a PC register value as an instruction memory address signal;

The decoding module interprets the read-write instruction sent by the instruction delay register, generates whether to read and write register signals, reads and writes the general register according to the signals, and sends the read general register data and the write register signals to the execution delay register;

the interrupt management module receives the interrupt request signal and arbitrates the interrupt request to generate an interrupt signal;

the execution module receives and executes the instruction of the execution delay register and the interrupt signal of the interrupt management module.

3. The RISC-V architecture based interrupt control system of claim 2, wherein the value module receives a reset signal, the original value of the instruction pointer register, determines whether the jump flag is valid, sets the instruction pointer register value to the value of the address to be jumped if it is valid, and adds 4 if it is invalid.

4. The RISC-V architecture based interrupt control system of claim 2, wherein the output interrupt source signal of the RISC-V bus is divided into synchronous interrupt and asynchronous interrupt, the synchronous interrupt being an interrupt generated by ECALL instruction and EBREAK instruction of the RISC-V bus, and the asynchronous interrupt being an interrupt generated by an external interrupt source connected to the RISC-V bus.

5. The RISC-V architecture based interrupt control system of claim 4, wherein the interface of the external interrupt source to which the RISC-V bus is connected comprises Flash, ROM, USI, PWM and GPIO.

6. The interrupt control system based on RISC-V architecture according to claim 2, wherein said execution module receives the memory access command, and performs the read memory operation by using an asynchronous read mode, and sends whether the register needs to be written and the register address needs to be written, the register data signal needs to be written to the REHS module, and the memory data signal needs to be written and the memory address needs to be written to the AHB bus, and the bus allocates the accessed module.

7. The RISC-V architecture based interrupt control system of claim 2, wherein the interrupt management module comprises: an IDLE state machine, a MEPC state machine, MSTATUS state machine, MCAUSE state machine, and MSTATUS _ MRET state machine; the IDLE state machine is IDLE, the MEPC state machine is the state of the machine exception PC, the MSTATUS state machine is global interrupt and other state information, the MCAUSE state machine is the type of record current exception generation, and the MSTATUS _ MRET state machine is interrupt return state.

8. A RISC-V architecture based interrupt control method using the system of any one of claims 1-7, comprising:

The interrupt management module receives instruction content inst_i output by the decoding module, and judges whether synchronous interrupt or asynchronous interrupt is carried out according to the value of inst_i;

the execution module assigns the feedback jump address to the inst_addr, and after the synchronous interrupt or asynchronous interrupt processing is completed, the state machine enters the MEPC state machine;

Setting the value of a MEPC register as a current instruction address when the MEPC state machine is executed, and storing the PC value of an instruction before entering an exception by a MEPC register as a return address of the exception; the CSR_REG module completes the read-write operation of a CSR register;

the MEPC state machine writes the MEPC register of the CSR, jumps to the MSTATUS state machine, writes the matatus register, closes the global interrupt, and jumps to the MCAUSE state machine from the MSTATUS state machine;

The MCAUSE state machine records the type value of synchronous interrupt or asynchronous interrupt and writes the type value into a mcause register;

Assigning the machine mode exception entry base address register mtvec to an interrupt entry address of an execution module, and executing corresponding interrupt processing by the execution module;

After the interrupt processing is completed, the value of the return address mepc register serving as an exception is assigned to an interrupt entry address in the execution module, and the execution module continues to execute the operation interrupted by the interrupt.

9. A computer readable storage medium, characterized in that a computer program is stored thereon, which program, when being executed by a processor, implements the method of claim 8.