CN117947506A - Selective epitaxy preparation method of semiconductor/superconductor heterojunction nanowire network - Google Patents
Selective epitaxy preparation method of semiconductor/superconductor heterojunction nanowire network Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 239000002070 nanowire Substances 0.000 title claims abstract description 54
- 239000002887 superconductor Substances 0.000 title claims abstract description 44
- 238000000407 epitaxy Methods 0.000 title claims abstract description 40
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 239000000463 material Substances 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 32
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- H—ELECTRICITY
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- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
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- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/04—Pattern deposit, e.g. by using masks
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
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Abstract
The present disclosure provides a selective epitaxy preparation method of a semiconductor/superconductor heterojunction nanowire network, comprising: preparing a patterned step structure on the surface of the substrate; carrying out selective epitaxial growth on the material based on the patterned step structure, and extending a semiconductor nanowire network at the patterned step structure; and (3) extending the superconductor on the semiconductor nanowire network to obtain a semiconductor/superconductor heterojunction nanowire network. The method utilizes low adsorption energy and low nucleation energy at the step to realize selective epitaxial growth of the material, the selectivity of the material does not depend on the quality and the type of mask materials, selective epitaxial growth can be realized at a lower temperature, a new method is provided for low-temperature epitaxial patterning materials, the range of selective epitaxial materials is expanded, and the problems that the traditional selective epitaxial method is complex in process, depends strongly on the quality and the type of mask materials and has a narrow epitaxial temperature window are solved.
Description
Technical Field
The disclosure relates to the technical field of material preparation, in particular to a selective epitaxy preparation method of a semiconductor/superconductor heterojunction nanowire network.
Background
Topology quantum calculation based on Maastricht Treaty and the Na zero energy mode is an important scheme for developing a quantum computer, and finding Maastricht Treaty and the Na zero energy mode are the preconditions for realizing the scheme. In theory, in a strong spin orbit coupled semiconductor/superconductor heterojunction nanowire system, by applying a magnetic field, using the neighbor effect of the superconductor, a Maastricht Treaty rena zero energy mode can occur at both ends of the heterojunction nanowire. Aiming at the theory, a semiconductor/superconductor heterojunction nanowire network needs to be prepared experimentally, and the network is used for verifying whether Maastricht Treaty Rana zero energy modes exist or not on one hand; on the other hand, the method is used for carrying out the braiding operation of Maastricht Treaty Rana zero energy modes so as to construct topological quantum bits.
At present, a traditional plane selective epitaxy method is mainly adopted to prepare a semiconductor/superconductor heterojunction nanowire network, and the principle is that the patterned selective growth of materials is realized by utilizing the difference of desorption coefficients of the materials between a mask layer and a substrate. Therefore, this technique is strongly dependent on the kind of mask material in the implementation, and without a suitable mask material, it is difficult to achieve patterned selective growth of the material. On the other hand, conventional planar selective epitaxy techniques require higher growth temperatures for material growth. Excessive growth temperatures tend to cause the material to be grown to decompose or even be completely destroyed. In view of these problems, it is highly desirable to find a method for preparing a semiconductor/superconductor heterojunction nanowire network with a simple process, independent of the quality and type of mask materials, and a wide epitaxial temperature window.
Disclosure of Invention
In view of the above, the present disclosure provides a selective epitaxy preparation method of a semiconductor/superconductor heterojunction nanowire network, which is used for solving the above technical problems.
The present disclosure provides a selective epitaxy preparation method of a semiconductor/superconductor heterojunction nanowire network, comprising: preparing a patterned step structure on the surface of the substrate; the selective epitaxial growth of the material is carried out based on the patterned step structure, and a semiconductor nanowire network is epitaxially grown at the patterned step structure; and (3) extending the superconductor on the semiconductor nanowire network to obtain a semiconductor/superconductor heterojunction nanowire network.
According to an embodiment of the present disclosure, preparing a patterned step structure on a substrate surface includes: depositing a protective layer on the substrate; patterning and etching the protective layer and the substrate to obtain a patterned step structure; and removing the remaining protective layer.
According to an embodiment of the present disclosure, depositing a protective layer on a substrate includes: depositing a protective layer on a substrate by chemical vapor deposition, physical vapor deposition or atomic layer deposition; removing the remaining protective layer, including; and removing the residual protective layer by adopting dry etching or wet etching.
According to an embodiment of the present disclosure, patterning and etching the protective layer and the substrate includes: patterning the protective layer and the substrate by electron beam exposure or lithography; and etching the protective layer and the substrate by adopting dry etching or wet etching.
According to an embodiment of the present disclosure, an epitaxial semiconductor nanowire network at a patterned step structure, comprising: the semiconductor nanowire network is epitaxially grown by molecular beam epitaxy, chemical beam epitaxy or metal organic vapor phase epitaxy.
According to embodiments of the present disclosure, the temperature of the epitaxial semiconductor nanowire network is 200 ℃ to 700 ℃.
According to an embodiment of the present disclosure, the substrate includes a semiconductor substrate, a metal substrate, or an oxide substrate; the protective layer comprises a metal simple substance, an oxide or a nitride.
According to an embodiment of the present disclosure, a material of a semiconductor nanowire network includes a compound semiconductor or an elemental semiconductor; the material of the superconductor includes a compound superconductor or an elemental superconductor.
According to embodiments of the present disclosure, the patterned step structure has a length of nanometer magnitude to centimeter magnitude, a width of nanometer magnitude to micrometer magnitude, and a height of nanometer magnitude; the semiconductor/superconductor heterojunction nanowire network has a length of nanometer magnitude to centimeter magnitude, a width of nanometer magnitude to micrometer magnitude, and a height of nanometer magnitude to micrometer magnitude.
According to embodiments of the present disclosure, the area of the semiconductor/superconductor heterojunction nanowire network is nanoscale to wafer scale.
The selective epitaxy preparation method of the semiconductor/superconductor heterojunction nanowire network provided by the embodiment of the disclosure at least comprises the following beneficial effects:
the patterning step structure is prepared on the substrate, and the selective epitaxial growth of the material is realized by utilizing low adsorption energy and low nucleation energy at the step of the patterning step structure. Compared with the traditional selective epitaxy, the method utilizes atomic diffusion to realize selective epitaxy growth, the selectivity of the material does not depend on the quality and the type of the material, selective epitaxy growth can be realized at a lower temperature, a new method is provided for low-temperature epitaxy patterning materials, the range of the selective epitaxy materials is expanded, and the problems that the traditional selective epitaxy method is complex in process, depends strongly on the quality and the type of mask materials and has a narrow epitaxy temperature window are solved. And the method has simple process.
Drawings
The connections between the various features of the present disclosure are further described below with reference to the accompanying drawings. The figures are exemplary, some features are not shown in actual scale, and some features that are conventional in the art to which this disclosure pertains and are not essential to the present disclosure may be omitted from some figures, or additional features that are not essential to the present disclosure are shown, and combinations of the various features shown in the figures are not intended to limit the present disclosure. In addition, throughout the specification, the same reference numerals refer to the same. The specific drawings are as follows:
Fig. 1 schematically illustrates a flow chart of a selected-area epitaxial fabrication method of a surface semiconductor/superconductor heterojunction nanowire network, in accordance with an embodiment of the disclosure.
Fig. 2 schematically illustrates a block diagram corresponding to each operation in the preparation method according to the embodiment of the present disclosure.
Detailed Description
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; may be mechanically connected, may be electrically connected or may communicate with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.
In the description of the present disclosure, it should be understood that the terms "longitudinal," "length," "circumferential," "front," "rear," "left," "right," "top," "bottom," "inner," "outer," and the like indicate an orientation or a positional relationship based on that shown in the drawings, merely to facilitate description of the present disclosure and to simplify the description, and do not indicate or imply that the subsystem or element being referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present disclosure.
Like elements are denoted by like or similar reference numerals throughout the drawings. Conventional structures or constructions will be omitted when they may obscure the understanding of this disclosure. And the shape, size and position relation of each component in the figure do not reflect the actual size, proportion and actual position relation. In addition, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Similarly, in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. The description of the reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise.
The selective epitaxial preparation method of the semiconductor/superconductor heterojunction nanowire network provided by the embodiment of the present disclosure will be explained in detail with reference to the specific drawings.
Fig. 1 schematically illustrates a flow chart of a selected-area epitaxial fabrication method of a surface semiconductor/superconductor heterojunction nanowire network, in accordance with an embodiment of the disclosure. Fig. 2 schematically illustrates a block diagram corresponding to each operation in the preparation method according to the embodiment of the present disclosure.
As shown in fig. 1 and 2, the preparation method may include, for example, operations S110 to S130.
In operation S110, a patterned step structure is prepared on a surface of a substrate.
First, a substrate 10 is prepared as shown in fig. 2 (a). The substrate 10 may be a semiconductor substrate (e.g., si, ge, siC, gaAs, gaSb, gaP, inAs, inSb and InP, etc.), a metal substrate (e.g., mo, etc.), or an oxide substrate (e.g., sapphire, mgO, glass, etc.). The substrates are selected to provide the functions of a gate and the like for the subsequent preparation of electronic devices and quantum devices.
Then, a protective layer 11 is prepared on the substrate 10, as shown in fig. 2 (b). The protective layer 11 may be deposited on the substrate 10 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The deposition methods are adopted to ensure that the protection layer 11 with uniform and compact appearance can be obtained, so that the non-pattern position on the substrate 10 can be fully protected. The protection layer 11 is used to protect the surface of the substrate 10 at the non-pattern position from damage during pattern etching and surface treatment, thereby avoiding influence on migration of adsorbed atoms or molecules. The material of the protective layer 11 is a metal simple substance (e.g., metal A1, etc.), an oxide, or a nitride (e.g., silicon oxide, silicon nitride, aluminum oxide, etc.), which is selected to ensure that the protective layer 11 is easily removed in a subsequent process.
Finally, patterning and etching are performed on the protective layer 11 and the substrate 10 by using the micro-nano processing technology, so as to obtain a patterned step structure, as shown in fig. 2 (c). The remaining protective layer 11 is removed to form a patterned substrate 12, the cross-sectional structure of which is shown in fig. 2 (d), and the perspective structure of which is shown in fig. 2 (g). The patterning substrate 12 is realized through photoetching and electron beam exposure processes, and the photoetching and electron beam exposure processes are selected to ensure that the pattern morphology on the patterning substrate 12 is continuous and have good controllability. The steps are realized by dry etching and wet etching, and the two etching methods are selected to ensure that the steps obtained by etching are uniform in size, so that the epitaxial semiconductor nanowire network morphology is ensured to be uniform. The remaining protective layer 11 can be removed by dry etching or wet etching, and the two etching methods are selected to ensure that the protective layer 11 is completely removed and avoid damage to the surface of the substrate. The length of the patterned step structure is in the order of nanometers to centimeters, the width is in the order of nanometers to micrometers, and the height is in the order of nanometers, and the dimensions are used for regulating and controlling the dimensions of the semiconductor nanowire network.
In operation S120, a selective epitaxial growth of a material is performed based on the patterned step structure, and a semiconductor nanowire network is epitaxially grown at the step structure.
The patterned substrate 12 with the patterned step structure is placed into a device for epitaxy of the semiconductor material 13, and a semiconductor nanowire network is obtained, wherein the cross-sectional structure diagram is shown in fig. 2 (e), and the three-dimensional structure diagram is shown in fig. 2 (h). Unlike conventional planar selective epitaxy, which utilizes the difference in desorption coefficient of material between the mask layer and the substrate to realize patterned selective growth of material, the epitaxy mechanism of the semiconductor material 13 is to utilize low adsorption energy and low nucleation energy at the step to realize selective epitaxial growth of material. The semiconductor material 13 is epitaxially grown, including molecular beam epitaxy, chemical beam epitaxy, or metal organic vapor phase epitaxy. These epitaxial modes are chosen to ensure that atoms or molecules undergo adequate diffusion migration at the substrate surface until diffusion to the step locations stops and nucleates. The epitaxial semiconductor material 13 is an elemental semiconductor (e.g., si, ge, etc.) or a compound semiconductor (e.g., gaAs xSb1-x, inAs, inSb, pbTe, znTe, alAs, alSb, etc.). These semiconductor materials are the requisite materials for developing semiconductor electronic devices and quantum devices. The temperature of the epitaxial semiconductor material 13 on the patterned substrate 12 is 200 c to 700 c, which temperature interval is chosen to ensure that precise epitaxy of the semiconductor material 13 is achieved at the pattern location. The lower epitaxy temperature and the epitaxy temperature are adjustable in a large range, so that the problem of narrow epitaxy temperature window in the traditional selective epitaxy method is solved.
In operation S130, a superconductor is grown on the semiconductor nanowire network, resulting in a semiconductor/superconductor heterojunction nanowire network.
The superconducting material 14 is epitaxially grown on the semiconductor material 13 to obtain a large-area semiconductor/superconductor heterojunction nanowire network, the cross-sectional structure is shown in fig. 2 (f), and the perspective structure is shown in fig. 2 (i). The superconducting material 14 is a simple substance superconductor (e.g., al, in, pb, etc.) or a compound superconductor. The choice of these superconductors ensures the production of high quality semiconductor/superconductor electronic devices and quantum devices. The semiconductor/superconductor heterojunction nanowire network has a length of nanometer magnitude to centimeter magnitude, a width of nanometer magnitude to micrometer magnitude, and a height of nanometer magnitude to micrometer magnitude. The area of the semiconductor/superconductor heterojunction nanowire network is nanoscale to wafer scale.
In order to more clearly illustrate the selective epitaxial preparation method of the semiconductor/superconductor heterojunction nanowire network provided by the embodiments of the present disclosure, a specific example is listed below.
In this example, the substrate material selected is a Ge substrate, the protective layer selected is amorphous silicon oxide, and the protective layer is deposited by plasma enhanced chemical vapor deposition. The selected exposure mode is electron beam exposure, and the electron beam glue is PMMA. The pattern etching mode adopts reactive ion beam etching, photoresist removing adopts an oxygen plasma photoresist remover, and the protective layer removing adopts wet etching (hydrofluoric acid slow-release liquid). The epitaxy material is InSb material with larger lattice mismatch with Ge, and the epitaxy mode is molecular beam epitaxy.
The specific process is as follows:
step (1): and depositing a 20 nm-thick silicon oxide amorphous layer on the Ge substrate by utilizing a plasma enhanced chemical vapor deposition technology, and protecting the surface of the Ge substrate from being damaged in the subsequent process so as to ensure that atoms or molecules have a sufficiently long diffusion length on the Ge substrate and can be diffused to a pattern step.
Step (2): a patterned Ge substrate was prepared, with steps at the pattern locations. The Ge substrate was decomposed into a desired size and PMMA electron beam paste was spin coated thereon, followed by baking at 150 ℃ for 10 minutes. The substrate was exposed by an electron beam exposure apparatus, developed with MIBK: ipa=1:3 solution for 40s, and fixed with IPA solution for 40s, to obtain a 100nm wide nanowire network pattern. And then post-baking and removing the bottom film. The silicon oxide at the position of the substrate pattern is etched by using a reactive ion beam etching device and etched for 10nm to realize the step effect. The etching parameters are set to etch 30nm silicon oxide, so as to achieve the effect of over etching and obtain the Ge step with the height of 7 nm. And then removing PMMA electron beam glue on the surface of the substrate by using an oxygen plasma glue machine.
Step (3): and etching the substrate for 30 seconds by using hydrofluoric acid slow release liquid (HF: NH 4 F=1:7) to remove the amorphous silicon oxide protective layer at the position without steps. The Ge substrate with the patterned steps is used for epitaxy, so that the influence of electron beam glue on the subsequent epitaxy process can be eliminated, and the influence of mask layer quality and type on material selective epitaxy can be avoided.
Step (4): and placing the processed substrate into a molecular beam epitaxy device to carry out epitaxy of the InSb material. And a large area of InSb nanowire network with excellent selectivity, uniformity and high crystal quality is extended on the Ge substrate.
Step (5): based on the InSb nanowire network, further in-situ epitaxy of superconducting Al is performed, and a large-area patterned InSb/Al heterojunction nanowire network is obtained.
In summary, according to the preparation method provided by the embodiment of the disclosure, a protective layer is deposited on a substrate, a patterned step is processed on the surface of the substrate by using a micro-nano processing technology, then the protective layer is removed, the epitaxial selective growth of a semiconductor nanowire network is performed at the patterned step, and finally a superconductor is epitaxially grown on the semiconductor nanowire network, so that a large-area patterned semiconductor/superconductor heterojunction nanowire network is obtained. Compared with the traditional selective epitaxy method, the selective epitaxy growth of the material is realized by utilizing low adsorption energy and low nucleation energy at the patterning step, the selective epitaxy growth of the material is realized at a lower temperature without depending on the quality and the type of the mask material, a new method is provided for low-temperature epitaxy patterning materials, the range of the selective epitaxy material is expanded, and the problems that the traditional selective epitaxy method is complex in process, depends strongly on the quality and the type of the mask material and has a narrow epitaxy temperature window are solved.
The foregoing description of the specific embodiments has been provided for the purpose of illustrating the general principles of the present disclosure, including embodiments and concepts thereof, and is recognized as being merely exemplary of the presently preferred embodiments and concepts thereof. Those skilled in the art will appreciate that the present disclosure is not limited to the specific embodiments described herein, and that various obvious changes, rearrangements and substitutions can be made by those skilled in the art without departing from the scope of the disclosure. Thus, while the present disclosure has been described in terms of the above embodiments, the present disclosure is not limited to the above embodiments, but may include many other equivalent embodiments without departing from the spirit of the present disclosure, all falling within the scope of the present disclosure.
Claims (10)
1. A selective epitaxy preparation method of a semiconductor/superconductor heterojunction nanowire network comprises the following steps:
Preparing a patterned step structure on the surface of the substrate;
Epitaxial growth of a selected region of a material based on the patterned step structure, and epitaxy of a semiconductor nanowire network at the patterned step structure;
and (3) extending a superconductor on the semiconductor nanowire network to obtain a semiconductor/superconductor heterojunction nanowire network.
2. The method of manufacturing of claim 1, wherein the manufacturing of the patterned step structure on the substrate surface comprises:
depositing a protective layer on the substrate;
patterning and etching the protective layer and the substrate to obtain the patterned step structure;
and removing the remaining protective layer.
3. The method of manufacturing of claim 2, wherein depositing a protective layer on the substrate comprises:
depositing a protective layer on the substrate by means of chemical vapor deposition, physical vapor deposition or atomic layer deposition;
The removing of the remaining protective layer comprises;
And removing the residual protective layer by adopting dry etching or wet etching.
4. The method of manufacturing of claim 2, wherein the patterning and etching the protective layer and the substrate comprises:
patterning the protective layer and the substrate using electron beam exposure or lithography; and etching the protective layer and the substrate by adopting dry etching or wet etching.
5. The method of manufacturing of claim 1, wherein the epitaxially growing a semiconductor nanowire network at the patterned step structure comprises:
The semiconductor nanowire network is epitaxially grown by molecular beam epitaxy, chemical beam epitaxy or metal organic vapor phase epitaxy.
6. The method of manufacturing according to claim 1 or 5, wherein the temperature of the epitaxial semiconductor nanowire network is 200 ℃ to 700 ℃.
7. The manufacturing method according to claim 2, wherein the substrate comprises a semiconductor substrate, a metal substrate, or an oxide substrate; the protective layer comprises a metal simple substance, an oxide or a nitride.
8. The method of manufacturing according to claim 1, wherein the material of the semiconductor nanowire network comprises a compound semiconductor or an elemental semiconductor; the material of the superconductor comprises a compound superconductor or an elemental superconductor.
9. The method of manufacturing of claim 1, wherein the patterned step structure has a length on the order of nanometers to centimeters, a width on the order of nanometers to micrometers, and a height on the order of nanometers;
The semiconductor/superconductor heterojunction nanowire network has a length of nanometer magnitude to centimeter magnitude, a width of nanometer magnitude to micrometer magnitude and a height of nanometer magnitude to micrometer magnitude.
10. The method of claim 1, wherein the semiconductor/superconductor heterojunction nanowire network has an area ranging from nanoscale to wafer scale.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410114963.8A CN117947506A (en) | 2024-01-26 | 2024-01-26 | Selective epitaxy preparation method of semiconductor/superconductor heterojunction nanowire network |
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