CN113838964B - Superconducting-semiconductor nanowire heterojunction, preparation method thereof and device comprising superconducting-semiconductor nanowire heterojunction - Google Patents

Superconducting-semiconductor nanowire heterojunction, preparation method thereof and device comprising superconducting-semiconductor nanowire heterojunction Download PDF

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CN113838964B
CN113838964B CN202111080289.9A CN202111080289A CN113838964B CN 113838964 B CN113838964 B CN 113838964B CN 202111080289 A CN202111080289 A CN 202111080289A CN 113838964 B CN113838964 B CN 113838964B
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semiconductor nanowire
superconducting
heterojunction
substrate
semiconductor
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CN113838964A (en
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何珂
张�浩
冯硝
姜钰莹
苗文韬
宋文玉
曹霑
杨帅
李琳
仝冰冰
臧运祎
耿祖汗
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Beijing Institute Of Quantum Information Science
Tsinghua University
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Beijing Institute Of Quantum Information Science
Tsinghua University
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    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H10N60/12—Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/85—Superconducting active materials

Abstract

The invention relates to the technical field of heterojunction, in particular to a superconducting-semiconductor nanowire heterojunction, which comprises a substrate, and a semiconductor nanowire and a superconductor layer which are grown on the substrate, wherein at least one part of the superconductor layer is in direct contact with the semiconductor nanowire; the semiconductor nanowire is made of a compound semiconductor PbTe, the superconductor layer is made of an element superconductor Pb, and the substrate is made of a compound semiconductor CdTe. The invention also relates to a preparation method of the superconducting-semiconductor nanowire heterojunction. The invention further relates to a device comprising said superconducting-semiconductor nanowire heterojunction.

Description

Superconducting-semiconductor nanowire heterojunction, preparation method thereof and device comprising superconducting-semiconductor nanowire heterojunction
Technical Field
The invention relates to the technical field of heterojunction, in particular to a superconducting-semiconductor nanowire heterojunction, a preparation method thereof and a device comprising the same.
Background
The topological quantum computing scheme utilizes a non-Abbe random son 'Mahalana zero mode' (MZM-Majorana zero mode) in a condensed state system to encode, can effectively resist local disturbance, thereby solving the problems of quantum decoherence and error correction and having inherent fault tolerance. The superconducting-semiconductor nanowire mixed system is an ideal material system capable of realizing topological quantum computation, and has the advantages of easy regulation and control by an electrical means, easy integration and the like. Researchers generally consider that the existence of a "maladies" that follow non-abbe statistics in a "superconducting-semiconductor nanowire" one-dimensional heterojunction is an ideal material system that can achieve topological quantum computation. The heterostructure of the superconducting-semiconductor nanowire needs to cover superconducting materials on a section of semiconductor nanowire, the area of the surface of the nanowire covered by the superconducting materials can become a topological superconducting area under extremely low temperature through strong magnetic field and electric field regulation, and the tail end of the area can detect a 'Malabar zero mode', so that the heterostructure quantum bit is a basic carrier of topological qubits. Ideal mahalanobis quantum devices require semiconductor nanowires with ultra-high crystal quality and quantum transport properties, while requiring very clean interfaces between the nanowires and the superconductor.
The material system widely used at present for topology quantum computing schemes based on one-dimensional heterojunction systems of "superconducting-semiconductor nanowires" is superconducting material Al (aluminum), combined with III-V semiconductor InAs (indium arsenide) or InSb (indium antimonide) nanowires, which have the characteristics required for achieving topology superconductivity, such as high mobility, strong spin-orbit coupling and sufficiently large g-factors, for example, the electron mobility of InAs nanowires can reach 3.3X10 4 cm 2 The spin orbit coupling strength is 10 mu eV, the g factor is 20-50, and the electron mobility of InSb can reach 7.7X10 4 cm 2 The spin orbit coupling strength is 230 mu eV, and the g factor is 58-64.
However, the growth method of the InAs or InSb nanowires is a VLS (vapor-liquid-solid mechanical) method, the nanowires are vertically grown on the substrate, the nanowires are not limited by the crystal lattice of the substrate, and higher electron mobility can be obtained. And then the nanowire grown by the VLS method needs to be transferred when the device is processed, so that the problems of low efficiency and low yield exist, and the large-scale integration of the device is not facilitated. If a molecular beam epitaxy selective growth method is selected to transversely grow the nanowire in the substrate surface, although the transfer of the nanowire can be avoided, the lattice of the InAs or InSb nanowire cannot be well matched with that of a common substrate (InP, gaAs or Si), and the mobility of the nanowire is greatly lower than that of the nanowire grown by a VLS method due to defects caused by lattice mismatch. InAs nanowires grown by molecular beam epitaxy selective area reported in the literature have mobility of only 700cm 2 The mobility of the InSb nanowire is only 950cm 2 /Vs。
Disclosure of Invention
Based on the above, the invention provides a novel superconducting-semiconductor nanowire heterojunction, a preparation method thereof and a device comprising the novel superconducting-semiconductor nanowire heterojunction, crystal lattices of a substrate and a semiconductor nanowire are more matched, the nanowire can be directly grown on the substrate through a molecular beam epitaxy selective region, and the superconducting-semiconductor nanowire is more matched and can be used as a heterostructure in topological quantum computation.
In one aspect of the present invention, there is provided a superconducting-semiconductor nanowire heterojunction comprising:
a substrate, and a semiconductor nanowire and a superconductor layer grown on the substrate, at least a portion of the superconductor layer being in direct contact with the semiconductor nanowire;
the semiconductor nanowire is made of a compound semiconductor PbTe, the superconductor layer is made of an element superconductor Pb, and the substrate is made of a compound semiconductor CdTe.
In one embodiment, the semiconductor nanowire is 3 μm to 5 μm long and 0.05 μm to 0.3 μm wide.
In one embodiment, the semiconductor nanowires are parallel to the substrate surface.
In one embodiment, the superconducting-semiconductor nanowire heterojunction interface is atomically flat.
In one embodiment, the semiconductor nanowire is partially covered by the superconductor layer.
In one embodiment, one end of the semiconductor nanowire has a length of 1/3 to 2/3 that of the superconductor layer.
In one embodiment, the two ends of the semiconductor nanowire are covered by the superconductor layer, and the area between 100nm and 300nm is left uncovered by the superconductor layer.
In still another aspect, the present invention provides a method for preparing the superconducting-semiconductor nanowire heterojunction, including the steps of:
plating a mask on the CdTe substrate;
throwing HSQ Fox-series electron beam photoresist with preset thickness on the mask, and forming a photoresist three-dimensional pattern on the mask after electron beam exposure development;
throwing positive electron beam photoresist on the mask and the photoresist three-dimensional graph, and forming a groove on the mask after electron beam exposure development;
etching to remove the mask in the groove and removing the positive electron beam photoresist;
and growing PbTe nanowires on the CdTe substrate in the groove by utilizing a molecular beam epitaxy technology, and inclining the photoresist three-dimensional pattern by a preset angle relative to the Pb beam direction, so that the projection part of the photoresist three-dimensional pattern shields part of the PbTe nanowires, and Pb is grown in situ on the non-shielded part to form a heterojunction.
In one embodiment, the preset thickness is 500 nm-1000 nm, the preset angle is 20-70 degrees, and the distance between the groove and the photoresist three-dimensional pattern is 120-300 nm.
In yet another aspect of the invention, a device is provided comprising the superconducting-semiconductor nanowire heterojunction.
In one embodiment, the device is a topological quantum device.
Compared with the prior art, the invention at least comprises the following beneficial effects:
the heterojunction of the superconducting-semiconductor nanowire provided by the invention is formed by selecting the compound semiconductor CdTe as a substrate material, the compound semiconductor PbTe as a semiconductor nanowire material epitaxially grown on the substrate and the element superconductor Pb as a superconductor layer material, so that the substrate and the semiconductor nanowire have high lattice matching degree on one hand, the semiconductor nanowire has high electron mobility, and on the other hand, the semiconductor nanowire and the superconducting material have larger induced superconducting energy gap. The superconducting-semiconductor nanowire heterojunction has great potential in topological quantum device application, and is expected to become a new generation of topological quantum computing system material. In addition, the heterojunction is directly and transversely grown on the substrate, so that the nanowire is not required to be transferred in the subsequent device processing, and the large-scale integration of the device is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a superconducting-semiconductor nanowire heterojunction structure in one embodiment of the invention;
FIG. 2 is a process flow diagram of fabricating nanowire heterojunction in one embodiment of the invention;
FIGS. 3-5 are TEM views of Pb-PbTe nanowires prepared in example 1 of the invention, wherein FIG. 4 is an enlarged view at the PbTe-CdTe interface, and FIG. 5 is an enlarged view at the Pb-PbTe interface;
FIG. 6 is a schematic diagram of a PbTe nanowire field effect transistor structure;
FIG. 7 is a graph of PbTe nanowire field effect transistor conductance-gate voltage fitting;
wherein: 1-a substrate; 2-a mask layer; 3-HSQ Fox-series electron beam photoresist layer; 31-photoresist three-dimensional pattern; 4-positive electron beam photoresist layer; 41-grooves; 5-a first phase material; 6-a second phase material.
Detailed Description
Reference now will be made in detail to embodiments of the invention, one or more examples of which are described below. Each example is provided by way of explanation, not limitation, of the invention. Indeed, it will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the scope or spirit of the invention. For example, features illustrated or described as part of one embodiment can be used on another embodiment to yield still a further embodiment.
Accordingly, it is intended that the present invention cover such modifications and variations as fall within the scope of the appended claims and their equivalents. Other objects, features and aspects of the present invention will be disclosed in or be apparent from the following detailed description. It is to be understood by one of ordinary skill in the art that the present discussion is a description of exemplary embodiments only, and is not intended as limiting the broader aspects of the present invention.
Except where shown or otherwise indicated in the operating examples, all numbers expressing quantities of ingredients, physical and chemical properties, and so forth, used in the specification and claims are to be understood as being modified in all instances by the term "about". For example, therefore, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that can be varied appropriately by those skilled in the art utilizing the teachings disclosed herein seeking to obtain the desired properties. The use of numerical ranges by endpoints includes all numbers subsumed within that range and any range within that range, e.g., 1 to 5 includes 1, 1.1, 1.3, 1.5, 2, 2.75, 3, 3.80, 4, 5, and the like.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The term "malassezian zero mode" is a quasi-particle excitation with zero energy, predicted to exist in a topological superconducting system. Since it follows non-Abbe statistics, it can be used for topological quantum computation.
The term "VLS (vapor-liquid-solid mechanism)" is a combined growth method. In the growth system, three states of gas, liquid and solid exist simultaneously, and the substance to be grown is firstly changed into liquid state (generally solution) from gas state, and then the crystal is grown on the crystal substrate by liquid deposition.
The term "epitaxial growth" refers to the growth of a single crystal layer on a single crystal substrate (substrate) that has the same crystal orientation as the substrate as if the original crystal had been extended outward by a certain length. Epitaxial growth requires a very good lattice match of the substrate and the species grown on the substrate.
The term "molecular beam epitaxy" refers to the process of epitaxially growing a thin film material on a substrate, in which the vapor produced by heating in an oven containing various desired components is collimated by small holes to form a molecular beam or atomic beam, which is then directly sprayed onto a monocrystalline substrate at a suitable temperature to cause the molecules or atoms to "grow" layer by layer in a crystalline arrangement to form a thin film on the substrate. The term "molecular beam epitaxy selective growth method" is to define a mask material with a specific pattern on a substrate through micro-nano processing, so that the substrate is partially exposed, and thin film materials are grown in the exposed substrate area, thereby realizing the selective epitaxy. The method is suitable for growing low-dimensional materials such as nanowires.
The term "spin coating" refers to uniformly spinning off the glue solution and tiling it on the surface of the material, for example "spin positive electron beam resist on a mask" refers to uniformly spinning off the glue solution of positive electron beam resist and tiling it on a mask.
The term "superconducting neighbor effect" refers to the fact that when a film of a normal conductor or semiconductor is coated on the surface of a superconductor, if the film thickness is less than the coherence length of the Cooper electron pair, the coated film will become a superconductor, and the superconducting material will induce a superconducting energy gap in the semiconductor material. This phenomenon is known as the proximity effect of superconductors. The superconducting neighbor effect can inhibit superconducting properties after the temperature is increased or a magnetic field is applied, and the observed superconducting energy gap can be gradually reduced until the superconducting energy gap disappears.
Referring to fig. 1, an embodiment of the present invention provides a superconducting-semiconductor nanowire heterojunction, including: a substrate 1, and a semiconductor nanowire 11 and a superconductor layer 12 grown on said substrate 1, at least a portion of said superconductor layer 12 being in direct contact with said semiconductor nanowire 11.
The material of the semiconductor nanowire 11 is a compound semiconductor PbTe, the material of the superconductor layer 12 is an element superconductor Pb, and the material of the substrate 1 is a compound semiconductor CdTe.
The growth is epitaxial growth, which is complete in-plane eutectic lattice growth.
In some embodiments, the semiconductor nanowires 11 are 3 μm to 5 μm long and 0.05 μm to 0.3 μm wide.
In some embodiments, the semiconductor nanowires 11 are parallel to the surface of the substrate 1. Because the lattice matching degree of PbTe and CdTe is high, the growth of the semiconductor nanowire 11 parallel to the surface of the substrate 1 is facilitated, so that the position of the nanowire can be precisely defined, and the nanowire is not required to be transferred in the subsequent device preparation process. Facilitating large scale integration of devices
At least one semiconductor nanowire 11 is grown on the substrate 1. In some embodiments, a plurality of nanowires 11 are grown on the substrate 1, which are arranged parallel to each other. In other embodiments, nanowires 11 grown on substrate 1 are arranged in a grid structure.
In some embodiments, the semiconductor nanowire 11 and the superconductor layer 12 form a superconducting-semiconductor nanowire heterojunction, the interface of the superconducting-semiconductor nanowire heterojunction is flattened at an atomic level, the problem caused by disordered interfaces can be avoided, and the device prepared by the method has better performance.
In some embodiments, the semiconductor nanowire 11 is partially covered by a superconductor layer 12. The upper part of the semiconductor nanowire 11 is covered with the superconductor layer 12, and the area of the surface of the semiconductor nanowire 11 covered by the superconductor layer 12 can be changed into a topological superconducting area by regulating and controlling a strong magnetic field and an electric field at extremely low temperature, and the tail end of the semiconductor nanowire can detect a 'Mahalanobis zero mode', so that the superconducting-semiconductor nanowire heterojunction can be used as a basic carrier of topological qubits. In some preferred embodiments, one end of the semiconductor nanowire has a length of 1/3 to 2/3 that is covered by the superconductor layer.
In some embodiments, the nanowires are capped at both ends with superconductors, leaving a region of 100 nm-300 nm in between uncovered by the superconductor layer, forming a superconducting josephson junction.
The embodiment of the invention also provides a preparation method of the superconducting-semiconductor nanowire heterojunction, which comprises the following steps:
plating a mask on the CdTe substrate;
throwing HSQ Fox-series electron beam photoresist with preset thickness on the mask, and forming a photoresist three-dimensional pattern on the mask after electron beam exposure development;
throwing positive electron beam photoresist on the mask and the photoresist three-dimensional graph, and forming a groove on the mask after electron beam exposure development;
etching to remove the mask in the groove and removing the positive electron beam photoresist;
and growing PbTe nanowires on the CdTe substrate in the groove by utilizing a molecular beam epitaxy technology, and inclining the photoresist three-dimensional pattern by a preset angle relative to the Pb beam direction, so that the projection part of the photoresist three-dimensional pattern shields part of the PbTe nanowires, and Pb is grown in situ on the non-shielded part to form a heterojunction.
In some embodiments, the HSQ Fox-series electron beam resist is HSQ Fox-15 or HSQ Fox-16; the preset thickness is 500 nm-1000 nm. Preferably, the HSQ Fox-series electron beam photoresist is HSQ Fox-16.
In some embodiments, the shape of the three-dimensional pattern of the photoresist is not particularly limited, so that the heterojunction is not covered on the nanowire of the specific selected area, and in the present invention, the three-dimensional pattern of the photoresist is a cuboid or a cube, preferably a cuboid, for convenience. More preferably, the three-dimensional pattern of the photoresist has a length of 1 μm to 5 μm and a width of 100nm to 500nm.
In some embodiments, the positive electron beam resist is a positive electron beam resist commonly used in the art, including but not limited to PMMA, S18xx series g-Line, SPR955 series i-Line, BCI-3511i-Line, and the like.
In some embodiments, the positive electron beam photoresist may be removed with an organic solvent or oxygen plasma, which may be acetone, xylene, N-ethyl pyrrolidone, N-methyl pyrrolidone, or the like.
In some embodiments, the grooves are 3 μm to 5 μm long and 0.05 μm to 0.3 μm wide.
In some embodiments, the predetermined angle is 20 ° to 70 °.
In some embodiments, the distance between the grooves and the photoresist three-dimensional pattern is 120nm to 300nm.
In some embodiments, the mask may be selectively replaced according to the desired growth of the semiconductor nanowire material, provided that the semiconductor nanowire material cannot be attached thereto, typically an oxide film, which may be, for example, al 2 O 3 Film, siO 2 Thin film or HfO 2 Films, and the like.
In some embodiments, the mask may have a thickness of 10nm to 40nm.
The invention realizes the selective growth of the semiconductor nanowire by plating the mask which is not suitable for growing the semiconductor nanowire on the substrate.
In some embodiments, the method of plating the mask may be any method in the art of plating a thin film, for example, may be magnetron sputtering, molecular beam epitaxy, electron beam evaporation, thermal evaporation, or chemical vapor deposition.
In some embodiments, the method of etching the mask may be a conventional etching method, for example, a dry etching method or a wet etching method, preferably a wet etching method, according to the nature of the mask. For example, when the mask is Al 2 O 3 When the film is formed, a solution commonly used for etching aluminum, such as a transition aluminum etching solution or a TMAH solution with the mass concentration of 25%, can be selected; when the mask is SiO 2 In the case of a film, an HF solution having a mass concentration of 1% may be used.
In some embodiments, when the semiconductor nanowires are grown on the substrate in the grooves using molecular beam epitaxy techniques, the substrate temperature is 270-340 ℃ and the growth speed is 0.2-0.8 nm/min.
By regulating the parameters, the nanowire can be further ensured to grow on the substrate in the groove only, and the nanowire will not be attached to the mask region.
In yet another aspect of the present invention, there is also provided a device comprising the above-described superconducting-semiconductor nanowire heterojunction.
Such devices include, but are not limited to, semiconductor lasers, quantum cascade lasers, tunneling resonance transistors, single electron transistors, molecular oscillators, quantum gyroscopes, quantum lasers, quantum amplifiers, quantum magnetometers, quantum transistors, quantum reservoirs, interferometric element sensors, topological quantum devices, and the like.
In some embodiments, the device is a topological quantum device. The topological quantum device can be applied to a topological quantum computer.
The following are specific examples. The present invention is further described in detail to assist those skilled in the art and researchers in further understanding the present invention, and the technical conditions and the like are not to be construed as limiting the present invention in any way. Any modification made within the scope of the claims of the present invention is within the scope of the claims of the present invention. The drugs and apparatus used in the examples are all routine choices in the art, unless specifically indicated. The experimental methods without specific conditions noted in the examples were carried out according to conventional conditions, such as those described in the literature, books, or recommended by the manufacturer.
Example 1
Fig. 2 is a process flow diagram of preparing a superconducting-semiconductor nanowire heterojunction in this embodiment. In this embodiment, the substrate 1 is CdTe substrate, and the mask layer 2 is Al 2 O 3 The thin film, HSQ Fox-series electron beam photoresist layer 3 is HSQ Fox-16 electron beam photoresist layer, positive electron beam photoresist layer 4 is PMMA photoresist layer, nanowire 5 is PbTe nanowire, and heterogeneous material layer 6 is Pb superconducting material.
The method comprises the following specific steps:
1) As shown in fig. 1 (a) to (d), after the CdTe substrate is cleaned,plating 40nm Al on CdTe substrate by magnetron sputtering method 2 O 3 A film. Subsequently, the HSQ Fox-16 electron beam photoresist is tiled on Al 2 O 3 Forming a photoresist layer with the thickness of 700nm on the film, and forming a photoresist three-dimensional pattern 31 with the length of 3 mu m, the width of 200nm and the height of 700nm after electron beam exposure and development in a selected area;
2) As shown in the graphs (e) to (h) of FIG. 1, al of the structure formed in step 1) 2 O 3 The film surface was coated with a 200nm thick PMMA positive electron beam resist layer and developed by electron beam exposure to form grooves 41 of 3 μm length and 100nm width to expose Al 2 O 3 A film. The grooves 41 are offset parallel to the photoresist three-dimensional pattern 31 and are 200nm apart. Then placing the sample in a transition aluminum etching solution preheated to 50 ℃ for 5-8 s, and removing Al in the groove 41 2 O 3 The film exposes the CdTe substrate. Then washing the PMMA positive electron beam photoresist layer with acetone;
3) As shown in (i) to (k) of fig. 1, the CdTe substrate temperature was controlled to 330 ℃ using molecular beam epitaxy technique, and PbTe semiconductor nanowires were grown in the grooves 41 using PbTe molecular source at a growth rate of 0.4nm/min according to the beam direction shown in (i). The substrate was then cooled by passing liquid nitrogen and the CdTe substrate was tilted 60℃to become Al 2 O 3 The film and part of the PbTe semiconductor nanowires are grown in situ to cover the Pb superconducting material, and the PbTe semiconductor nanowires shielded by the projection part of the photoresist three-dimensional pattern 31 are not covered with the Pb superconducting material.
Structural characterization and performance testing
1. PbTe-CdTe, pb-PbTe interface lattice matching
The Pb-PbTe nanowire heterojunction prepared in example 1 was characterized by a Cross-sectional TEM (Transmission Electron microscope), as shown in FIGS. 3 to 5. Fig. 3 shows a cross-sectional view of a Pb-PbTe nanowire heterojunction grown on CdTe, fig. 4 is an enlarged view at the PbTe-CdTe interface, and fig. 5 is an enlarged view at the Pb-PbTe interface. As can be seen from fig. 4 and 5, the crystal lattice at the interface of PbTe-CdTe and Pb-PbTe is perfectly matched, and there are no crystal lattice defects at the interface.
2. Electron mobility of PbTe nanowires
In combination with a preparation method of a conventional field effect tube in the field, the PbTe nanowire field effect tube is prepared, the structure is shown in fig. 6, a curve of conductance-Gate voltage (G-Gate voltage) of the PbTe nanowire field effect tube is tested and fitted, so that mobility is calculated, and the specific method can be referred to in the following literature: the preparation method comprises the steps of (1) preparing,towards high mobility InSb nanowire devices nanotechnology 26,215202 (2015), the results are shown in fig. 7. The electron mobility of the device reaches 1.41×10 4 cm 2 The mobility of the InAs or InSb nanowire which is obtained by the molecular beam epitaxy selective region method is improved by one order of magnitude compared with that of the InAs or InSb nanowire which is also obtained by the molecular beam epitaxy selective region method, which proves that the high crystal quality interface of PbTe-CdTe is beneficial to improving the electron mobility.
3. Pb-PbTe nanowire (superconducting-semiconductor nanowire) superconducting energy gap
The superconducting energy gap induced by the neighbor effect depends on the energy gap size of the superconducting material itself and the interface properties of the superconducting-semiconductor. The reported superconductive energy gaps in Al-InAs nanowires and Al-InSb nanowire systems which are formed by in-situ covering of a superconductive material Al through molecular beam epitaxy are about 0.2meV, and are equivalent to the superconductive energy gaps of Al.
The superconducting energy gap of Pb material is about 1meV, pb is covered on PbTe nanowire in situ by molecular beam epitaxy in the invention, and an atomically flat interface can be obtained, so that the heterojunction of the invention can induce a larger energy gap in a PbTe system. A large superconducting energy gap is beneficial for topological quantum devices.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present invention, which facilitate a specific and detailed understanding of the technical solutions of the present invention, but are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. It should be understood that, based on the technical solutions provided by the present invention, those skilled in the art may obtain technical solutions through logical analysis, reasoning or limited experiments, which are all within the scope of protection of the appended claims. The scope of the patent is therefore intended to be covered by the appended claims, and the description and drawings may be interpreted as illustrative of the contents of the claims.

Claims (10)

1. A superconducting-semiconductor nanowire heterojunction, comprising:
a substrate, and a semiconductor nanowire and a superconductor layer grown on the substrate, at least a portion of the superconductor layer being in direct contact with the semiconductor nanowire;
the semiconductor nanowire is made of a compound semiconductor PbTe, the superconductor layer is made of an element superconductor Pb, and the substrate is made of a compound semiconductor CdTe.
2. The superconducting-semiconductor nanowire heterojunction according to claim 1, wherein the semiconductor nanowire is 3-5 μm long and 0.05-0.3 μm wide.
3. The superconducting-semiconductor nanowire heterojunction of claim 1, wherein the semiconductor nanowire is parallel to the substrate surface.
4. The superconducting-semiconductor nanowire heterojunction of claim 1, wherein the semiconductor nanowire upper portion covers the superconductor layer.
5. The superconducting-semiconductor nanowire heterojunction according to claim 4, wherein one end of the semiconductor nanowire has a length of 1/3 to 2/3 that of the semiconductor nanowire, and is covered by the superconductor layer.
6. The superconducting-semiconductor nanowire heterojunction according to claim 4, wherein two ends of the semiconductor nanowire are covered by superconductors, and a region leaving 100 nm-300 nm in the middle is not covered by the superconductor layer.
7. A method of preparing a superconducting-semiconductor nanowire heterojunction as claimed in any one of claims 1 to 6, comprising the steps of:
plating a mask on the CdTe substrate;
throwing HSQ Fox-series electron beam photoresist with preset thickness on the mask, and forming a photoresist three-dimensional pattern on the mask after electron beam exposure development;
throwing positive electron beam photoresist on the mask and the photoresist three-dimensional graph, and forming a groove on the mask after electron beam exposure development;
etching to remove the mask in the groove and removing the positive electron beam photoresist;
and growing PbTe nanowires on the CdTe substrate in the groove by utilizing a molecular beam epitaxy technology, and inclining the photoresist three-dimensional pattern by a preset angle relative to the Pb beam direction, so that the projection part of the photoresist three-dimensional pattern shields part of the PbTe nanowires, and Pb is grown in situ on the non-shielded part to form a heterojunction.
8. The method for preparing a superconducting-semiconductor nanowire heterojunction according to claim 7, wherein the preset thickness is 500-1000 nm, the preset angle is 20-70 degrees, and the distance between the groove and the photoresist three-dimensional pattern is 120-300 nm.
9. A device comprising a superconducting-semiconductor nanowire heterojunction as claimed in any one of claims 1 to 6.
10. The device of claim 9, wherein the device is a topological quantum device.
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