CN117936523A - Multi-layer chip stacking and packaging structure - Google Patents
Multi-layer chip stacking and packaging structure Download PDFInfo
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- CN117936523A CN117936523A CN202211733411.2A CN202211733411A CN117936523A CN 117936523 A CN117936523 A CN 117936523A CN 202211733411 A CN202211733411 A CN 202211733411A CN 117936523 A CN117936523 A CN 117936523A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000017525 heat dissipation Effects 0.000 claims abstract description 19
- 230000000712 assembly Effects 0.000 claims abstract description 7
- 238000000429 assembly Methods 0.000 claims abstract description 7
- 239000004519 grease Substances 0.000 claims description 5
- 229920001296 polysiloxane Polymers 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 1
- 230000004308 accommodation Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 3
- 238000000465 moulding Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The application relates to the technical field of chip packaging, in particular to a multi-layer chip stacking packaging structure, which comprises a substrate, a multi-layer chip assembly and a radiator; the multi-layer chip assemblies are vertically overlapped on the substrate, each layer of chip assembly comprises a plurality of chips which are arranged at intervals in the circumferential direction, the chips in two adjacent layers of chip assemblies are staggered to form an accommodating space, and the side surfaces of the chips facing the accommodating space in the same column in the vertical direction are positioned on the same plane; the radiator is the polygon column form setting, and the radiator is located accommodation space, and the lateral surface of radiator is pasted with each chip and faces accommodation space's side mutually. The application has the effect of improving the stacking stability of a plurality of chips and improving the heat dissipation performance of the chips.
Description
Technical Field
The application relates to the technical field of chip packaging, in particular to a multilayer chip stacking packaging structure.
Background
With the rapid development of the semiconductor industry, electronic products are miniaturized to be thinner and thinner to meet the demands of users and to increase the product performance and the memory, so that the semiconductor packaging structure adopts a plurality of chip stacking (Stack-Die) technologies or a chip lead stacking (FOW) technology to Stack two or more chips in a single packaging structure, thereby reducing the packaging volume of the product and improving the product performance. Such a stacked product (memory card/memory card) is usually provided with 2 types of chips, a memory chip and a control chip, and is packaged in the same substrate unit by stacking.
In the related art, a plurality of chips are stacked by rotating the chips in a three-dimensional space, if the overlapping areas between the adjacent chips are more, the heat dissipation performance of the chips is affected, and if the overlapping areas between the adjacent chips are less, the chips are rotated in the three-dimensional space, so that the chips above are easily unstable, and the packaging of the chips on the substrate is not facilitated.
Disclosure of Invention
In order to improve the stability of stacking a plurality of chips and improve the heat dissipation performance of the chips, the application provides a multi-layer chip stacking and packaging structure.
The application provides a multilayer chip stacking and packaging structure which adopts the following technical scheme:
A multi-layered chip stack package structure, comprising:
A substrate;
The multi-layer chip assembly is stacked on the substrate in the up-down direction, each layer of chip assembly comprises a plurality of chips which are arranged at intervals in the circumferential direction, the chips in two adjacent layers of chip assemblies are arranged in a staggered mode, an accommodating space is enclosed, and the side faces, facing the accommodating space, of the chips in the same column in the up-down direction are located on the same plane; and
The radiator is arranged in a polygonal column shape, the radiator is positioned in the accommodating space, and the outer side face of the radiator is attached to the side face of each chip facing the accommodating space.
By adopting the technical scheme, in the first aspect, the two ends of the chip on the upper layer are overlapped with the end parts of the two adjacent chips on the lower layer, so that the middle part of the chip on the upper layer is suspended, the overlapped area between the adjacent chips in the stacked chips can be reduced, and the heat dissipation performance of the chips is improved; in the second aspect, two ends of the chip on the upper layer are lapped at the ends of two adjacent chips on the lower layer, so that the stability of chip stacking can be enhanced, the problem of chip instability caused by three-dimensional rotation stacking of a plurality of chips can be solved, and the situation that the chip collapses can be avoided when the chips are packaged after the chips are stacked; in the third aspect, the plurality of chips are stacked to enclose the accommodating space, the radiator can be arranged in the accommodating space, the outer side face of the radiator and the side face of each chip, which faces the accommodating space, can be attached to each other, so that heat generated by each chip can be directly dissipated through the radiator, and the heat dissipation performance of the chip is further improved.
Optionally, the packaging structure further comprises a plastic sealing layer, wherein the plastic sealing layer covers the substrate and coats the plurality of layers of the chip components, and the top end of the radiator is positioned outside the plastic sealing layer.
By adopting the technical scheme, when the chip packaging is realized, the chip can radiate heat through the top end of the radiator.
Optionally, a plurality of heat dissipation fins are arranged at the top end of the heat sink.
By adopting the technical scheme, the heat dissipation performance of the chip can be improved.
Optionally, a layer of heat-conducting silicone grease is arranged on the periphery of the radiator.
By adopting the technical scheme, the heat conduction silicone grease can fill the gap between the side surface of the chip and the side surface of the radiator on one hand, and can improve the heat conduction efficiency between the chip and the radiator on the other hand, thereby improving the heat dissipation performance of the chip.
Optionally, each of the chips is rectangular.
Through adopting above-mentioned technical scheme, the both ends overlap joint of upper chip is in two adjacent chip tip of lower floor, and the chip is the cuboid, and the chip middle part is unsettled, can reduce the chip and overlap the proportion that the area accounts for the chip surface, when guaranteeing chip stability, improves the heat dispersion of chip.
Optionally, a plurality of the chips in the same layer of the chip assembly are uniformly spaced.
By adopting the technical scheme, the stacking stability of a plurality of chips can be improved.
Optionally, the plurality of chips at the lowest layer are electrically connected with the substrate, and the plurality of chips in the same column are electrically connected from top to bottom.
Through adopting above-mentioned technical scheme, simplified the structure of lead wire, avoid appearing the condition of interference between the lead wire, be favorable to realizing holistic electric connection.
Optionally, among the plurality of chips in the same column from top to bottom, a plurality of chips keep away from the one end of accommodation space is ladder-shaped setting, and is up and down to connect through the lead wire between two adjacent chips in same column.
Through adopting above-mentioned technical scheme, be ladder-type to a plurality of chip tip in same row from top to bottom, can improve the stability that the chip piles up, be favorable to connecting wire between two adjacent chips from top to bottom simultaneously to realize holistic electric connection.
Optionally, the radiator middle part runs through and is equipped with the louvre, the radiator is equipped with the inside wall in louvre is equipped with a plurality of fin.
By adopting the technical scheme, after the heat of the chip is transferred to the radiator, the heat can be directly radiated to the outside through the radiating fins, and the radiating performance of the chip can be improved.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the two ends of the upper chip are lapped at the ends of the two adjacent lower chips, so that the middle of the upper chip is suspended, the overlapping area between the adjacent chips in the stacked chips can be reduced, and the heat dissipation performance of the chips is improved;
2. The two ends of the upper chip are lapped at the ends of the two adjacent lower chips, so that the stacking stability of the chips can be enhanced, and the collapse of the chips can be avoided;
3. The plurality of chips are stacked to enclose the accommodating space, the radiator can be arranged in the accommodating space, the outer side face of the radiator and the side face of each chip facing the accommodating space can be attached, so that heat generated by each chip can be directly dissipated through the radiator, and the heat dissipation performance of the chip is further improved.
Drawings
FIG. 1 is a schematic diagram of a multi-layer chip stack package structure according to an embodiment of the present application;
FIG. 2 is a schematic diagram of the multi-layered chip stack package structure (with heat spreader and plastic encapsulant layers omitted) of FIG. 1;
FIG. 3 is a schematic diagram of the structure of the substrate and a layer of chip assembly of FIG. 1;
FIG. 4 is a schematic diagram of the multi-layer chip stack package structure (stealth molding layer) of FIG. 1;
Fig. 5 is a schematic structural diagram of the multi-layer chip stack package structure (the hidden plastic layer and the heat sink fins outside the heat sink) in fig. 1.
Reference numerals illustrate: 1. a substrate; 2. a chip assembly; 21. a chip; 22. an accommodation space; 3. a heat sink; 31. a heat radiation fin; 32. a heat radiation hole; 4. a plastic sealing layer; 5. and (5) a lead wire.
Detailed Description
The application is described in further detail below with reference to fig. 1-5.
The embodiment of the application discloses a multilayer chip stacking and packaging structure. Referring to fig. 1, the multi-layered chip stack package structure includes a substrate 1, a multi-layered chip assembly 2 (the chip assembly 2 is located within a molding layer 4, and thus the chip assembly 2 is not shown in fig. 1), a heat sink 3, and the molding layer 4.
Referring to fig. 2 and 3, the multi-layer chip assemblies 2 are stacked on the substrate 1 in the up-down direction, each layer of chip assemblies 2 includes a plurality of chips 21 arranged at intervals in the circumferential direction, and the chips 21 in the adjacent two layers of chip assemblies 2 are arranged in an staggered manner, that is, two ends of the chip 21 in the upper layer are stacked on the ends of the two adjacent chips 21 in the lower layer, and the two adjacent chips 21 in the lower layer play a supporting role for the chip 21 in the upper layer, so that the middle of the chip 21 in the upper layer is suspended.
In the existing stacking manner of the chips 21, the plurality of chips 21 are rotationally stacked in the three-dimensional space, so that the middle parts of the adjacent chips 21 are contacted, and as can be understood, the end parts of the chips 21 are contacted with the outside, so that the heat at the end parts of the chips 21 is easily transferred to the outside, the heat at the middle parts of the chips 21 is easily gathered, and the middle parts of the chips 21 are not easy to dissipate heat. In the application, the chips 21 on the upper and lower layers are contacted through the end parts, so that the middle part of the chip 21 is suspended, and the heat dissipation effect of the middle part of the chip 21 can be improved.
The chips 21 of the upper and lower layers are contacted through the end parts, and compared with the chips 21 of the upper and lower layers contacted through the middle parts, the two adjacent chips 21 of the lower layer simultaneously play a supporting role on one chip 21 of the upper layer, so that the stability of the chips 21 of the upper layer can be improved, and the overlapping area between the adjacent chips 21 in the stacked chips 21 can be reduced, thereby improving the heat dissipation performance of the chips 21.
The two ends of the upper layer of chips 21 are lapped at the ends of the lower layer of adjacent two chips 21, so that the stacking stability of the chips 21 can be enhanced, and the problem of instability of the chips 21 caused by three-dimensional rotation stacking of a plurality of chips 21 can be solved. The plurality of chips 21 in the same layer of chip assembly 2 are uniformly arranged at intervals, so that the stacking stability of the plurality of chips 21 can be improved, and the stacking of the chips 21 is not limited by the number of stacking layers.
The surface of the chip 21 may be square or rectangular, in this embodiment, the surface of each chip 21 is rectangular, two ends of the upper chip 21 are overlapped with two adjacent ends of the lower chip 21, the surface of the chip 21 is rectangular, the middle of the chip 21 is suspended, the proportion of the overlapping area of the chip 21 to the surface of the chip 21 can be reduced, the stability of the chip 21 is ensured, and the heat dissipation performance of the chip 21 is improved.
Referring to fig. 2, each chip 21 may be directly or indirectly electrically connected to the substrate 1. In this embodiment, the plurality of chips 21 located at the lowest layer are all electrically connected to the substrate 1, specifically, connected through the leads 5, and may be connected through solder balls in other embodiments. The chips 21 in the same column are electrically connected, namely, the upper chip 21 is electrically connected with the lower chip 21 to realize indirect electrical connection with the substrate 1, so that the connection simplifies the structure of the leads 5, avoids interference between the leads 5, and is beneficial to realizing integral electrical connection.
Referring to fig. 2, a plurality of chips 21 are stacked and stacked alternately to enclose an accommodating space 22, and among the plurality of chips 21 in the same column from top to bottom, one end of the plurality of chips 21 away from the accommodating space 22 is arranged in a step shape, that is, among the two adjacent chips 21 in the upper and lower directions, the end of the chip 21 in the lower layer away from the accommodating space 22 is located at the outer side of the end of the chip 21 in the upper layer away from the accommodating space 22, and the two adjacent chips 21 in the same column from top to bottom are connected by a lead 5. The ends of the chips 21 in the same column are in a step shape, so that the stacking stability of the chips 21 can be improved, and meanwhile, connection between two adjacent chips 21 in the up-down direction is facilitated, and thus integral electric connection is realized.
The side surfaces of the chips 21 facing the accommodation space 22 in the same column are on the same plane, and referring to fig. 5, the heat sink 3 is provided in a polygonal column shape, the heat sink 3 is positioned in the accommodation space 22, and the outer side surface of the heat sink 3 is attached to the side surface of each chip 21 facing the accommodation space 22.
In this embodiment, the number of chips 21 in each layer of the chip assembly 2 is four, so that the heat sink 3 has an octagon shape. In other embodiments, the number of chips 21 in each layer of the chip assembly 2 may be three, five, six or more.
The plurality of chips 21 are staggered and stacked to enclose the accommodating space 22, so that on one hand, the stacking stability can be improved, the stackable layers of the chips 21 can be improved, on the other hand, the radiator 3 can be arranged in the accommodating space 22, the outer side surface of the radiator 3 can be attached to the side surface of each chip 21 facing the accommodating space 22, and the heat generated by each chip 21 can be directly dissipated through the radiator 3, so that the heat dissipation performance of the chips 21 can be further improved.
The periphery of the radiator 3 is provided with a layer of heat-conducting silicone grease, and the heat-conducting silicone grease can fill gaps between the side face of the chip 21 and the side face of the radiator 3 on one hand, and can improve the heat-conducting efficiency between the chip 21 and the radiator 3 on the other hand, so that the heat-radiating performance of the chip 21 is improved.
The plastic layer 4 covers the substrate 1 and coats the multi-layer chip assembly 2, the top end of the radiator 3 is positioned outside the plastic layer 4, the plastic layer 4 realizes the packaging of the chip 21, and meanwhile, the chip 21 can radiate heat through the top end of the radiator 3. Further, the top end of the radiator 3 is provided with a plurality of radiating fins 31, and heat of the radiator 3 is transferred to the outside through the radiating fins 31, so that the radiating performance of the chip 21 can be improved.
After stacking the chips 21, injecting a molding compound onto the substrate 1, where if the stacking stability of the chips 21 is insufficient, the flow of the molding compound may cause the chip 21 to collapse, so as to affect the molding of the chip 21. In the application, the chips 21 are stacked into a tower shape, the plastic packaging glue flows to fill the gaps among the chips 21, and the inner sides of the chips 21 are provided with the support of the radiator 3, so that the stability of the chips 21 can be improved, the collapse of the chips 21 can be avoided as much as possible, and the smooth packaging of the chips 21 is ensured.
The middle part of the radiator 3 is provided with a radiating hole 32 in a penetrating way, the inner side wall of the radiator 3 provided with the radiating hole 32 is provided with a plurality of radiating fins 31, and after the heat of the chip 21 is transferred to the radiator 3, the heat can be directly radiated to the outside through the radiating fins 31, so that the radiating performance of the chip 21 can be improved.
The implementation principle of the multilayer chip stacking and packaging structure provided by the embodiment of the application is as follows: the two ends of the upper chip 21 are lapped at the end parts of the two adjacent chips 21 of the lower layer, so that the middle part of the upper chip 21 is suspended, on one hand, the heat accumulation in the middle part of the chips 21 is avoided, and on the other hand, the overlapping area between the adjacent chips 21 in the stacked chips 21 can be reduced, thereby improving the heat dissipation performance of the chips 21; on the other hand, the stability of stacking the chips 21 can be enhanced, the problem of unstability of the chips 21 caused by three-dimensional rotation stacking of the chips 21 can be solved, and collapse of the chips 21 can be avoided when the chips 21 are packaged after the chips 21 are stacked.
The plurality of chips 21 are stacked and are tower-shaped, and enclose accommodating space 22, on the one hand, the stability of stacking chips 21 is enhanced, on the other hand, the wiring is convenient for, and the whole electric connection is realized, on the other hand, radiator 3 can be arranged in accommodating space 22, and radiator 3 lateral surface and each chip 21 lateral surface facing accommodating space 22 can all paste mutually for the heat that each chip 21 produced can directly give off heat through radiator 3, further improves the heat dispersion of chip 21.
The above embodiments are not intended to limit the scope of the present application, so: all equivalent changes in structure, shape and principle of the application should be covered in the scope of protection of the application.
Claims (9)
1. A multi-layered chip stack package structure, comprising:
a substrate (1);
the multi-layer chip assembly (2), the multi-layer chip assembly (2) is stacked on the base plate (1) up and down, each layer of chip assembly (2) comprises a plurality of chips (21) which are arranged at intervals in the circumferential direction, the chips (21) in two adjacent layers of chip assemblies (2) are arranged in a staggered manner, an accommodating space (22) is enclosed, and the side surfaces of the chips (21) facing the accommodating space (22) in the same column up and down are positioned on the same plane; and
The radiator (3) is arranged in a polygonal column shape, the radiator (3) is positioned in the accommodating space (22), and the outer side face of the radiator (3) is attached to the side face of each chip (21) facing the accommodating space (22).
2. The multi-layer chip stack package structure according to claim 1, further comprising a plastic layer (4), wherein the plastic layer (4) covers the substrate (1) and encapsulates the multi-layer chip assembly (2), and the top end of the heat sink (3) is located outside the plastic layer (4).
3. The multi-layered chip stack package structure according to claim 2, wherein the heat sink (3) has a plurality of heat dissipation fins (31) at a top end thereof.
4. The multi-layered chip stack package structure according to claim 1, wherein the heat spreader (3) is provided with a layer of thermally conductive silicone grease on its peripheral surface.
5. The multilayer chip stack package according to claim 1, wherein each of the chips (21) is provided in a rectangular parallelepiped shape.
6. The multi-layered chip stack package structure according to claim 1, wherein a plurality of the chips (21) in the same layer of the chip assembly (2) are arranged at uniform intervals.
7. The multilayer chip stack package structure according to claim 1, wherein the plurality of chips (21) located at the lowermost layer are electrically connected to the substrate (1), and the plurality of chips (21) located in the same column are electrically connected to each other.
8. The multilayer chip stack package structure according to claim 7, wherein among the plurality of chips (21) in the same column from top to bottom, one end of the plurality of chips (21) away from the accommodating space (22) is arranged in a step-like manner, and two adjacent chips (21) in the same column from top to bottom are connected by a lead (5).
9. The multi-layer chip stacking and packaging structure according to claim 1, wherein a heat dissipation hole (32) is formed in the middle of the heat sink (3) in a penetrating manner, and a plurality of heat dissipation fins (31) are arranged on the inner side wall of the heat sink (3) with the heat dissipation hole (32).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211733411.2A CN117936523A (en) | 2022-12-30 | 2022-12-30 | Multi-layer chip stacking and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211733411.2A CN117936523A (en) | 2022-12-30 | 2022-12-30 | Multi-layer chip stacking and packaging structure |
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| Publication Number | Publication Date |
|---|---|
| CN117936523A true CN117936523A (en) | 2024-04-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211733411.2A Pending CN117936523A (en) | 2022-12-30 | 2022-12-30 | Multi-layer chip stacking and packaging structure |
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| CN (1) | CN117936523A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100327424A1 (en) * | 2009-06-24 | 2010-12-30 | Henning Braunisch | Multi-chip package and method of providing die-to-die interconnects in same |
| US20200126882A1 (en) * | 2018-10-22 | 2020-04-23 | Samsung Electronics Co., Ltd. | Semiconductor package |
| US20200227377A1 (en) * | 2017-12-29 | 2020-07-16 | Intel Corporation | Microelectronic assemblies |
| CN111554672A (en) * | 2020-05-14 | 2020-08-18 | 甬矽电子(宁波)股份有限公司 | Chip stacking structure and chip stacking method |
| CN112768443A (en) * | 2021-04-08 | 2021-05-07 | 甬矽电子(宁波)股份有限公司 | Multilayer stack packaging structure and preparation method thereof |
-
2022
- 2022-12-30 CN CN202211733411.2A patent/CN117936523A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100327424A1 (en) * | 2009-06-24 | 2010-12-30 | Henning Braunisch | Multi-chip package and method of providing die-to-die interconnects in same |
| US20200227377A1 (en) * | 2017-12-29 | 2020-07-16 | Intel Corporation | Microelectronic assemblies |
| US20200126882A1 (en) * | 2018-10-22 | 2020-04-23 | Samsung Electronics Co., Ltd. | Semiconductor package |
| CN111554672A (en) * | 2020-05-14 | 2020-08-18 | 甬矽电子(宁波)股份有限公司 | Chip stacking structure and chip stacking method |
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