CN117936455A - Manufacturing method of semiconductor structure and structure thereof - Google Patents
Manufacturing method of semiconductor structure and structure thereof Download PDFInfo
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- CN117936455A CN117936455A CN202211255723.7A CN202211255723A CN117936455A CN 117936455 A CN117936455 A CN 117936455A CN 202211255723 A CN202211255723 A CN 202211255723A CN 117936455 A CN117936455 A CN 117936455A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 241
- 238000000034 method Methods 0.000 claims abstract description 195
- 230000008569 process Effects 0.000 claims abstract description 176
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000007789 gas Substances 0.000 claims description 53
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 48
- 229910052786 argon Inorganic materials 0.000 claims description 24
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 24
- 239000001301 oxygen Substances 0.000 claims description 24
- 229910052760 oxygen Inorganic materials 0.000 claims description 24
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 16
- LGPPATCNSOSOQH-UHFFFAOYSA-N 1,1,2,3,4,4-hexafluorobuta-1,3-diene Chemical compound FC(F)=C(F)C(F)=C(F)F LGPPATCNSOSOQH-UHFFFAOYSA-N 0.000 claims description 15
- 239000004341 Octafluorocyclobutane Substances 0.000 claims description 15
- BCCOBQSFUDVTJQ-UHFFFAOYSA-N octafluorocyclobutane Chemical compound FC1(F)C(F)(F)C(F)(F)C1(F)F BCCOBQSFUDVTJQ-UHFFFAOYSA-N 0.000 claims description 15
- 235000019407 octafluorocyclobutane Nutrition 0.000 claims description 15
- 230000005611 electricity Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 172
- 239000000463 material Substances 0.000 description 26
- 229920002120 photoresistant polymer Polymers 0.000 description 23
- 239000011800 void material Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
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- 150000002484 inorganic compounds Chemical class 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000006552 photochemical reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The embodiment of the disclosure relates to the field of semiconductors, and provides a manufacturing method of a semiconductor structure and the structure thereof, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate is provided with a conductive structure and an insulating structure covering the conductive structure; forming a mask layer, wherein the mask layer is positioned on the insulating structure and is provided with a first opening exposing the top surface of a first part of the insulating structure; etching the insulating structure by adopting a first etching process to form a first groove and a second groove which are communicated, wherein the inner side surface of the second groove is recessed towards the inner side surface far from the first groove compared with the inner side surface of the first groove; etching the side wall of the mask layer exposed by the first opening by adopting a second etching process so as to expand the first opening into a second opening and expose the top surface of a second part of the insulating structure; etching the insulating structure by adopting a third etching process to form a through hole communicated with the bottom of the second groove; and the conductive column is formed and electrically connected with the conductive structure, so that the reliability of the conductive column can be improved.
Description
Technical Field
The embodiment of the disclosure relates to the field of semiconductors, in particular to a manufacturing method of a semiconductor structure and the structure thereof.
Background
An Integrated Circuit (IC) is a circuit in which a unit circuit or some functional circuits, even the functional circuits of a whole machine, are integrally formed on a single chip and then packaged in a case for easy mounting and soldering. Integrated circuits include films, semiconductor integrated circuits and hybrid integrated circuits, in which semiconductor processes are used to fabricate transistors, resistors, capacitors and wiring on very small semiconductor materials or insulating substrates to form a complete circuit.
In integrated circuits, it is important to form electrical connections between different conductive layers, however, as the process is continuously scaled down, resulting in formation of conductive pillars with voids during the process of forming electrical connections between different conductive layers, which affects the reliability of the conductive pillars.
Disclosure of Invention
The embodiment of the disclosure provides a manufacturing method of a semiconductor structure and the structure thereof, which can at least improve the reliability of a conductive column.
According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a conductive structure and an insulating structure covering the conductive structure, and the insulating structure covers the top surface of the conductive structure; forming a mask layer, wherein the mask layer is positioned on the insulating structure and is provided with a first opening exposing the top surface of a first part of the insulating structure; etching the insulating structure with a first thickness along the first opening by adopting a first etching process to form a first groove and a second groove which are communicated in the insulating structure, wherein the first groove is positioned between the first opening and the second groove, and the inner side surface of the second groove is recessed towards the inner side surface far away from the first groove compared with the inner side surface of the first groove; etching the side wall of the mask layer exposed by the first opening by adopting a second etching process so as to expand the first opening into a second opening and expose the top surface of a second part of the insulating structure; etching the insulating structure along the second opening by adopting a third etching process until the top surface of the conductive structure is exposed, so as to form a through hole communicated with the bottom of the second groove, and further enlarging the opening size of the first groove; and forming a conductive column which fills the through hole and at least part of the second groove and is electrically connected with the conductive structure.
In some embodiments, prior to forming the conductive pillars, further comprising: etching the side wall of the mask layer exposed by the second opening by adopting a fourth etching process, so that the second opening is enlarged to be a third opening and the top surface of a third part of the insulating structure is exposed; and etching the insulating structure along the third opening by adopting a fifth etching process so as to enlarge the opening size of the first groove.
In some embodiments, the process time period of the fourth etching process is longer than the process time period of the second etching process.
In some embodiments, the process duration of the fourth etching process is 1.3-1.7 times the process duration of the second etching process.
In some embodiments, the process parameters of the fifth etching process include: the etching gas comprises at least one of hexafluorobutadiene, octafluorocyclobutane or difluoromethane, and the radio frequency is 40 KHz-60 MHz.
In some embodiments, the process parameters of the fourth etching process include: the etching gas comprises oxygen and argon, the gas flow of the oxygen is 10-15 sccm, the gas flow of the argon is 150-160 sccm, the radio frequency power is 600-1000W, and the radio frequency is 30-60 MHz.
In some embodiments, the insulating structure comprises: the insulating layer and etching stop layer, etching stop layer covers the surface of electrically conductive structure, the insulating layer is located the surface of etching stop layer still includes before the formation conductive column: and etching the exposed etching stop layer until the top surface of the conductive structure is exposed.
In some embodiments, the process parameters of the first etching process include: the etching gas comprises octafluorocyclobutane, hexafluorobutadiene, oxygen and argon, the gas flow rate of octafluorocyclobutane is 50-65 sccm, the gas flow rate of hexafluorobutadiene is 55-70 sccm, the gas flow rate of oxygen is 55-65 sccm, the gas flow rate of argon is 180-200 sccm, and the radio frequency is 40 KHz-60 MHz.
In some embodiments, the process parameters of the second etching process include: the etching gas comprises oxygen and argon, the gas flow of the oxygen is 10-15 sccm, the gas flow of the argon is 150-160 sccm, the etching power is 600-1000W, the radio frequency is 30-60 MHz, and the etching duration is 10-15 s.
In some embodiments, the process parameters of the third etching process include: the etching gas comprises any one of hexafluorobutadiene, octafluorocyclobutane or difluoromethane, and the radio frequency is 40-60 MHz.
In some embodiments, after forming the conductive pillars, further comprising: and flattening the conductive column and the insulating structure until the conductive column in the second groove is removed.
According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a semiconductor structure, including: a substrate having a conductive structure thereon; the conductive column is located the top surface of conductive structure and with conductive structure electricity is connected, the conductive column includes first conducting layer and second conducting layer, first conducting layer is located the second conducting layer with between the conductive structure, just the lateral surface of second conducting layer is compared the lateral surface orientation of first conducting layer is kept away from the lateral surface protrusion of first conducting layer.
In some embodiments, further comprising: and the insulating structure covers the side wall of the conductive column.
In some embodiments, the second conductive layer has a width of 180 to 200nm.
In some embodiments, the first conductive layer has a height of 1600nm to 2400nm and a width of 150nm to 160nm.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages: the insulating structure is etched along the first opening of the mask layer by adopting a first etching process in the process of forming the conductive column so as to form a first groove and a second groove which are communicated, the opening size of the first opening is enlarged by adopting a second etching process so as to form a second opening, the insulating structure is etched along the second opening by adopting a third etching process until the top surface of the conductive structure is exposed, and the opening size of the first groove is enlarged by adopting a third etching process, so that the filling performance of the conductive column material can be improved in the subsequent process step of forming the conductive column, the gap formed in the conductive column can be reduced, and the reliability of the formed conductive column is improved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 to 7 are schematic structural views of a method for fabricating a semiconductor structure according to an embodiment of the disclosure;
fig. 8 to 16 are schematic structural views corresponding to steps of another method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 17 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure.
Detailed Description
As known from the background art, with the continuous miniaturization of the integration level, in the process of forming the conductive column, due to the large depth-to-width ratio of the conductive column groove to be formed, the angle deviation or fine fluctuation of the etching ions striking the sidewall of the groove in the plasma etching can be larger in the sidewall of the conductive column groove formed by the etching than in other parts, so that a void cavity is easy to be formed in the process of filling the conductive column material in the subsequent process of forming the conductive column.
However, in order to improve the void space, a groove is usually formed by etching, then a conductive post is formed in the groove, then the void space in the conductive post is exposed by etching the conductive post, and then a new conductive film layer is grown to eliminate the void space by etching-depositing-etching-depositing, but such a process results in an increase of process steps and process cost.
The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, a mask layer is formed on an insulating structure, the mask layer is provided with a first opening, the insulating structure is etched along the first opening to form a first groove and a second groove which are communicated, the first groove is positioned between the first opening and the second groove, the inner side surface of the second groove is recessed away from the inner side surface of the first groove compared with the inner side surface of the first groove, the first opening is enlarged to form a second opening through a second etching process, the insulating structure is etched along the second opening until the top surface of the conductive structure is exposed, and the opening size of the first groove is enlarged while a through hole is formed, so that the filling performance of a conductive column material is improved in the process of forming the conductive column, and therefore, a void hole in the conductive column is improved, and the reliability of the formed conductive column is improved.
Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. The technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Referring to fig. 1 to 7, fig. 1 to 7 are schematic structural diagrams corresponding to steps of a method for fabricating a semiconductor structure according to an embodiment of the disclosure,
Specifically, the method for manufacturing the semiconductor structure comprises the following steps: providing a substrate 100, wherein the substrate 100 is provided with a conductive structure 110 and an insulating structure 120 covering the conductive structure 110, and the insulating structure 120 covers the top surface of the conductive structure 110; forming a mask layer 130, wherein the mask layer 130 is located on the insulating structure 120, and the mask layer 130 has a first opening 131 therein exposing a top surface of a first portion of the insulating structure 120; etching the insulating structure 120 with the first thickness along the first opening 131 by adopting a first etching process to form a first groove 140 and a second groove 150 which are communicated in the insulating structure 120, wherein the first groove 140 is positioned between the first opening 131 and the second groove 150, and the inner side surface of the second groove 150 is recessed towards the inner side surface far from the first groove 140 compared with the inner side surface of the first groove 140; etching the side wall of the mask layer 130 exposed by the first opening 131 by adopting a second etching process, so that the first opening 131 is enlarged to be a second opening 132 and the top surface of the second part of the insulating structure 120 is exposed; etching the insulating structure along the second opening by a third etching process until the top surface of the conductive structure is exposed, so as to form a through hole 160 communicated with the bottom of the second groove 150, and further enlarge the opening size of the first groove 140; the conductive pillars 170 are formed, and the conductive pillars 170 fill the through holes 160 and at least a portion of the second recesses 150, and are electrically connected to the conductive structures 110.
In the embodiment of the disclosure, the mask layer 130 having the first opening 131 is formed, so that a process basis can be provided for a subsequent first etching process, the insulating structure 120 with the first thickness is etched along the first opening 131 through the first etching process, so that the first groove 140 and the second groove 150 which are communicated are formed in the insulating structure 120, the inner side surface of the formed second groove 150 is recessed towards the inner side surface far away from the first groove 140 compared with the inner side surface of the first groove 140, the formed first groove 140 and second groove 150 have a structure with a small upper opening and a large lower opening, and the problem that a gap is formed if a conductive column is directly etched and filled is caused.
Referring to fig. 1 and 2, the material type of the substrate 100 may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanium, gallium arsenide, indium gallium arsenide, or the like, and in other embodiments, the substrate 100 may also be a composite structure formed with other semiconductor structures, for example, the substrate 100 may be a composite structure with word lines, bit lines, capacitors, and/or transistors.
In some embodiments, the conductive structure 110 may be a single-layer film structure, may be a single-layer film formed of tungsten, and in other embodiments, the conductive structure 110 may be a multi-layer film stack structure, for example, the conductive structure 110 may include a first conductive layer, a first diffusion barrier layer, and a second conductive layer, where the first conductive layer may be a metal semiconductor compound material, for example, cobalt silicide, etc., the first diffusion barrier layer may be a titanium nitride layer, and the second conductive layer may be a metal material, for example, tungsten, etc.
In some embodiments, the insulating structure 120 may include an insulating layer 121 and an etching stop layer 122, where the etching stop layer 122 covers the surface of the conductive structure 110, and the insulating layer 121 is located on the surface of the etching stop layer 122, and the etching stop layer 122 is used for stopping the etching process in the subsequent process of forming the through hole, so as to slow down the etching step and avoid causing larger damage to the conductive structure 110 in the etching process.
In some embodiments, the material of the insulating layer 121 is different from the material of the etching stop layer 122, and the material of the insulating layer 121 may have a larger difference from the etching selection ratio of the etching stop layer 122, so that the etching rate is reduced when the surface of the etching stop layer 122 is etched in the process of etching the insulating layer 121, thereby avoiding the excessively fast etching rate from directly etching the conductive structure and avoiding damage and pollution to the conductive structure 110.
In some embodiments, the material of the insulating layer 121 may include: silicon nitride, silicon oxynitride, and the like.
In some embodiments, the material of etch stop layer 122 may include: silicon oxide, and the like.
In some embodiments, the front projection of the first opening 131 of the mask layer 130 on the surface of the substrate 100 may be located in the front projection of the conductive structure 110 on the surface of the substrate 100, or the front projection of the first opening 131 on the surface of the substrate 100 may coincide with the front projection of the conductive structure 110 on the surface of the substrate 100, so that the through hole formed in the subsequent etching process may not deviate from the top surface of the conductive structure 110, and the formed conductive pillar is prevented from being connected with the conductive structure in a contact manner, thereby improving the reliability of the formed semiconductor structure.
In some embodiments, the material of the mask layer 130 may be a carbon-containing material, and the carbon-containing material is softer to facilitate etching, so as to reduce the difficulty of forming the mask layer 130 with the first opening.
In some embodiments, a method of forming the first opening of the mask layer 130 may include: providing an initial mask layer 180, wherein the initial mask layer 180 is located on the top surface of the insulating structure 120, forming an anti-reflection layer 190, wherein the anti-reflection layer 190 is located on the top surface of the initial mask layer 180, forming a photoresist layer 200 with a first pattern, wherein the photoresist layer 200 is located on the top surface of the anti-reflection layer 190, etching the anti-reflection layer 190 and the initial mask layer 180 by using the photoresist layer 200 as a mask, and the remaining initial mask layer 180 is used as a mask layer 130, wherein after forming the mask layer 130, further comprises: the anti-reflection layer 190 and the photoresist layer 200 are removed.
It will be appreciated that as the feature size decreases, the photoresist pits caused by the highly reflective layer and the lateral photochemical reaction of light scattered by solid particles in the film become more and more unacceptable, so that the problems of reflection and standing waves generated when the photoresist layer 200 is illuminated can be reduced by forming an anti-reflective layer 190, and it should be noted that the highly reflective layer may be referred to as the mask layer 130 in the present embodiment.
In some embodiments, the major components of the material of the anti-reflective layer 190 may be a crosslinkable resin, a thermal acid generator, a surfactant, and a solvent.
In some examples, the photoresist layer 200 may be an initial photoresist layer formed first, the photoresist layer 200 is formed by illumination, and the orthographic projection of the first pattern of the photoresist layer 200 on the surface of the substrate 100 may be located within the orthographic projection of the conductive structure 110 on the surface of the substrate 100, or the orthographic projection of the first pattern of the photoresist layer 200 on the surface of the substrate 100 may coincide with the orthographic projection of the conductive structure 110 on the surface of the substrate 100, so that the through hole formed in the subsequent etching process may not deviate from the top surface of the conductive structure 110, and the formed conductive pillar is prevented from being connected with the conductive structure in a contact manner, thereby improving the reliability of the formed semiconductor structure.
In some embodiments, the material of the photoresist layer 200 may be a positive photoresist and a negative photoresist, where the positive photoresist is used to transfer the pattern onto the photoresist layer 200 under the irradiation of an exposure source such as ultraviolet rays, the irradiated portion is decomposed, the non-irradiated portion remains, the negative photoresist is used to decompose the non-irradiated portion under the irradiation of an exposure source such as ultraviolet rays, the resolution of the positive photoresist is better than that of the negative photoresist, and the negative photoresist has high heat resistance, so that the corresponding material can be selected according to actual needs.
Referring to fig. 2, the initial mask layer 180 is etched using the photoresist layer 200 as a mask to form the mask layer 130 having the first opening 131, and then the insulating structure 120 is etched at a first thickness along the first opening to form the first recess 140 and the second recess 150, and the inner side of the second recess 150 is formed to be recessed from the inner side of the first recess 140 toward the inner side away from the first recess 140 due to the etching process, in other words, the recess width of the second recess 150 is formed to be greater than the recess width of the first recess 140 in the cross-sectional view shown in fig. 2.
In some embodiments, the process parameters of the first etching process may include: the etching gas adopted comprises octafluorocyclobutane, hexafluorobutadiene, oxygen and argon, the gas flow of octafluorocyclobutane is 50-65 sccm, the gas flow of hexafluorobutadiene is 55-70 sccm, the gas flow of oxygen is 55-65 sccm, the gas flow of argon is 180-200 sccm, the radio frequency is 40 KHz-60 MHz, octafluorocyclobutane, hexafluorobutadiene, oxygen and argon are used as the etching gas of the first etching process, the etching gas is ionized by a radio frequency source with the radio frequency of 40 KHz-60 MHz to generate plasma, and then the insulating structure is etched by the plasma.
In some embodiments, the width of the first grooves 140 in the direction parallel to the substrate 100 may be 120nm to 130nm, and the width of the second grooves in the direction parallel to the substrate 100 may be 140nm to 150nm.
Referring to fig. 3, the mask layer 180 exposed from the first opening is etched using a second etching process to form the second opening 132.
In some embodiments, the width of the second opening 132 in a direction parallel to the substrate 100 may be 145nm to 155nm.
In some embodiments, the process parameters of the second etching process include: the etching gas comprises oxygen and argon, the gas flow of the oxygen is 10-15 sccm, the gas flow of the argon is 150-160 sccm, the etching power is 600W-1000W, the radio frequency is 30 MHz-60 MHz, the etching duration is 10-15 s, the oxygen and the argon are used as the etching gas of the second etching process, the etching power is 600W-1000W, the radio frequency is 30 MHz-60 MHz as an etching source to convert the oxygen and the argon into plasma, the insulating structure is etched by the plasma, the etching power is 600W-1000W, the radio frequency is 30 MHz-60 MHz which is higher than the conventionally used etching power and radio frequency, and both the high power and the high frequency radio frequency can improve the bombardment efficiency of the plasma on the surface of the insulating structure 120, so that the etching capability of the second etching process can be increased.
In some embodiments, the material of the mask layer 130 is a carbon-containing material, however, the carbon-containing material has a higher etching selectivity to oxygen, so that the etching capability of the etching gas to the mask layer 130 can be increased by adding argon as the etching gas, and the lateral etching capability of the second etching process to the mask layer 130 can be increased, where the lateral etching capability refers to the etching rate of the mask layer 130 from the sidewall of the mask layer 130 exposed from the second opening.
In some embodiments, as the process is continuously scaled, the aspect ratio of the formed via is correspondingly increased, so that the thickness of the mask layer 130 formed during the deposition of the mask layer 130 is generally thicker, and the etching selectivity of the mask layer 130 is also higher, and in the second etching process, not only the mask layer 130 is etched in the direction perpendicular to the substrate 100, but also the sidewall of the mask layer 130, that is, the first opening 131 is enlarged to the second opening 132, thereby providing a process basis for the subsequent third etching process.
Referring to fig. 4, a third etching process is performed to etch the insulating structure 120 along the second opening 132 to form the via 160, and also to enlarge the opening size of the first groove 140.
In some embodiments, the process parameters of the third etching process include: the adopted etching gas comprises any one of hexafluorobutadiene, octafluorocyclobutane or difluoromethane, the radio frequency is 40-60 MHz, any one of hexafluorobutadiene, octafluorocyclobutane or difluoromethane is used as the etching gas of the third etching process, the etching gas is converted into plasma through a radio frequency source with the radio frequency of 40-60 MHz, the insulating structure is etched through the plasma, and the etching capability of the third etching process can be improved through the radio frequency source with the radio frequency of 40-60 MHz.
In some embodiments, prior to forming the conductive pillars, further comprising: the exposed etching stop layer 122 is etched until the top surface of the conductive structure 110 is exposed, the etching stop layer 122 can stop etching after the insulating layer 121 is etched by the third etching process, and then the etching stop layer 122 can be etched by adopting an etching mode with a slower etching rate, that is to say, the third etching process is divided into two steps, the insulating layer 121 is etched first and the etching stop layer 122 is etched later, so that the situation that the etching process cannot be controlled due to too high etching rate of one step of etching can be avoided, and the conductive structure is prevented from being polluted and etched.
It will be appreciated that as the etching gas is consumed during etching, the opening size of the via 160 is smaller as it approaches the conductive structure 110, so that the via 160 structure with a larger upper opening and a smaller lower opening is shown in the schematic cross-sectional structure as shown.
In some embodiments, the width of the enlarged first groove 140 in a direction parallel to the substrate 100 may be 145nm to 155nm, for example 150nm, 152nm, 155nm, or the like.
In some embodiments, the width of the formed via 160 in a direction parallel to the substrate 100 may be 145nm to 155nm, for example, 148nm, 150nm, 152nm, or the like.
Referring to fig. 5, in some embodiments, the third etching process further comprises: the mask layer 130 is removed, and the insulating structure 120 exposed by the first groove 140 and a part of the insulating structure 120 exposed by the second groove 150 are etched and removed by chemical polishing, so as to form a horn-like opening shape, thereby improving the filling performance of the conductive column material in the subsequent process of forming the conductive column, reducing the gap in the conductive column, and improving the reliability of the formed semiconductor structure.
The horn mouth means that the diameter of the upper opening is larger than that of the lower opening, and the cross section of the upper opening is arc-shaped.
Referring to fig. 6, the conductive pillars 170 are formed, and the conductive pillars 170 are filled with the remaining second grooves 150 and the through holes 160 and contact the conductive structures 110, so that electrical signals can be transmitted to the conductive structures 110 or conductive signals within the conductive structures 110 can be extracted through the conductive pillars 170.
In other embodiments, the insulating structure 120 exposed by the first recess 140 and part of the insulating structure 120 exposed by the second recess 150 may not be removed by grinding, and in the prior art, the conducting post is directly formed by one etching process and filling, so that the void forming the conducting post 170 may be improved by the second etching process and the third etching process, and the top surface opening of the material filling the conducting post 170 may be increased by removing the insulating structure 120 exposed by the first recess 140 and part of the insulating structure 120 exposed by the second recess 150 by grinding, so that the void forming effect in the conducting post 170 is better.
Referring to fig. 7, after forming the conductive post 170, further includes: the conductive pillars 170 and the insulating structure 120 are planarized until the conductive pillars 170 located in the second recesses 150 (see fig. 5) are removed. The top surface of the conductive post 170 may be polished by planarization, i.e., the portion of the top surface of the conductive post 170 that is flared may be removed, thereby matching the subsequent process.
In the embodiment of the disclosure, the mask layer 130 having the first opening 131 is formed, so that a process basis can be provided for a subsequent first etching process, the insulating structure 120 with a first thickness is etched along the first opening 131 through the first etching process, so as to form the first groove 140 and the second groove 150 which are communicated in the insulating structure 120, the inner side surface of the formed second groove 150 is recessed towards the inner side surface far away from the first groove 140 compared with the inner side surface of the first groove 140, the formed first groove 140 and second groove 150 present a structure with a small upper opening and a large lower opening, so that the problem that a gap is formed if a conductive column is directly etched and filled is caused, the problem that the gap is formed by directly etching and filling the conductive column is solved, the application further comprises the steps of increasing the opening size of the first opening 131 through the first etching process after the first etching process, etching the second opening 132 until the top surface of the conductive structure is exposed through the third etching process, so as to form the through hole 160 which is communicated with the second groove 150, and simultaneously forming the through hole 160, the first groove 140 is also enlarged in size, so that the gap is enlarged, the subsequent conductive column is formed, and the conductive column is further formed, and the gap is further reduced, and the performance of the conductive column is further reduced, and the conductive column is formed, and the gap is further, and the conductive structure is further is formed, and the gap is further
An embodiment of the present disclosure further provides another method for manufacturing a semiconductor structure, which is substantially the same as the foregoing embodiment, and the main differences include: the method for manufacturing the semiconductor structure according to another embodiment of the present disclosure will be described below with reference to the accompanying drawings, where the same or corresponding parts of the foregoing embodiments may be referred to for corresponding description of the foregoing embodiments, and details will not be repeated.
Referring to fig. 8 to 16, fig. 8 to 16 are schematic structural views corresponding to the steps in the embodiment of the disclosure.
Specifically, referring to fig. 8, a substrate 300 is provided, on which a conductive structure 310 and an insulating structure 320 covering the conductive structure are formed, an initial mask layer 380 is formed on the insulating structure 320, an anti-reflection layer 390 is formed on the initial mask layer 380, and a photoresist layer 400 is formed on the surface of the anti-reflection layer 390.
The insulating structure 320 includes: the insulating layer 321 and the etching stop layer 322, the etching stop layer 322 covers the surface of the conductive structure 310, and the insulating layer 321 is located on the surface of the etching stop layer 322.
Referring to fig. 9, an initial mask layer 380 is etched using the photoresist layer 400 as a mask, a first etching process is performed using the mask layer 330 as a mask, and the insulating structure is etched to form a first recess 340 and a second recess 350.
Referring to fig. 10, a second etching process is performed to form a second opening 332.
Referring to fig. 11 to 14, a third etching process is performed to form a through hole 360 communicating with the bottom of the second groove 350.
Referring to fig. 11, in some embodiments, the third etching process may include a first sub-etching process that etches the insulating layer 321 until a surface of the etch stop layer is exposed.
Referring to fig. 12, a fourth etching process is used to etch the sidewall of the mask layer 330 exposed by the second opening 332, so that the second opening 332 is enlarged to be a third opening 333 and the top surface of the third portion of the insulating structure 320 is exposed, and a process basis can be provided for a subsequent fifth etching process by using the fourth etching process to form the third opening 333.
In some embodiments, the process parameters of the fourth etching process include: the adopted etching gas comprises oxygen and argon, the gas flow of the oxygen is 10-15 sccm, the gas flow of the argon is 150-160 sccm, the radio frequency power is 600-1000W, the radio frequency is 30 MHz-60 MHz, the oxygen and the argon are used as the etching gas of the fourth etching process, the etching power is 600-1000W, the radio frequency is 30 MHz-60 MHz as an etching source to convert the oxygen and the argon into plasma, the insulating structure is etched through the plasma, and the etching capability of the fourth etching process can be increased by adopting the etching source with the etching power of 600-1000W and the radio frequency of 30 MHz-60 MHz.
In some embodiments, the etching gas, the gas flow of the etching gas, the radio frequency power and the radio frequency of the fourth etching process may be the same as those of the second etching process, so that the process parameters of the second etching process do not need to be adjusted, and the etching pattern formed in the second etching process may also be used for continuously etching the mask layer 330, so that the change of the etching morphology caused by changing the etching parameters may be avoided.
In some embodiments, the process time length of the fourth etching process is longer than the process time length of the second etching process, it is understood that in the first sub-etching process, the width of the second groove 350 in the direction parallel to the substrate 300 is enlarged, by setting the process time length of the fourth etching process to be longer than the process time length of the second etching process, the difference between the opening width of the third opening 333 and the opening width of the second opening 332 formed is larger than the opening width of the second opening 332 and the opening width of the first opening 331, so that the influence caused by the enlarged width of the second groove 350 in the first sub-etching process can be eliminated in the subsequent process of performing the fifth etching process, and the problem of the void of the conductive pillar formed subsequently can be further improved.
In some embodiments, the process duration of the fourth etching process is 1.3-1.7 times that of the second etching process, for example, the process duration of the fourth etching process is 1.5 times or 1.6 times that of the second etching process, etc., it is understood that the process duration of the fourth etching process corresponds to the opening width of the third opening 333 formed, when the process duration of the fourth etching process is less than 1.3 times that of the second etching process, the effect of improving the effect of the width of the second groove 350 generated by the first sub-etching process is poor, and when the process duration of the fourth etching process is greater than 1.7 times that of the second etching process, too many insulating structures 320 etched later in the process of the fifth etching process may be caused, resulting in too small space between adjacent conductive pillars formed and affecting the insulating performance of the insulating structures 320.
In some embodiments, the opening width of the third opening 333 formed by the fourth etching process may be equal to the maximum width of the second recess 350, so that the second recess 350 increased during the etching of the third etching process may be exposed, thereby improving the void problem of the subsequent formation of the conductive pillar.
Referring to fig. 13, the insulating structure 320 is etched along the third opening 333 using a fifth etching process to enlarge the opening size of the first recess 340, and by enlarging the opening size of the first recess 340, the void in the conductive pillar may be improved in the subsequent formation of the conductive pillar.
In some embodiments, the process parameters of the fifth etching process include: the etching gas comprises at least one of hexafluorobutadiene, octafluorocyclobutane or difluoromethane, and the radio frequency is 40 KHz-60 MHz. Any one of hexafluorobutadiene, octafluorocyclobutane or difluoromethane is used as the etching gas for the fifth etching process, the etching gas is converted into plasma by a radio frequency source with the radio frequency of 40-60 MHz, the insulating structure is etched by the plasma, and the etching capability of the fifth etching process can be improved by the radio frequency source with the radio frequency of 40-60 MHz.
Referring to fig. 14, in some embodiments, the third etching process further includes a second sub-etching process by which the exposed etch stop layer 322 is etched until the top surface of the conductive structure 310 is exposed. Etching the etch stop layer 322 may provide a process basis for subsequent formation of conductive pillars 370 in contact with the conductive structure 310.
In some embodiments, the etching rate of the third etching process may be slowed down by dividing the third etching process into the first sub-etching process and the second sub-etching process, so that etching of the conductive structure during the third etching process may be avoided, and the conductive structure is prevented from being etched, which may prevent performance of the conductive structure from being reduced.
In some embodiments further comprising: the insulating structure 320 exposed by the first recess 340 and a portion of the insulating structure 320 exposed by the second recess 350 are removed.
Referring to fig. 15, conductive pillars 370 are formed, and the conductive pillars 370 fill the through holes 360.
Referring to fig. 16, the conductive pillars 370 are planarized to accommodate subsequent process steps.
The embodiment of the disclosure can improve the third etching process by adding the fourth etching process and the fifth etching process, so as to reduce the influence of the third etching process on the structure of the conductive column 370 formed subsequently, and further improve the void problem of the conductive column 370.
Another embodiment of the present disclosure further provides a semiconductor structure, which may be formed by using all or part of the steps of the foregoing embodiments, and the semiconductor structure provided in the embodiments of the present disclosure will be described with reference to the accompanying drawings, where the description of the same or corresponding parts of the foregoing embodiments may be referred to the corresponding description of the foregoing embodiments, and will not be repeated herein.
Referring to fig. 17, a semiconductor structure includes: a substrate 500, the substrate 500 having a conductive structure 510 thereon; the conductive column 570, the conductive column 570 is located on the top surface of the conductive structure 510 and is electrically connected with the conductive structure 510, the conductive column 570 includes a first conductive layer 571 and a second conductive layer 572, the first conductive layer 571 is located between the second conductive layer 572 and the conductive structure 510, and an outer side surface of the second conductive layer 572 protrudes towards an outer side surface far from the first conductive layer 571 compared to the outer side surface of the first conductive layer 571. By providing the outer side surface of the second conductive layer 572 to protrude away from the outer side surface of the first conductive layer 571 compared to the outer side surface of the first conductive layer 571, the top surface area of the second conductive layer 572 can be increased, so that the contact area between other structures and the second conductive layer 572 can be increased, and the contact resistance between the second conductive layer 572 and other structures can be reduced.
In some embodiments, the semiconductor structure further comprises: the insulating structure 520, the insulating structure 520 covers the sidewall of the conductive column 570. Adjacent conductive posts 570 may be isolated by providing insulating structures 520 to avoid electrical connection between adjacent conductive posts 570.
In some embodiments, the insulating structure 520 may include an insulating layer 521 and an etch stop layer 522, and the process of fabricating the semiconductor structure may be facilitated by providing the etch stop layer 522, and the insulating layer 521 may be used to isolate adjacent conductive pillars 570.
In some embodiments, the width of the second conductive layer 572 is 180-200 nm, such as 183nm, 190nm, 195nm, or the like. By setting the width of the second conductive layer 572 to be 180-200 nm, the width of the second conductive layer 572 can be increased on the premise of ensuring a certain distance between the adjacent second conductive layers 572, and thus the contact resistance of the top surface of the second conductive layer 572 can be reduced, and it can be understood that when the width of the second conductive layer 572 is smaller than 180nm, the effect of improving the contact resistance and increasing the contact area of the second conductive layer 572 is poor, and when the width of the second conductive layer 572 is larger than 200nm, the space between the second conductive layers 572 may be smaller, affecting the reliability of the semiconductor structure.
In some embodiments, the first conductive layer 571 has a height of 1600nm to 2400nm and a width of 150nm to 160nm, for example, the height may be 1700nm, 2000nm, or 200nm, etc., and the width may be 155nm, 157nm, or 159nm, etc., it is understood that when the height of the first conductive layer 571 is less than 1600nm, the resistance of the first conductive layer 571 is higher, when the height of the first conductive layer 571 is more than 2400nm, the decrease of the integration of the semiconductor structure is unfavorable, and the process step of the semiconductor structure is more difficult, when the width of the first conductive layer 571 is less than 150nm, the resistance of the first conductive layer 571 is larger, and when the width of the first conductive layer is more than 160nm, the process step of the semiconductor structure is more difficult.
Embodiments of the present disclosure provide a semiconductor structure including: a substrate 500, the substrate 500 having a conductive structure 510 thereon; the conductive column 570, the conductive column 570 is located on the top surface of the conductive structure 510 and is electrically connected with the conductive structure 510, the conductive column 570 includes a first conductive layer 571 and a second conductive layer 572, the first conductive layer 571 is located between the second conductive layer 572 and the conductive structure 510, and an outer side surface of the second conductive layer 572 protrudes towards an outer side surface far from the first conductive layer 571 compared to the outer side surface of the first conductive layer 571. By providing the outer side surface of the second conductive layer 572 to protrude away from the outer side surface of the first conductive layer 571 compared to the outer side surface of the first conductive layer 571, the top surface area of the second conductive layer 572 can be increased, so that the contact area between other structures and the second conductive layer 572 can be increased, and the contact resistance between the second conductive layer 572 and other structures can be reduced.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the disclosure, and the scope of the embodiments of the disclosure should be assessed accordingly to that of the appended claims.
Claims (15)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a conductive structure and an insulating structure covering the conductive structure, and the insulating structure covers the top surface of the conductive structure;
Forming a mask layer, wherein the mask layer is positioned on the insulating structure and is provided with a first opening exposing the top surface of a first part of the insulating structure;
Etching the insulating structure with a first thickness along the first opening by adopting a first etching process to form a first groove and a second groove which are communicated in the insulating structure, wherein the first groove is positioned between the first opening and the second groove, and the inner side surface of the second groove is recessed towards the inner side surface far away from the first groove compared with the inner side surface of the first groove;
Etching the side wall of the mask layer exposed by the first opening by adopting a second etching process so as to expand the first opening into a second opening and expose the top surface of a second part of the insulating structure;
Etching the insulating structure along the second opening by adopting a third etching process until the top surface of the conductive structure is exposed so as to form a through hole communicated with the bottom of the second groove;
And forming a conductive column which fills the through hole and is electrically connected with the conductive structure.
2. The method of fabricating a semiconductor structure of claim 1, further comprising, prior to forming the conductive pillars:
Etching the side wall of the mask layer exposed by the second opening by adopting a fourth etching process, so that the second opening is enlarged to be a third opening and the top surface of a third part of the insulating structure is exposed;
and etching the insulating structure along the third opening by adopting a fifth etching process so as to enlarge the opening size of the first groove.
3. The method of claim 2, wherein the process time of the fourth etching process is longer than the process time of the second etching process.
4. A method of fabricating a semiconductor structure according to claim 2 or 3, wherein the process duration of the fourth etching process is 1.3 to 1.7 times the process duration of the second etching process.
5. The method of claim 2, wherein the process parameters of the fifth etching process include: the etching gas comprises at least one of hexafluorobutadiene, octafluorocyclobutane or difluoromethane, and the radio frequency is 40 KHz-60 MHz.
6. The method of claim 2, wherein the fourth etching process includes:
The etching gas comprises oxygen and argon, the gas flow of the oxygen is 10-15 sccm, the gas flow of the argon is 150-160 sccm, the radio frequency power is 600-1000W, and the radio frequency is 30-60 MHz.
7. The method of manufacturing a semiconductor structure according to claim 1 or 2, wherein the insulating structure comprises: the insulating layer and the etching stop layer, the etching stop layer covers the surface of the conductive structure, the insulating layer is located the surface of the etching stop layer, and the insulating layer further comprises: and etching the exposed etching stop layer until the top surface of the conductive structure is exposed.
8. The method of claim 1, wherein the process parameters of the first etching process comprise:
The etching gas comprises octafluorocyclobutane, hexafluorobutadiene, oxygen and argon, the gas flow rate of octafluorocyclobutane is 50-65 sccm, the gas flow rate of hexafluorobutadiene is 55-70 sccm, the gas flow rate of oxygen is 55-65 sccm, the gas flow rate of argon is 180-200 sccm, and the radio frequency is 40 KHz-60 MHz.
9. The method of claim 1, wherein the process parameters of the second etching process include:
The etching gas comprises oxygen and argon, the gas flow of the oxygen is 10-15 sccm, the gas flow of the argon is 150-160 sccm, the etching power is 600-1000W, the radio frequency is 30-60 MHz, and the etching duration is 10-15 s.
10. The method of claim 1, wherein the process parameters of the third etching process include: the etching gas comprises any one of hexafluorobutadiene, octafluorocyclobutane or difluoromethane, and the radio frequency is 40-60 MHz.
11. The method of fabricating a semiconductor structure of claim 1, wherein forming the conductive pillars comprises: and forming an initial conductive column to fill the through hole and at least part of the second groove, and carrying out planarization treatment on the initial conductive column and the insulating structure until the second groove and the initial conductive column in the second groove are removed so as to keep the initial conductive column in the through hole as the conductive column.
12. A semiconductor structure, comprising:
A substrate having a conductive structure thereon;
The conductive column is located the top surface of conductive structure and with conductive structure electricity is connected, the conductive column includes first conducting layer and second conducting layer, first conducting layer is located the second conducting layer with between the conductive structure, just the lateral surface of second conducting layer is compared the lateral surface orientation of first conducting layer is kept away from the lateral surface protrusion of first conducting layer.
13. The semiconductor structure of claim 12, further comprising: and the insulating structure covers the side wall of the conductive column.
14. The semiconductor structure of claim 12, wherein the second conductive layer has a width of 180-200 nm.
15. The semiconductor structure of claim 12, wherein the first conductive layer has a height of 1600nm to 2400nm and a width of 150nm to 160nm.
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| CN202211255723.7A CN117936455A (en) | 2022-10-13 | 2022-10-13 | Manufacturing method of semiconductor structure and structure thereof |
| PCT/CN2022/133245 WO2024077714A1 (en) | 2022-10-13 | 2022-11-21 | Manufacturing method for semiconductor structure, and structure thereof |
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| CN202211255723.7A CN117936455A (en) | 2022-10-13 | 2022-10-13 | Manufacturing method of semiconductor structure and structure thereof |
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| US6933556B2 (en) * | 2001-06-22 | 2005-08-23 | Fujio Masuoka | Semiconductor memory with gate at least partially located in recess defined in vertically oriented semiconductor layer |
| CN111599696A (en) * | 2020-05-28 | 2020-08-28 | 矽磐微电子(重庆)有限公司 | Semiconductor module packaging method and semiconductor module |
| CN114512468A (en) * | 2020-11-16 | 2022-05-17 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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