CN117931739A - PCB design data conversion method, device, equipment and medium - Google Patents
PCB design data conversion method, device, equipment and medium Download PDFInfo
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- 229910052802 copper Inorganic materials 0.000 claims description 13
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F30/30—Circuit design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
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Abstract
The invention provides a PCB design data conversion method, a device, equipment and a medium, which relate to the field of circuits and acquire PCB design data in a text format generated by an EDA tool; and in a new environment, sequentially reading and analyzing a laminated design data part, a device data part, a bonding pad data part, a network data part and a layer data part in the PCB design data in the text format, and converting the read and analyzed data part into data in the new environment. The invention has the beneficial effects that: the method can read and analyze the text-format PCB design data generated by the EDA tool, and convert the text-format PCB design data into data in a new environment, thereby effectively solving the defect that PCB files led out by other EDA tools in the prior art cannot be directly read, and is unfavorable for secondary development.
Description
Technical Field
The present invention relates to the field of circuits, and in particular, to a method, an apparatus, a device, and a medium for converting PCB design data.
Background
The PCB (Printed Circuit Board ) is an important electronic component, which is a support for electronic components and is also a carrier for electrical connection of electronic components. Almost every electronic device includes electronic components such as an integrated circuit, and a printed board is used for electrically interconnecting the components. The electronic device not only simplifies the assembly and welding work of the electronic product, but also reduces the whole volume, reduces the product cost and improves the quality and the reliability of the electronic device.
At present, a plurality of PCB design development software are available in the market, after a user finishes the PCB design by one software, the PCB design data format of each software is incompatible, so that the PCB design software can only be subjected to secondary development or modification later, and the originally designed PCB files cannot be read by other software due to incompatibility, so that secondary development cannot be performed.
Disclosure of Invention
The invention aims to read out the PCB text files of other EDA tools and convert the PCB text files into data in a new environment so as to overcome the problem that the designs of other EDA tools are not compatible in the prior art.
In a first aspect, a method of converting PCB design data, obtains PCB design data in text format generated by an EDA tool; sequentially reading and analyzing a laminated design data part, a device data part, a bonding pad data part, a network data part and a layer data part in the PCB design data in the text format in a new environment; and converting the read and parsed data part into data in a new environment.
Preferably, the data converted into the new environment is formed into the PCB design data in a graphic format by a graphic display tool.
Preferably, sequentially reading and parsing the stack design data part, the device data part, the pad data part, the network data part and the layer data part in the text-format PCB design data, including: extracting the data type in the PCB design data in the text format through the keywords; and reading a laminated design data part, a device data part, a bonding pad data part, a network data part and a layer data part in the PCB design data in the text format according to the data type.
Preferably, in the new environment, sequentially reading and analyzing the stack design data part, the device data part, the pad data part, the network data part and the layer data part in the text-format PCB design data, including: and each data part of the text format is provided with a starting keyword and an ending keyword, and the content of each data part of the text format is respectively determined by reading the starting keyword and the ending keyword of each data part of the text format.
Preferably, the laminate design data part includes information on the number of plies, name, size, thickness, type of ply, conductivity and dielectric constant of each ply; the device data part comprises element names, position information of devices on a circuit board, size of the devices, reference information, pin position information and number information; the pad data part comprises pad position information, shape and position information of a welding hole, and corresponds to the pad or the position information of the welding hole through a device pin; the network data part comprises position information and length of a connecting line, position information of a via hole and shape and position information of copper cladding; the layer data section includes a layer setting and a sub-setting name.
Preferably, the PCB design data in a graphic format formed by converting the data converted into the new environment through the graphic display tool includes: constructing a corresponding number of plate layers according to the number information of the plate layers, and constructing a corresponding plate layer according to the thickness information, the position information and the size of the plate layers, wherein the corresponding plate layer comprises type information, conductivity information and dielectric constant information of the plate layer; correspondingly constructing the devices on the corresponding plate layers according to the size and position information of the devices, and placing pins with different numbers on the corresponding devices according to the pin position information; corresponding bonding pads are correspondingly arranged on the circuit boards of the corresponding plate layers according to the bonding pad position information and the shape information, and corresponding bonding holes are constructed on the circuit boards of the corresponding plate layers according to the position information of the bonding holes; setting connection lines on the circuit boards of the corresponding plate layers according to the position information and the length information of the connection lines, connecting corresponding pins, bonding pads and welding holes, constructing through holes on the circuit boards of the corresponding plate layers according to the position information of the through holes, and constructing copper coating on the corresponding plate layers according to the copper coating information through the connection lines; and displaying the name information according to the setting and the sub-setting of each layer and each layer in a one-to-one correspondence manner.
Preferably, converting the read and parsed data portion into data in a new environment includes: whenever any one data part in the PCB design data in the text format is read and parsed, the read and parsed data part is converted into data in a new environment.
In a second aspect, the present application also proposes a PCB design data conversion device, comprising:
An acquisition unit for acquiring the text-formatted PCB design data generated by the EDA tool;
The analysis unit is used for sequentially reading and analyzing the laminated design data part, the device data part, the bonding pad data part, the network data part and the layer data part in the PCB design data in the text format under a new environment;
And the conversion unit is used for converting the read and parsed data part into data in a new environment.
Preferably, the parsing unit is specifically configured to, when sequentially reading and parsing the stack design data portion, the device data portion, the pad data portion, the network data portion, and the layer data portion in the text format PCB design data: extracting the data type in the PCB design data in the text format through the keywords; and reading a laminated design data part, a device data part, a bonding pad data part, a network data part and a layer data part in the PCB design data in the text format according to the data type.
In a third aspect, an embodiment of the present invention provides an electronic device, including a processor and a memory. Wherein the memory is for storing one or more computer programs; the one or more computer programs, when executed by the processor, enable the electronic device to implement the method of any one of the possible designs of the first aspect described above.
In a fourth aspect, the present invention provides a computer-readable storage medium having stored therein a computer program which, when executed by a processor, implements a method as in any of the above embodiments.
In a fifth aspect, embodiments of the present invention further provide a computer program product which, when run on an electronic device, causes the electronic device to perform the method of any one of the possible designs of the above aspect.
The invention has the beneficial effects that: the method can read and analyze the PCB design data in the text format generated by the EDA tool, read the laminated design data part, the device data part, the bonding pad data part, the network data part and the layer data part through keywords, convert the data into data in a new environment, and form the data in the new environment into the PCB design data in the graphic format through the graphic display tool, thereby effectively solving the defects that PCB files led out by other EDA tools in the prior art cannot be directly read, and are unfavorable for secondary development.
Drawings
FIG. 1 is a block diagram of a system architecture of the present invention;
FIG. 2 is a schematic diagram of the content of a text format PCB design data portion according to an embodiment of the present invention;
FIG. 3 is a schematic view of an apparatus according to an embodiment of the present invention;
Fig. 4 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
The EDA tool, namely an electronic design automation tool, refers to an automatic design of electronic products by taking a computer as a working platform and integrating the latest achievements of applying electronic technology, computer technology, information processing and intelligent technology. The design method mainly utilizes Computer Aided Design (CAD) software to complete the flow of functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule inspection, and the like) and the like of a very large scale integrated circuit (VLSI) chip. The EDA tool is capable of performing circuit schematics, circuit layouts, circuit characteristic analysis, circuit design (including analog and digital circuits), and simulations. With EDA tools, electronic designers can start designing electronic systems from concepts, algorithms, protocols, etc., and can automatically process the whole process from circuit design, performance analysis to the design of IC layout or PCB layout of electronic products on a computer. The following are some common EDA software: altium Designer, cadence Allegro/OrCAD, mentor Graphics, kiCad, etc.
The new environment refers to another tool different from the traditional EDA tool, can convert a text format file derived by the traditional EDA tool into data of another tool data structure, and is used for sequentially reading and analyzing a laminated design data part, a device data part, a bonding pad data part, a network data part and a layer data part in the PCB design data of the text format; and converting the read and parsed data part into data in a new environment.
In some embodiments, the graphics display tool is OpenGL, which in the present disclosure refers to OpenGL (collectively Open Graphics Library) that is a cross-programming language, cross-platform Application Programming Interface (API) for rendering 2D and 3D vector graphics. It consists of nearly 350 different function calls that can be used to draw three-dimensional scenes from simple graphics to complex. The interface is a professional graphic program interface and is also a powerful and convenient-to-call bottom graphic library. Efficient implementations of OpenGL (using graphics acceleration hardware) exist in Windows, part of the UNIX platform, and Mac OS. These implementations are typically provided by a display device vendor and are highly dependent on the hardware provided by the vendor. Furthermore, the open source library measa is a purely software-based graphics API whose code is compatible with OpenGL, which allows programmers to interact directly with a Graphics Processing Unit (GPU) to achieve efficient image rendering and real-time graphics computation. OpenGL is widely used in game development, CAD, visual simulation, scientific computing, and many other applications where high quality graphics functionality is required. The OpenGL standard is maintained by the Khronos Group and is continually updated to support modern graphics technologies, including but not limited to: basic rendering function: points, lines, polygons, texture maps, blending, depth testing, etc. Advanced properties: shader programming (GLSL), vertex Buffer Objects (VBOs), frame Buffer Objects (FBOs), geometry shaders, compute shaders, texture arrays, cube maps, and the like. Scalability: the vendor may provide extended functionality for specific hardware support such as antialiasing, HDR rendering, multisampling, delayed rendering, etc.
The PCB referred to in the present application is an abbreviation of Printed Circuit Board (printed circuit board), which is one of essential basic components in electronic devices. The primary function of the printed circuit board is to provide electrical interconnections between electronic components in a limited space and to support and secure the components in a predetermined position. The circuit patterns are formed on the insulating substrate by etching conductive materials such as copper foil, and the PCB realizes the functions of signal transmission, power distribution, grounding and the like. The PCB can be divided into a plurality of types such as a single-layer board, a double-layer board, a multi-layer board and the like according to the number of layers, and more complicated wiring can be realized in a smaller volume as the number of layers is larger. Advanced PCB designs will employ multilayer structures with multiple interconnect layers inside, meeting the requirements of modern electronics for miniaturization, high integration, and performance stability.
Referring to fig. 1, a method for converting PCB design data is described in this embodiment, including:
step S101, obtaining PCB design data in a text format generated by an EDA tool;
Step S102, under a new environment, sequentially reading and analyzing a laminated design data part, a device data part, a bonding pad data part, a network data part and a layer data part in the PCB design data in the text format;
step S103, converting the read and parsed data part into data under a new environment.
As a further preferred embodiment, the data converted to the new environment is formed into PCB design data in a graphical format by a graphical display tool.
Specifically, the EDA tool is used for exporting a file in a text format of a PCB, such as a file in a TXT or PcbDoc format, opening and reading the file in the text format, sequentially reading the file in the text format, further reading the contents of the laminated design data part, the device data part, the pad data part, the network data part and the layer data part, and when acquiring the contents of the laminated design data part, the device data part, the pad data part, the network data part and the layer data part, converting the acquired data part into data of a data structure in a new environment, and converting the file in the text format exported by the EDA tool into the data structure passing through the new environment because the data structures of other EDA tools and the new environment (different from the traditional EDA tool) are different, wherein the operations can be realized through a program stored in a computer storage medium, so that the converted data can be exported or edited continuously through the new environment.
As a further preferred embodiment, the data converted to the new environment is formed into PCB design data in a graphical format by a graphical display tool for presentation to a user.
As a further preferred embodiment, sequentially reading and parsing the stack design data part, the device data part, the pad data part, the network data part and the layer data part in the text-formatted PCB design data includes: extracting the data type in the PCB design data in the text format through the keywords; and reading a laminated design data part, a device data part, a bonding pad data part, a network data part and a layer data part in the PCB design data in the text format according to the data type.
Specifically, different data portions are determined according to the read contents, and when the type of the data portion is determined, corresponding data is read.
Illustratively, referring to FIG. 2, when the keyword "stackup" keyword in the text file is extracted, the category is determined to be the overlay design data portion, and the corresponding content is the specific content contained in the corresponding overlay design data portion.
As a further preferred embodiment, the data information is read by means of a table.
Specifically, when the stack design data portion, the device data portion, the pad data portion, the network data portion, and the layer data portion are read, the data information in the PCB text file is arranged in a table format, and thus the data information is read in a table format.
Illustratively, one-end information recorded in the PCB design data in text format in connection with FIG. 2 is recorded by "+|! "different contents are separated, the first row represents titles of different data information, and the remaining row contents represent specific contents corresponding to the first row title, and are one-to-one corresponding as in a table, i.e., the first title" number "corresponds to the contents" 0"," 1"," 2"," 3"," 4"," 5"," 6"," 7"," 8 "of the first column.
As a further preferred embodiment, in a new environment, sequentially reading and parsing the stack design data part, the device data part, the pad data part, the network data part and the layer data part in the text format PCB design data, including: and each data part of the text format is provided with a starting keyword and an ending keyword, and the content of each data part of the text format is respectively determined by reading the starting keyword and the ending keyword of each data part of the text format.
Specifically, when the reading of the stack design data portion, the device data portion, the pad data portion, the network data portion, and the layer data portion is performed, it starts with its actual key and ends with an end key.
Illustratively, in connection with FIG. 2, beginning with [ stackup ] when a certain portion of the text file is read represents beginning to read the overlay design data portion, and ending when [ End stackup ] is read represents reading the overlay design data portion.
As a further preferable embodiment, the laminate design data section includes information on the number of plies, name, size, thickness, type of ply, conductivity, dielectric constant information, and the like of each ply; the device data part comprises element names, position information of devices on a circuit board, size of the devices, reference information, pin position information, number information and the like; the pad data part comprises pad position information, shape, position information of a welding hole and the like, and corresponds to the position information of the pad or the welding hole through a device pin; the network data part comprises position information and length of a connecting line, position information of a via hole, shape and position information of copper cladding and the like; the layer data section includes a layer setting and a sub-setting name.
As a further preferred embodiment, the position information is coordinate information.
Specifically, the position where the device, the bonding pad, the bonding hole, etc. are placed and the position of the boundary are determined by the position information of the coordinates.
As a further preferred embodiment, the shape of the copper cladding and the shape of the component are determined by the positional information of the corners of the copper cladding or the component.
As a further preferred embodiment, the PCB design data in a graphical format from the data converted to the new environment by the graphical display tool comprises: constructing a corresponding number of plate layers according to the number information of the plate layers, and constructing a corresponding plate layer according to the thickness information, the position information and the size of the plate layers, wherein the corresponding plate layer comprises type information, conductivity information and dielectric constant information of the plate layer; correspondingly constructing the devices on the corresponding plate layers according to the size and position information of the devices, and placing pins with different numbers on the corresponding devices according to the pin position information; corresponding bonding pads are correspondingly arranged on the circuit boards of the corresponding plate layers according to the bonding pad position information and the shape information, and corresponding bonding holes are constructed on the circuit boards of the corresponding plate layers according to the position information of the bonding holes; setting connection lines on the circuit boards of the corresponding plate layers according to the position information and the length information of the connection lines, connecting corresponding pins, bonding pads and welding holes, constructing through holes on the circuit boards of the corresponding plate layers according to the position information of the through holes, and constructing copper coating on the corresponding plate layers according to the copper coating information through the connection lines; and displaying the name information according to the setting and the sub-setting of each layer and each layer in a one-to-one correspondence manner.
Specifically, when the laminated design data portion is acquired, the corresponding board layer is reconstructed according to the sizes and positions of different board layers, when the device data portion is acquired, the corresponding device is placed on the board layer according to the sizes and position information of different devices, the number of pins and the position information, when the pad data portion is acquired, the corresponding device is placed on the board layer according to the positions of the pads and the welding holes, when the device data portion is acquired, the lead is drawn on the board layer according to the positions and the lengths of the lead, the via hole is arranged on the board layer according to the position information of the via hole, the copper is arranged on the board layer according to the shape and the position information of the copper, and when the layer data portion is acquired, the corresponding board layer is displayed according to the arrangement and the sub-arrangement name of the layer.
As a further preferred embodiment, converting the read and parsed data portion into data in a new environment comprises: whenever any one data part in the PCB design data in the text format is read and parsed, the read and parsed data part is converted into data in a new environment.
Specifically, the read and parsed data portion is converted into data in a new environment, and the complete reading of the PCB design data in text format is not required, and the conversion into data in the new environment is started whenever the content of one data portion is read, for example, the conversion into data in the stack design data portion in the new environment is started when the stack design data portion is acquired.
In other embodiments of the present invention, referring to fig. 3, a PCB design data conversion device is further provided, including:
an acquisition unit 301 for acquiring the text-formatted PCB design data generated by the EDA tool;
The parsing unit 302 is configured to sequentially read and parse the stack design data portion, the device data portion, the pad data portion, the network data portion, and the layer data portion in the text-format PCB design data in a new environment;
the converting unit 303 is configured to convert the read and parsed data portion into data under a new environment.
As a further preferred embodiment, the parsing unit is specifically configured to, when sequentially reading and parsing the stack design data portion, the device data portion, the pad data portion, the network data portion, and the layer data portion in the text format PCB design data: extracting the data type in the PCB design data in the text format through the keywords; and reading a laminated design data part, a device data part, a bonding pad data part, a network data part and a layer data part in the PCB design data in the text format according to the data type.
All relevant contents of each step related to the above method embodiment may be cited to the functional descriptions of the corresponding functional modules, which are not described herein.
In other embodiments of the present invention, an electronic device 400 is disclosed, as shown in fig. 4, the electronic device 400 may include: one or more processors 401; a memory 402; a display 403; one or more applications (not shown); and one or more computer programs 404, which may be connected via one or more communication buses 405. Wherein the one or more computer programs 404 are stored in the memory 402 and configured to be executed by the one or more processors 401, the one or more computer programs 404 comprise instructions that may be used to perform the various steps as in fig. 1-4 and the corresponding embodiments.
From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be implemented by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to implement all or part of the functions described above. The specific working processes of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which are not described herein.
The functional units in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the embodiments of the present invention may be essentially or a part contributing to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in the embodiments of the present invention. And the aforementioned storage medium includes: flash memory, removable hard disk, read-only memory, random access memory, magnetic or optical disk, and the like.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. A PCB design data conversion method, comprising:
Acquiring PCB design data in a text format generated by an EDA tool;
sequentially reading and analyzing a laminated design data part, a device data part, a bonding pad data part, a network data part and a layer data part in the PCB design data in the text format in a new environment;
and converting the read and parsed data part into data in a new environment.
2. The method of claim 1, wherein the data converted to the new environment is formed into PCB design data in a graphical format by a graphical display tool.
3. The method of claim 1, wherein sequentially reading and parsing the stack design data portion, the device data portion, the pad data portion, the network data portion, and the layer data portion of the text-formatted PCB design data comprises:
Extracting the data type in the PCB design data in the text format through the keywords;
And reading a laminated design data part, a device data part, a bonding pad data part, a network data part and a layer data part in the PCB design data in the text format according to the data type.
4. The method of claim 1, wherein sequentially reading and parsing the stack design data portion, the device data portion, the pad data portion, the network data portion, and the layer data portion of the text-formatted PCB design data in a new environment comprises:
And each data part of the text format is provided with a starting keyword and an ending keyword, and the content of each data part of the text format is respectively determined by reading the starting keyword and the ending keyword of each data part of the text format.
5. The method of claim 2, wherein the step of determining the position of the substrate comprises,
The laminated design data part includes information of the number of the plate layers, name, size, thickness, type of the layer, conductivity and dielectric constant of each plate layer;
The device data part comprises element names, position information of devices on a circuit board, size of the devices, reference information, pin position information and number information;
The pad data part comprises pad position information, shape and position information of a welding hole, and corresponds to the pad or the position information of the welding hole through a device pin;
The network data part comprises position information and length of a connecting line, position information of a via hole and shape and position information of copper cladding;
the layer data section includes a layer setting and a sub-setting name.
6. The method of claim 5, wherein forming the data converted into the new environment into the PCB design data in a graphical format by the graphical display tool comprises:
Constructing a corresponding number of plate layers according to the number information of the plate layers, and constructing a corresponding plate layer according to the thickness information, the position information and the size of the plate layers, wherein the corresponding plate layer comprises type information, conductivity information and dielectric constant information of the plate layer;
Correspondingly constructing the devices on the corresponding plate layers according to the size and position information of the devices, and placing pins with different numbers on the corresponding devices according to the pin position information;
Corresponding bonding pads are correspondingly arranged on the circuit boards of the corresponding plate layers according to the bonding pad position information and the shape information, and corresponding bonding holes are constructed on the circuit boards of the corresponding plate layers according to the position information of the bonding holes;
Setting connection lines on the circuit boards of the corresponding plate layers according to the position information and the length information of the connection lines, connecting corresponding pins, bonding pads and welding holes, constructing through holes on the circuit boards of the corresponding plate layers according to the position information of the through holes, and constructing copper coating on the corresponding plate layers according to the copper coating information through the connection lines;
and displaying the name information according to the setting and the sub-setting of each layer and each layer in a one-to-one correspondence manner.
7. The method of claim 2, wherein converting the read and parsed data portion into data in a new environment, comprises:
Whenever any one data part in the PCB design data in the text format is read and parsed, the read and parsed data part is converted into data in a new environment.
8. A PCB design data conversion apparatus, comprising:
An acquisition unit for acquiring the text-formatted PCB design data generated by the EDA tool;
The analysis unit is used for sequentially reading and analyzing the laminated design data part, the device data part, the bonding pad data part, the network data part and the layer data part in the PCB design data in the text format under a new environment;
And the conversion unit is used for converting the read and parsed data part into data in a new environment.
9. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program executable on the processor, which when executed by the processor causes the processor to implement the method of any of claims 1 to 7.
10. A computer readable storage medium having a computer program stored therein, which, when executed by a processor, implements the method of any of claims 1 to 7.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102231146A (en) * | 2011-07-11 | 2011-11-02 | 西安电子科技大学 | Automatic extraction and normalization storage method of manufacturing data of heterogeneous electronic design automation (EDA) design |
| US20170048985A1 (en) * | 2013-11-29 | 2017-02-16 | Michael Knox | Apparatus and method for the manufacturing of printed wiring boards and component attachment |
| CN106649852A (en) * | 2016-12-30 | 2017-05-10 | 广州兴森快捷电路科技有限公司 | Method and system for converting PCB file into Gerber file |
| CN114357930A (en) * | 2022-01-06 | 2022-04-15 | 上海侠为电子有限公司 | Automatic component layout method based on hierarchical structure |
| CN115345107A (en) * | 2022-08-22 | 2022-11-15 | 西安电子科技大学 | Method for converting ODB + + file into three-dimensional geometric model |
| CN116187261A (en) * | 2023-03-13 | 2023-05-30 | 深圳市频芯电路有限公司 | Calculation method for PCB lamination combination mode and material cost |
| CN116187252A (en) * | 2023-03-30 | 2023-05-30 | 深圳前海硬之城信息技术有限公司 | Acceleration generation method, device, equipment and storage medium for PCB drawing |
| CN116663479A (en) * | 2023-06-14 | 2023-08-29 | 上海弘快科技有限公司 | PCB-Package collaborative design method |
| CN117574845A (en) * | 2023-11-24 | 2024-02-20 | 电子科技大学长三角研究院(湖州) | Q3D-based gallium nitride power converter electromagnetic compatibility optimization method and system |
-
2024
- 2024-03-22 CN CN202410331134.5A patent/CN117931739A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102231146A (en) * | 2011-07-11 | 2011-11-02 | 西安电子科技大学 | Automatic extraction and normalization storage method of manufacturing data of heterogeneous electronic design automation (EDA) design |
| US20170048985A1 (en) * | 2013-11-29 | 2017-02-16 | Michael Knox | Apparatus and method for the manufacturing of printed wiring boards and component attachment |
| CN106649852A (en) * | 2016-12-30 | 2017-05-10 | 广州兴森快捷电路科技有限公司 | Method and system for converting PCB file into Gerber file |
| CN114357930A (en) * | 2022-01-06 | 2022-04-15 | 上海侠为电子有限公司 | Automatic component layout method based on hierarchical structure |
| CN115345107A (en) * | 2022-08-22 | 2022-11-15 | 西安电子科技大学 | Method for converting ODB + + file into three-dimensional geometric model |
| CN116187261A (en) * | 2023-03-13 | 2023-05-30 | 深圳市频芯电路有限公司 | Calculation method for PCB lamination combination mode and material cost |
| CN116187252A (en) * | 2023-03-30 | 2023-05-30 | 深圳前海硬之城信息技术有限公司 | Acceleration generation method, device, equipment and storage medium for PCB drawing |
| CN116663479A (en) * | 2023-06-14 | 2023-08-29 | 上海弘快科技有限公司 | PCB-Package collaborative design method |
| CN117574845A (en) * | 2023-11-24 | 2024-02-20 | 电子科技大学长三角研究院(湖州) | Q3D-based gallium nitride power converter electromagnetic compatibility optimization method and system |
Non-Patent Citations (3)
| Title |
|---|
| JF_IZR6MDQV: "获取通过EDA工具所生成的文本格式的PCB设计数据", pages 1 - 31, Retrieved from the Internet <URL:m.elecfans.com/article/2103121.html> * |
| 凡亿范老师: "嘉立创EDA与AD、PADS、OrCAD之间的PCB互转", 电子设计联盟, 9 June 2023 (2023-06-09), pages 1 - 17 * |
| 武洪恩等: "PCB ASCll pcbdoc文件格式解析方法研究", 自动化技术与应用, 31 December 2015 (2015-12-31), pages 102 - 105 * |
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