CN115345107A - Method for converting ODB + + file into three-dimensional geometric model - Google Patents
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Abstract
The invention discloses a method for converting an ODB + + file into a three-dimensional geometric model, which comprises the following specific steps: respectively creating display interfaces of a PCB three-dimensional layout model and a PCB three-dimensional geometric model, reading and processing information related to PCB modeling according to the standard of the ODB + + file, constructing the PCB three-dimensional layout model, and realizing the creation of the PCB three-dimensional geometric model by extracting a target area and a target network of the PCB three-dimensional layout model. The method solves the problem of low visibility of a planar two-dimensional layout model in the prior art, and improves the visibility of a PCB model; the problem that the prior art cannot meet the electromagnetic simulation requirement of any target area of a cross-layer network and a PCB (printed Circuit Board) is solved, and the requirement of actual engineering is met.
Description
Technical Field
The invention belongs to the technical field of computers, and further relates to a method for converting an Open database ODB + + (Open Data Base) file into a three-dimensional geometric model in the technical field of Computer Aided Design (CAD). The invention can be applied to the design of three-dimensional electromagnetic modeling in an integrated circuit three-dimensional electromagnetic simulation system.
Background
With higher and higher bandwidths and faster signal edge rates, discontinuities caused by the fine structure of circuit boards and packages in integrated circuits significantly affect the quality of signal transmission. The signal and power integrity problem caused by the method is increasingly serious, so that potential electromagnetic problems in PCB (Printed Circuit Board) layout electromagnetic simulation need to be discovered and corrected in time before plate making. At present, the electromagnetic simulation analysis for the layout is mainly a planar two-dimensional layout, but the two-dimensional layout has the problem of low visibility, and the result precision of the simulation analysis is low. In addition, the PCB data formats of EDA (Electronics Design Automation) systems are not uniform, so that different modeling approaches need to be developed for different PCB data formats.
A patent document applied by the fifty fourth research institute of China electronics technology group company, "a method for converting an ODB + + file into an editable PCB layout" (application date: 2014, 12 and 5 months; application number: 201410734543.6, application publication number: CN 104346502A) discloses a method for converting an ODB + + file into an editable PCB layout. The method comprises the following specific steps: firstly, creating a software platform PLV supporting PCB layout design; secondly, designing a menu interface as an input port of the ODB + + file; thirdly, writing codes by using a C + + high-level language to read ODB + + files everywhere in EDA software; fourthly, screening frame information of the PCB layout according to standard symbols defined by the ODB + + file and storing the frame information into an internal data structure of the PLV of the software platform; fifthly, screening out packaging information, device information network information and text information of a silk-screen layer of the PCB layout according to standard symbols defined by the ODB + + file; and step six, uniformly transferring the obtained PCB layout frame information, packaging information, device information, network information and text information of the silk-screen layer into an internal data structure of the PLV platform, and calling a display function to display the PCB layout which can be selected and edited. The method has two defects: firstly, the planar two-dimensional layout cannot intuitively reflect all details and the whole of the PCB, and one or more cross-layer networks cannot display the details, so that the visibility is very low; secondly, the planar two-dimensional layout can not perform electromagnetic simulation on a cross-layer network and any target area, can only perform simulation on a fixed transmission line, and cannot meet the requirements of actual engineering.
Disclosure of Invention
The invention aims to provide a method for converting an ODB + + file into a three-dimensional geometric model, which aims to solve the problem that three-dimensional geometric modeling cannot be performed on different PCB file formats by using a modeling method, the problem that a planar two-dimensional layout cannot intuitively reflect a PCB cross-layer network structure or the whole PCB layout model, and the problem that the planar two-dimensional layout cannot meet the requirements of electromagnetic simulation on a cross-layer network and any target area.
The technical idea for realizing the purpose of the invention is as follows: the invention adopts ODB + + file to build the three-dimensional geometric model. Because ODB + + can provide intelligent and single data structure, and support the interconversion with the current mainstream PCB data format such as Gerber, IPC-2581. Therefore, based on the data format ODB + +, the problem that three-dimensional geometric modeling cannot be performed on different PCB file formats by using one modeling method can be solved. The invention adopts a plane geometry discrete algorithm, the PCB two-dimensional geometric model is dispersed in the horizontal direction, the discrete data in the vertical direction is calculated according to the discrete data in the horizontal direction and is processed, the construction of the three-dimensional layout model is realized, and the problem of low visibility of the plane two-dimensional layout model in the prior art is solved. The invention adopts a custom cutting technology, generates the three-dimensional geometric model by performing Boolean operation, plane dispersion and rendering on the plane two-dimensional geometric model through cutting of a target area on the PCB three-dimensional layout model and extraction of a target network, and solves the problem that the prior art can not meet the electromagnetic simulation requirements of a cross-layer network and any target area of the PCB. Compared with the prior art that only electromagnetic simulation can be carried out on a fixed plane two-dimensional transmission line, the three-dimensional geometric model constructed by the method can better meet the requirements of actual engineering.
The technical scheme adopted by the invention comprises the following steps:
step 1, respectively building an import interface of an ODB + + compressed file and a three-dimensional display interface of a PCB model;
step 2, screening modeling information required by constructing a PCB two-dimensional geometric model:
step 2.1, selecting a file path for storing the ODB + + compressed file from the created file import interface, decompressing the ODB + + compressed file to obtain the ODB + + file with the structure in the form of a directory tree; designing a data structure for storing layer stacking sequence information and layer attribute information; selecting a storage path of a matrix folder in the ODB + + file, respectively screening out stacking sequence information defining PCB layers and attribute information of each layer from the matrix file under the decompressed matrix folder, and storing the stacking sequence information and the attribute information of the layers into a designed data structure;
step 2.2, designing a data structure for storing and analyzing non-device layer information; selecting a storage path of a layer folder in an ODB + + file, respectively screening graphic information and attribute information of a constructed layer from features files and attrlist files under the decompressed layer folder, and storing the graphic information and the attribute information of the constructed layer into a designed data structure in a classified manner;
step 2.3, designing a data structure for storing and analyzing the device layer information; selecting a file path for storing components in the ODB + + file, respectively screening device information of a top layer and a bottom layer of the PCB from the components files under the decompressed layer folder, and storing the device information of the top layer and the bottom layer into a designed data structure;
step 2.4, designing a data structure for storing the analytic network information and the encapsulation information; selecting a storage path of a steps folder in an ODB + + file, respectively screening out network information and packaging information from data files under the decompressed steps folder, and storing the network information and the packaging information into a designed data structure;
step 3, constructing a three-dimensional layout model of the PCB:
step 3.1, searching the layer stacking sequence and the layer attribute information in a data structure for storing the PCB layer stacking sequence and the layer attribute information, and classifying the layers according to the layer attribute information; determining a starting layer and a terminating layer of the via holes in the classified via hole layers, and respectively allocating via hole information to the metal layer spanned by the via hole information; writing different function interfaces according to different basic graph types of the characteristic data to create basic graphs of the constructed layer, and storing all the basic graphs into a constructed list in a pointer mode; according to the layer name and all basic graph pointer lists on the layer, forming a mapping relation which can be searched bidirectionally between the layer name and the basic graph pointer lists, and obtaining a PCB two-dimensional geometric model constructed according to layers;
step 3.2, searching and storing network information contained in a PCB network information data structure, searching a basic graphic pointer list corresponding to the layer name according to the layer name contained in the network information and the mapping relation between the layer name and all basic graphic pointer lists on the layer, searching a corresponding basic graphic pointer in the searched basic graphic pointer list, and storing the searched basic graphic pointer into the list; according to the network name and the basic graph pointer list, a mapping relation which can be searched in two directions is formed between the network name and the basic graph pointer list, and a PCB two-dimensional geometric model which is constructed according to a network is obtained;
step 3.3, designing a data structure for storing discrete information, adopting a planar grid discrete algorithm to respectively disperse the planar two-dimensional geometric models created according to layers in the horizontal and vertical directions to obtain discrete data of the three-dimensional layout model, and storing the layer names and the discrete data on the layers into the designed data structure;
step 3.4, searching for layer discrete data information in a discrete data structure storing the layer name and the layer, converting the discrete data into renderable graphic data according to different types of the discrete data, and only rendering the line grid by calling a rendering function interface, so that the discrete three-dimensional model data is rendered into a three-dimensional layout model and displayed in a three-dimensional layout model display interface;
step 4, constructing a three-dimensional geometric model of the PCB:
step 4.1, building a custom cutting setting interface of the PCB three-dimensional layout model;
4.2, extracting one or more target networks by selecting the names of the target networks in a menu bar on a three-dimensional layout display interface; setting a custom clipping parameter on a custom clipping setting interface, and performing Boolean operation on a target area and the whole PCB to realize the extraction of the PCB target area;
step 4.3, finding the corresponding graphic pointer through the network name according to the mapping relation between the network name and the basic graphic pointer list; cutting the target area to obtain a graphic pointer of the target area, and writing a function interface to stretch and perform Boolean operation on a two-dimensional plane geometric model pointed by the graphic pointer to realize conversion of a three-dimensional layout model of a target network into a three-dimensional geometric entity model;
and 4.4, dispersing the three-dimensional geometric solid model, converting the dispersed data into renderable graphic data, rendering the graphic data and displaying the graphic data on a display interface of the three-dimensional geometric model.
Compared with the prior art, the invention has the following advantages:
firstly, the invention converts ODB + + data format into three-dimensional parameterized geometric model, and converts mainstream PCB data format such as Gerber, IPC-2581 and the like into ODB + + data format. The problem that different three-dimensional geometric modeling methods need to be developed aiming at different PCB data formats at present is solved, and the three-dimensional geometric modeling efficiency of different PCB data formats is improved.
Secondly, the invention adopts a plane grid discrete algorithm, and the construction of the three-dimensional layout model is realized by dispersing the PCB two-dimensional geometric model in the horizontal direction, calculating the discrete data in the vertical direction according to the discrete data in the horizontal direction and processing the discrete data, thereby improving the visualization of the PCB layout model.
Thirdly, the three-dimensional geometric model is generated by performing Boolean operation, plane dispersion and rendering on the planar two-dimensional geometric model by adopting a custom cutting technology and cutting a target area on the PCB three-dimensional layout model and extracting a target network. Compared with the prior art that only a fixed plane two-dimensional transmission line can be subjected to electromagnetic simulation, the three-dimensional geometric model constructed by the method can better meet the requirements of actual engineering.
Description of the drawings:
FIG. 1 is a flow chart of an implementation of the present invention;
FIG. 2 is a schematic diagram of a three-dimensional layout model of a multilayer PCB generated in the present invention.
FIG. 3 is a schematic diagram of local amplification of a multi-layer PCB three-dimensional layout model generated in the present invention.
Fig. 4 is a schematic diagram of a three-dimensional geometric model of a multilayer PCB generated in the present invention.
The specific implementation mode is as follows:
the invention is described in further detail below with reference to the figures and examples.
The implementation steps of the present invention are further described with reference to fig. 1 and the embodiment.
The invention adopts an ACIS geometric modeling engine and a visualization tool function library VTK to convert the ODB + + file into a three-dimensional geometric model.
Step 1, respectively building an import interface and a model three-dimensional display interface of the ODB + + compressed file.
Step 1.1, the embodiment of the invention adopts a cross-platform C + + graphic user interface application program development framework Qt, and establishes an interface supporting import of ODB + + compressed files by using a high-level programming language C + +.
And 1.2, respectively building two display interfaces of the PCB three-dimensional layout model and the PCB three-dimensional geometric model, wherein the three-dimensional layout model and the three-dimensional geometric model display interface respectively comprise a menu bar and an attribute bar. The embodiment of the invention adopts ODB + + file generated by Cadence software, and because the ODB + + file is an international standard file, the ODB + + file formats exported by EDA software are the same.
And 2, screening modeling information required by constructing a PCB two-dimensional geometric model.
And 2.1, selecting a file path for storing the ODB + + compressed file from the created file import interface, decompressing the ODB + + compressed file to obtain an ODB + + file with a directory tree structure, and decompressing the read compressed file into a specified folder.
And 2.2, screening matrix information related to the stacking sequence of the layers of the PCB layout.
According to the method and the device, the matrix file under the decompressed matrix folder is read, the data structure for storing and analyzing the information of the matrix file is designed, and the obtained stacking sequence information of the layers of the PCB and the attribute information of each layer are stored in the designed data structure. The matrix file is a representation of the product model, where rows are the graph-level tables of the product model and columns are the step-level entities of the product model.
In the embodiment of the invention, because the matrix file is a structured text file, a syntax analyzer generator Bison is adopted to analyze the matrix file under the < product _ model _ name >/matrix/matrix path to obtain the name of the layer and the attribute information of the layer. And taking the layer name as a key value and the layer attribute information as a value, and storing the value in the associated container map under the designed data structure.
And 2.3, screening layer information and device information related to the PCB two-dimensional geometric model.
The method and the device respectively obtain the graphic information and the attribute information of the layers by reading the features file and the attist file in the layers folder after decompression. The features file mainly comprises a symbol table, an attribute name text table and a feature data list. The feature data list includes all the graphic data constituting the layer. The characteristic data is described by a graphic type, and is particularly constructed by basic symbols in a symbol table, such as rectangular rect, circular r, oval or user-defined symbols, wherein the user-defined symbols are described by various features files under symbols. The attrlist file mainly comprises attribute information of the image layer and is divided into a system attribute and a user-defined attribute. And designing a data structure according to the graph type, and classifying and storing the layer characteristic information obtained after analysis according to the layer. The graph types comprise straight lines L, arc lines A, irregular polygons S, pad types P and text types T.
In the embodiment of the present invention, since the features file is a line-recording text file, refer to the layer stacking sequence obtained by analyzing the matrix file in step 2.2. Therefore, the method of reading line by line is adopted to analyze the features files under the path < product _ name >/steps/< step _ name >/layers/< layer _ name >/features and under the path < product _ name >/systems/< system _ name >/features respectively. Creating a Layer type for managing the analyzed Layer information, creating a Symbol type for managing the information of the standard symbols and the user-defined symbols, and creating a Shape type for managing the characteristic data information. The data line of the format UNITS = < MM/INCH > is analyzed, and the reference unit is stored as a reference unit of the feature information data in the member variable under the Layer class. Reading a data value in a $ (n) < Symbol _ type > data < M/I > format after a text line of # Feature Symbol names, obtaining the number, the size and the shape of a standard Symbol for line record reference, and storing the size and the shape of the standard Symbol into a Symbol class. The obtained number is stored as a key value, and a structure object pointer list storing the size and shape of the standard symbol is stored as a value in a C + + relational container map. Reading n and test _ string in the @ (n) < text _ string > format after the text line of the # Feature attribute names can obtain attribute numbers and text character strings for line record reference, and storing the number n as a key value and the test _ string character strings as a value into a C + + associated container map. Finally, reading the characteristic data line after the text line of the # Layer features line by line, and respectively taking the corresponding data information from the map container for storing the symbols and the map container for the attributes according to the index of the characteristic data line. And recombining the fetched data information and storing the data information into member variables under the Shape type. And classifying the obtained feature data information according to the initial character, and storing a Shape type object pointer list into member variables under the Layer type.
The invention obtains the device information of the PCB two-dimensional geometric model by reading the components files in the folders of the top device layer and the bottom device layer after decompression. And designing a data structure of the storage device information, and storing the obtained top-layer device information and bottom-layer device information into the defined data structure.
In the embodiment of the invention, because the components file is a line recording text file, the components file under the path < product _ model _ name >/steps/< step _ name >/layers/< layer _ name >/components is analyzed in a line-by-line reading mode. Creating a Component class to manage the information of the device layer, and storing the number, the attribute, the position and the package number information of the device reference of each device in the top device layer and the bottom device layer after the analysis into the member variable of the Component class.
And 2.4, screening network information and packaging information related to the construction of the PCB two-dimensional geometric model.
The invention obtains the network information and the encapsulation information of the PCB two-dimensional geometric model by reading the data files in the decompressed step file folder. And designing a data structure to store and analyze to obtain network information and packaging information. The data file contains information read directly from the EDA system, including the CAD library and user-defined device packages, the outline and attributes of the device packages, and networking information. And recombining the information obtained by layer analysis according to the analyzed network structure characteristics and the analyzed packaging structure characteristics, and storing the recombined information into a designed data structure.
In the embodiment of the invention, because the data file is a line structure text file, the data file under the < product _ model _ name >/steps/< step _ name >/eda/data path is analyzed in a line-by-line reading mode. Designing the network information after Net type management analysis, designing sub-network information under a Subnet type management network, and designing the characteristic data information under a Fid type management sub-network. And analyzing the data line with the format of LYR < name1> \8230and < name >, and obtaining the layer name and the layer sequence referred by the FID data line in the sub-network. And taking the layer sequence as a key value and the layer name as a value, and storing the values into a C + + associated container map. Analyzing a data line with the format of @ < m > < text _ string >, obtaining an attribute number and an attribute text of network reference, taking the attribute number m as a key value and the test _ string as a value, and storing the key value and the value in a C + + associated container map. And analyzing a data line with a format of # & < n > < attribute _ name > to obtain an attribute name number and an attribute name, taking the attribute name number as a key value, taking the attribute name as a value, and storing the value into a C + + associated container map. Analyzing a data line with a format of # NET < x > to obtain the serial number of the current network, wherein the data line with the format of # NET < NET _ name >; < attributes >; and analyzing a data line with the ID = < ID > to obtain the name, the attribute and the unique identifier of the current network, and storing the obtained information into a member variable of the Net class. The type and the number of the current sub-network are obtained by analyzing the data line beginning with the SNT through traversing the sub-networks under the current network, and the obtained information of the type and the number of the sub-network is stored in member variables of the Subnet class. The method comprises the steps of analyzing data rows with the format of FID < type > < lyr _ num > < f _ num > under a sub-network by traversing FID data rows under a current sub-network, storing the obtained type and the feature data of the feature data, the corresponding layer name and the number of the feature data into member variables of a FID class, and storing an object pointer of the FID class into the member variables of the current Subnet class until the traversal of the current sub-network is finished. And storing the current Subnet class object pointer into the member variable of the current Net class until the current network traversal is finished. In the embodiment of the invention, a Package class is designed to manage the device Package information obtained by analyzing the data file. Since the component file is parsed in step 2.3 to obtain the device package number information referenced by the device, the data segment beginning with the PKG is parsed to obtain the graphic shape describing the device on the PCB. And analyzing the data segment at the beginning of the PIN to obtain the information of the PIN in the current device package, wherein the PIN information comprises the name, the type, the position and the shape of the PIN. The information of the device package and the pin information together constitute the package information of the PCB. Each PKG and PIN data line is followed by one or more profile records that describe the shape of the device and PINs. And storing the obtained pin information into a member variable of a Package class, taking the number of the device Package as a key value, taking a Package class object pointer as a value, and storing the key value and the value into a C + + associated container map.
And 3, constructing a three-dimensional layout model of the PCB.
The constructed three-dimensional layout model of the PCB is further described with reference to fig. 2.
The invention screens and constructs the information of the PCB two-dimensional geometric model according to the step 2, and constructs the PCB two-dimensional geometric model according to two division modes of layers and networks. The discrete data of the three-dimensional geometric model is generated by dispersing the constructed PCB two-dimensional geometric model, and the generated discrete data of the three-dimensional geometric model is converted into renderable graphic data. In order to improve the rendering efficiency, only the discrete line grids are displayed by calling an interface of a rendering function, so that the discrete three-dimensional geometric model data are rendered into a three-dimensional layout model and displayed in a built three-dimensional layout model display interface. Fig. 3 is a partially enlarged view of the lower left corner of the three-dimensional geometric layout model of the multilayer PCB generated in fig. 2.
And 3.1, establishing a two-dimensional geometric model according to layers.
According to the layer sequence specified by the matrix file, the invention classifies the layers according to the layer attributes, such as the layer attributes of a metal layer, a dielectric layer, a drilling layer, a device layer and the like. After determining the starting layer and the terminating layer of the via hole, respectively allocating via hole information such as the size of the via hole, the shape of the via hole and point location information of the center of the via hole to the metal layer spanned by the via hole according to the type of the via hole such as a through hole, a buried hole and a blind hole. And searching and storing the layer stacking sequence and the layer attribute information in the PCB layer stacking sequence and layer attribute information data structure, compiling different function interfaces according to different basic graph types of the characteristic data to create basic graphs for constructing layers, and storing all the basic graphs into a constructed list in a pointer mode. And forming a mapping relation which can be searched in two directions by the layer name and the basic graph pointer list according to the layer name and all the basic graph pointer lists on the layer, and obtaining the PCB two-dimensional geometric model constructed according to layers.
In the embodiment of the invention, the layer information and the symbol information in the data structure for storing the layer information, the basic symbol and the user-defined symbol are searched. According to different basic graph types, such as a straight line L, an arc line A, a pad shape P and a polygon S, different function interfaces are programmed to realize the creation of the basic graph. The basic graph is determined by the symbol shape and point location information, application program interfaces of different ACIS geometric shapes are called by C + +, function interfaces for creating symbols and basic primitives are written, and the created symbols and basic primitives are operated, such as sweep, boolean union operation and Boolean reduction operation, so that feature data are converted into a two-dimensional geometric model. The polygon S is formed without basic symbols and user-defined symbols and only formed by connecting straight lines and arc lines without widths end to end, and has the characteristics of closing and not selfing. Therefore, special processing needs to be carried out on the polygon, a multi-segment closed line is created by calling api _ mk _ ed _ line and api _ current _ arc _3pt, and then api _ make _ ewire and api _ cover _ wire functions are called to carry out end-to-end connection on the closed line and fill the closed line into a two-dimensional plane. And traversing member variables in the Component class for storing the device information to obtain the name, the attribute and the type of the device and the number information of the device package referenced by the device. And (4) according to the packaging information analyzed in the step (2.4), taking the number of the quoted device package as a retrieval condition, and acquiring shape information describing the device. Since the information describing the device is the same as the data structure describing the polygon facets, the shape information describing the device is parsed in a manner of parsing the polygon. The name of the device is used as a key value, the obtained graphic pointer describing the shape of the device is used as a value, and the value is stored in a C + + associative container map in a key value-pair mode.
And 3.2, creating a two-dimensional geometric model according to the network.
According to the network information obtained by analyzing the data file, the network is functionally divided into a power supply/ground network and a non-power supply/ground network through different attributes of characteristic data information contained in the network.
And according to the characteristic data information contained in each network, obtaining a PCB two-dimensional geometric model constructed according to the network according to the mapping relation between the layer name in the step 3.1 and all basic graphic pointer lists on the layer.
In the embodiment of the invention, the layer name is searched in the map container storing the reference layer information by acquiring the member variable under the Net type and according to the reference layer number contained in the FID data line and the corresponding feature data number in the reference layer. And 3, taking the layer name as a retrieval condition, and searching a corresponding basic graphic pointer list according to the layer name in the associated container map in the step 3.1. And searching the basic graphic pointer which is created in the step 3.1 and corresponds to the serial number of the characteristic data as a searching condition. And taking the network name as a key value, taking all basic graphic pointer lists under one network as value values, and storing the value values into the C + + associated container map. And forming a mapping relation which can be searched bidirectionally for the network name and the basic graph pointer list according to the network name and the basic graph pointer list to obtain a PCB two-dimensional geometric model constructed according to the network.
And 3.3, performing data dispersion on the two-dimensional geometric model created according to layers.
The invention adopts a plane discrete grid algorithm to carry out the dispersion on the plane two-dimensional geometric model established by layers in the step 3.1. And the two-dimensional geometric model of the plane is dispersed in the horizontal direction, so that unnecessary data is simplified and compressed. Because the patch data are the same in the vertical direction of the PCB three-dimensional layout model, the patch data in the vertical direction can be directly calculated by stretching the discrete data in the horizontal direction in the height direction.
In the embodiment of the invention, the DisplayMesh class is written to manage the dispersed data. And traversing the map container storing the layers and the graphic pointer list in the step 3.1, and traversing the graphic pointer list vector corresponding to each layer. And writing a function interface MeshEntity of the discrete plane two-dimensional geometric model by using C + +, taking a graphic pointer as a function entry parameter, and taking a DisplayMesh class object pointer as a function exit parameter. According to the type of the graph pointed by the graph pointer, two function interfaces, namely api _ get _ faces and api _ get _ edges, of the ACIS application program interface are called respectively to obtain the Face (Face) or the Edge (Edge) of the pointed graph, and the obtained Face and Edge are stored in a C + + list container. Writing a function interface get _ triangles _ from _ failed _ face by using C + +, taking a list container for storing all surface data of the graph as function input parameters, taking a DisplayMesh class object pointer as function output parameters, and obtaining vertex coordinates of a discrete surface, triangular meshes of the discrete surface and normal coordinates of the discrete surface. And taking list containers for storing all edges of the graph as function parameters, taking the DisplayMesh object pointer as function parameters, and adopting a Delaunay discrete algorithm to obtain the line grids after line segment dispersion and the edge vertex coordinates. After the horizontal discrete data are obtained, the GetVerticalMeshData function interface is compiled, the stack thickness and the DisplayMesh class object pointer obtained in the step 2.3 are used as function parameters, and triangular grid data and line segment discrete data in the vertical direction are obtained. And calculating the discrete data of the discrete surface to the vertical surface according to the symmetry, thereby expanding the plane two-dimensional layout model data to the three-dimensional layout model discrete data, and replacing the plane two-dimensional layout model data under the DisplayMesh member variable with the obtained three-dimensional layout model data. The layer name is used as a key value, the DisplayMesh class object is stored in a vector of a sequence type container, the vector is used as a value, and the value is stored in a C + + associated container map in a key value-pair mode.
And 3.4, rendering and displaying the generated three-dimensional layout model.
The method and the system traverse the map container for storing the discrete data of the three-dimensional layout model, and convert the discrete data into the graphic data for constructing the three-dimensional layout according to different data types. And calling a function interface for rendering graphic data to render the generated planar two-dimensional geometric model, so that the planar two-dimensional geometric model is converted into a three-dimensional layout model and is displayed in a three-dimensional layout model interface.
In the embodiment of the invention, a function interface of a visualization tool function library VTK is adopted to convert and render the discrete data. And traversing the map container storing the three-dimensional discrete data in the step 3.3, and converting the discrete data into a vtkPolyData data structure. The conversion from graphics data to rendering primitives is achieved by defining vtkPolyDataMapper objects for receiving vtkPolyData data. The vtkActor object is created to describe a rendering primitive in a scene. And (3) by creating a Render object, introducing the vtkActor object into an AddActor function as a function input parameter, realizing rendering of the three-dimensional layout model after dispersion, and sequentially storing the Render object of the final rendered graph into a C + + sequence type container vector. And storing the layer name as a key value and the vetcor container storing the Render object as a value into a C + + associated container map in a key value-pair mode to realize one-to-one mapping of the layer name and the rendered model. Traversing the map container storing the network information in the step 3.2, remapping the map container storing the network information according to the one-to-one correspondence relationship between the basic graphic pointer list and the vector container storing the Render object, and realizing that the basic graphic pointer list and the list storing the Render object can be respectively found from the network name. Traversing a map container for storing the layer names and the rendering model object list, and calling the object of the three-dimensional layout model display interface built in the step 1 to realize the rendering display of the whole PCB three-dimensional layout model.
And 4, constructing a three-dimensional geometric model of the PCB.
Extracting a target network or cutting a target area, and establishing a three-dimensional geometric model for the extracted target network or target area.
The constructed three-dimensional geometric model of the PCB is further described with reference to fig. 4.
According to the invention, the free cutting of the PCB target area is realized by building the user-defined cutting setting interface and the set user-defined cutting parameters. And after extracting the three-dimensional layout model of the target network or the target area, searching a two-dimensional plane geometric model corresponding to the three-dimensional layout model through the mapping relation between the network name and the basic graphic pointer. And stretching and Boolean operation are carried out on the two-dimensional plane geometric model, so that the two-dimensional plane geometric model is converted into a three-dimensional geometric solid model. And performing surface dispersion on the three-dimensional geometric solid model, converting the dispersed data into renderable graphic data, calling the created rendering function interface to render the graphic data, and displaying in a three-dimensional geometric model display interface.
And 4.1, building a cutting setting interface.
The invention adopts the self-cutting technology to realize the free cutting of the PCB three-dimensional layout model. And setting up an interface for cutting the three-dimensional layout model, and realizing free cutting of the target area on the PCB by setting the parameters of custom cutting.
In the embodiment of the invention, a C + + graphical user interface application program development framework Qt of a cross-platform is adopted, and a three-dimensional layout model cutting interface is built by using a C + + language. The network name which needs to be reserved in the user-defined area is selected, user-defined cutting parameters such as extension distance and corner shape are set, and the size and the shape of the cutting target area can be determined according to the size and the shape of the signal network reserved in the area signal.
And 4.2, extracting a target network or a target area and carrying out three-dimensional geometric modeling on the target network or the target area.
In an embodiment of the invention, a data structure is created that stores a model of a generated three-dimensional geometric solid. The extraction of the target network can be realized through the selection of the network name on the three-dimensional layout model display interface. And the graphic pointer corresponding to the three-dimensional layout model of the target network can be searched through the mapping relation between the layer name and the basic graphic pointer list, which can be searched in two directions, and the mapping relation between the network name and the basic graphic pointer list, which can be searched in two directions. And writing an export ToGeometry function by C + +, using the searched basic graph pointer list as a function entry parameter, and calling an application program function interface in an ACIS geometric modeling engine to realize stretching and Boolean operation on the planar geometric model. And converting the plane two-dimensional model into a three-dimensional geometric solid model through stretching and Boolean operation, and storing the generated three-dimensional solid model pointer into a designed data structure. Wherein the application program function interface of Boolean operation is like api _ unite, to realize Boolean operation; the function interface of model stretching is api _ sweep _ eith _ options.
And 4.3, dispersing and rendering the three-dimensional geometric solid model.
In the embodiment of the invention, since only the two-dimensional geometric model of the plane is discretized in the step 3.3, the discrete data in the vertical direction is calculated by stretching. The three-dimensional geometric solid model is discrete, so that not only the upper and lower parallel surfaces are discrete, but also the surfaces in the vertical direction are discrete. The more irregular the model is, the larger the discrete data is, so that if a three-dimensional geometric solid model has a large number of fine structures through Boolean operation, the discrete efficiency is greatly reduced. And 3.3, performing surface discretization on the generated three-dimensional geometric solid model by calling the surface discretization interface written in the step 3.3, and creating a DisplayMesh class object to manage the discretized grid data. And converting the generated discrete data into renderable graphic data, and displaying the generated PCB three-dimensional model in a display interface of the three-dimensional geometric model by calling the rendering interface written in the step 3.4.
Claims (6)
1. A method for converting an ODB + + file into a three-dimensional geometric model is characterized in that information related to PCB modeling is read and processed according to the standard of the ODB + + file, a three-dimensional layout model of a PCB is built, and the three-dimensional geometric model of the PCB is built by extracting a target area and a target network of the three-dimensional layout model of the PCB; the steps of the conversion method include the following:
step 1, respectively building an import interface of an ODB + + compressed file and a three-dimensional display interface of a PCB model;
step 2, screening modeling information required by constructing a PCB two-dimensional geometric model:
step 2.1, selecting a file path for storing the ODB + + compressed file from the created file import interface, decompressing the ODB + + compressed file to obtain the ODB + + file with the structure in the form of a directory tree; designing a data structure for storing layer stacking sequence information and layer attribute information; selecting a storage path of a matrix folder in the ODB + + file, respectively screening out stacking sequence information defining PCB layers and attribute information of each layer from the matrix file under the decompressed matrix folder, and storing the stacking sequence information and the attribute information of the layers into a designed data structure;
step 2.2, designing a data structure for storing and analyzing non-device layer information; selecting a storage path of a layer folder in an ODB + + file, respectively screening graphic information and attribute information of a constructed layer from features files and attrlist files under the decompressed layer folder, and storing the graphic information and the attribute information of the constructed layer into a designed data structure in a classified manner;
step 2.3, designing a data structure for storing and analyzing the device layer information; selecting a file path for storing components in the ODB + + file, respectively screening the component information of the top layer and the bottom layer of the PCB from the components file under the decompressed layer folder, and storing the component information of the top layer and the bottom layer into a designed data structure;
step 2.4, designing a data structure for storing the analytic network information and the encapsulation information; selecting a storage path of a steps folder in the ODB + + file, respectively screening out network information and packaging information from data files under the decompressed steps folder, and storing the network information and the packaging information into a designed data structure;
step 3, constructing a three-dimensional layout model of the PCB:
step 3.1, searching the layer stacking sequence and the layer attribute information in a data structure for storing the PCB layer stacking sequence and the layer attribute information, and classifying the layers according to the layer attribute information; determining a starting layer and a terminating layer of the via holes in the classified via hole layers, and respectively allocating via hole information to the metal layer spanned by the via hole information; writing different function interfaces according to different basic graph types of the characteristic data to create basic graphs of the constructed layer, and storing all the basic graphs into a constructed list in a pointer mode; according to the layer name and all basic graph pointer lists on the layer, forming a mapping relation which can be searched bidirectionally between the layer name and the basic graph pointer lists, and obtaining a PCB two-dimensional geometric model constructed according to layers;
step 3.2, searching and storing network information contained in a PCB network information data structure, searching a basic graph pointer list corresponding to the layer name according to the layer name contained in the network information and the mapping relation between the layer name and all basic graph pointer lists on the layer, searching a corresponding basic graph pointer in the searched basic graph pointer list, and storing the searched basic graph pointer into the list; according to the network name and the basic graph pointer list, forming a mapping relation which can be searched in two directions by the network name and the basic graph pointer list, and obtaining a PCB two-dimensional geometric model constructed according to a network;
step 3.3, designing a data structure for storing discrete information, adopting a planar grid discrete algorithm to respectively disperse the planar two-dimensional geometric models created according to layers in the horizontal and vertical directions to obtain discrete data of the three-dimensional layout model, and storing the layer names and the discrete data on the layers into the designed data structure;
step 3.4, searching for layer discrete data information in a discrete data structure storing the layer name and the layer, converting the discrete data into renderable graphic data according to different types of the discrete data, and only rendering the line grid by calling a rendering function interface, so that the discrete three-dimensional model data is rendered into a three-dimensional layout model and displayed in a three-dimensional layout model display interface;
step 4, constructing a three-dimensional geometric model of the PCB:
step 4.1, building a custom cutting setting interface of the PCB three-dimensional layout model;
4.2, extracting one or more target networks by selecting the target network names in a menu bar on the three-dimensional layout display interface; setting a custom clipping parameter on a custom clipping setting interface, and performing Boolean operation on a target area and the whole PCB to realize the extraction of the PCB target area;
step 4.3, finding out the corresponding graphic pointer through the network name according to the mapping relation between the network name and the basic graphic pointer list; cutting the target area to obtain a graphic pointer of the target area, and writing a function interface to stretch and perform Boolean operation on a two-dimensional plane geometric model pointed by the graphic pointer to realize conversion of a three-dimensional layout model of a target network into a three-dimensional geometric entity model;
and 4.4, dispersing the three-dimensional geometric solid model, converting the dispersed data into renderable graphic data, rendering the graphic data and displaying the graphic data on a display interface of the three-dimensional geometric model.
2. The method for converting an ODB + + file into a three-dimensional geometric model according to claim 1, wherein the step 2.1 of designing and storing the data structure of the layer stacking order information and the layer attribute information includes: and designing a matrix data type to store matrix information, designing a LayerRecord structure body to store attribute information of the layer, wherein the stacking sequence of the layer and the pointer of the LayerRecord structure body are member variables of the matrix data type.
3. The method for converting an ODB + + file into a three-dimensional geometric model according to claim 1, wherein the step 2.2 of designing a data structure for storing parsed non-device layer information comprises: designing LayerDataStore types to store layer information and layer attribute information of devices and non-device layers, designing Features Parser types to analyze non-device layer information, designing Features DataStore types to store non-device layer information, and designing Attrlist Parser types to store attrlist file information; the FeatureDataStore class object pointer is used as a member variable of the FeatureDataStore class, and the FeatureDataStore class object pointer and the AttrlistParser class object pointer are used as member variables of the LayerDataStore class.
4. The method for converting an ODB + + file into a three-dimensional geometric model according to claim 1, wherein the step 2.3 of designing a data structure for storing device layer information includes: designing ComponentScarser type analysis device layer information, designing ComponentsDataStore type storage device layer information, taking a ComponentScarsersers type object pointer as a member variable of ComponentsDataStore type, and taking a ComponentsDataStore type object pointer as a member variable of LayerDataStore type.
5. The method for converting an ODB + + file into a three-dimensional geometric model according to claim 1, wherein the step 2.4 of designing a data structure for storing parsing network information and encapsulation information includes: designing StepEdaDataStore type storage data file information, designing Net type storage network information, designing SubNet type storage sub-network information and designing Fid type storage network characteristic data information; taking the Fid class object pointer as a member variable of a sub Net class, and taking the sub Net class object pointer as a member variable of the Net class; designing a Package type to store packaging information, designing a Pin type to store information of a Pin, designing an OutlineRecord structure to store information of a Pin or a device outline, respectively using an indicator of the OutlineRecord structure as member variables of the Pin and the Package type, and using the Pin type as a member variable of the Package type.
6. The method for converting an ODB + + based file into a three-dimensional geometric model according to claim 1, wherein said designing a data structure storing discrete information in step 3.3 comprises: designing a DisplayMesh class to store scattered data information, designing grid discrete data of a storage surface of a FaceMesh structure, designing grid discrete data of a storage edge of an EdgeMesh structure, designing a DisplayData structure to store discrete vertex information, and taking a FaceMesh structure object pointer and an EdgeMesh structure object pointer as member variables of the DiplayMesh class.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116050015A (en) * | 2023-01-28 | 2023-05-02 | 西南应用磁学研究所(中国电子科技集团公司第九研究所) | Automatic modeling and layout checking method for multi-layer chip device |
| CN116090405A (en) * | 2023-03-23 | 2023-05-09 | 深圳前海硬之城信息技术有限公司 | Three-dimensional simulation method, device, equipment and storage medium |
| CN117892674A (en) * | 2024-03-15 | 2024-04-16 | 芯瑞微(上海)电子科技有限公司 | Conversion method for converting ODB++ format file of PCB into XFL format file |
| CN117931739A (en) * | 2024-03-22 | 2024-04-26 | 上海合见工业软件集团有限公司 | PCB design data conversion method, device, equipment and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116050015A (en) * | 2023-01-28 | 2023-05-02 | 西南应用磁学研究所(中国电子科技集团公司第九研究所) | Automatic modeling and layout checking method for multi-layer chip device |
| CN116090405A (en) * | 2023-03-23 | 2023-05-09 | 深圳前海硬之城信息技术有限公司 | Three-dimensional simulation method, device, equipment and storage medium |
| CN116090405B (en) * | 2023-03-23 | 2023-09-12 | 深圳前海硬之城信息技术有限公司 | Three-dimensional simulation method, device, equipment and storage medium |
| CN117892674A (en) * | 2024-03-15 | 2024-04-16 | 芯瑞微(上海)电子科技有限公司 | Conversion method for converting ODB++ format file of PCB into XFL format file |
| CN117892674B (en) * | 2024-03-15 | 2024-05-28 | 芯瑞微(上海)电子科技有限公司 | Conversion method for converting ODB++ format file of PCB into XFL format file |
| CN117931739A (en) * | 2024-03-22 | 2024-04-26 | 上海合见工业软件集团有限公司 | PCB design data conversion method, device, equipment and medium |
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